2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define MIPS_DEBUG_DISAS
25 /*****************************************************************************/
26 /* Exceptions processing helpers */
27 void cpu_loop_exit(void)
29 longjmp(env->jmp_env, 1);
32 __attribute__ (( regparm(2) ))
33 void do_raise_exception_err (uint32_t exception, int error_code)
36 if (logfile && exception < 0x100)
37 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
39 env->exception_index = exception;
40 env->error_code = error_code;
45 __attribute__ (( regparm(1) ))
46 void do_raise_exception (uint32_t exception)
48 do_raise_exception_err(exception, 0);
51 #define MEMSUFFIX _raw
52 #include "op_helper_mem.c"
54 #if !defined(CONFIG_USER_ONLY)
55 #define MEMSUFFIX _user
56 #include "op_helper_mem.c"
58 #define MEMSUFFIX _kernel
59 #include "op_helper_mem.c"
63 /* 64 bits arithmetic for 32 bits hosts */
64 #if (HOST_LONG_BITS == 32)
65 static inline uint64_t get_HILO (void)
67 return ((uint64_t)env->HI << 32) | (uint64_t)env->LO;
70 static inline void set_HILO (uint64_t HILO)
72 env->LO = HILO & 0xFFFFFFFF;
78 set_HILO((int64_t)T0 * (int64_t)T1);
83 set_HILO((uint64_t)T0 * (uint64_t)T1);
90 tmp = ((int64_t)T0 * (int64_t)T1);
91 set_HILO((int64_t)get_HILO() + tmp);
98 tmp = ((uint64_t)T0 * (uint64_t)T1);
99 set_HILO(get_HILO() + tmp);
106 tmp = ((int64_t)T0 * (int64_t)T1);
107 set_HILO((int64_t)get_HILO() - tmp);
114 tmp = ((uint64_t)T0 * (uint64_t)T1);
115 set_HILO(get_HILO() - tmp);
120 __attribute__ (( regparm(2) ))
121 void do_mfc0 (int reg, int sel)
123 const unsigned char *rn;
125 if (sel != 0 && reg != 16 && reg != 28) {
135 T0 = cpu_mips_get_random(env);
139 T0 = env->CP0_EntryLo0;
143 T0 = env->CP0_EntryLo1;
147 T0 = env->CP0_Context;
151 T0 = env->CP0_PageMask;
159 T0 = env->CP0_BadVAddr;
163 T0 = cpu_mips_get_count(env);
167 T0 = env->CP0_EntryHi;
171 T0 = env->CP0_Compare;
175 T0 = env->CP0_Status;
176 if (env->hflags & MIPS_HFLAG_UM)
177 T0 |= (1 << CP0St_UM);
178 if (env->hflags & MIPS_HFLAG_ERL)
179 T0 |= (1 << CP0St_ERL);
180 if (env->hflags & MIPS_HFLAG_EXL)
181 T0 |= (1 << CP0St_EXL);
199 T0 = env->CP0_Config0;
203 T0 = env->CP0_Config1;
207 rn = "Unknown config register";
212 T0 = env->CP0_LLAddr >> 4;
216 T0 = env->CP0_WatchLo;
220 T0 = env->CP0_WatchHi;
225 if (env->hflags & MIPS_HFLAG_DM)
240 T0 = env->CP0_DataLo;
249 T0 = env->CP0_ErrorEPC;
253 T0 = env->CP0_DESAVE;
261 #if defined MIPS_DEBUG_DISAS
262 if (loglevel & CPU_LOG_TB_IN_ASM) {
263 fprintf(logfile, "%08x mfc0 %s => %08x (%d %d)\n",
264 env->PC, rn, T0, reg, sel);
270 __attribute__ (( regparm(2) ))
271 void do_mtc0 (int reg, int sel)
273 const unsigned char *rn;
274 uint32_t val, old, mask;
277 if (sel != 0 && reg != 16 && reg != 28) {
285 val = (env->CP0_index & 0x80000000) | (T0 & 0x0000000F);
286 old = env->CP0_index;
287 env->CP0_index = val;
291 val = T0 & 0x03FFFFFFF;
292 old = env->CP0_EntryLo0;
293 env->CP0_EntryLo0 = val;
297 val = T0 & 0x03FFFFFFF;
298 old = env->CP0_EntryLo1;
299 env->CP0_EntryLo1 = val;
303 val = (env->CP0_Context & 0xFF000000) | (T0 & 0x00FFFFF0);
304 old = env->CP0_Context;
305 env->CP0_Context = val;
309 val = T0 & 0x01FFE000;
310 old = env->CP0_PageMask;
311 env->CP0_PageMask = val;
315 val = T0 & 0x0000000F;
316 old = env->CP0_Wired;
317 env->CP0_Wired = val;
322 old = cpu_mips_get_count(env);
323 cpu_mips_store_count(env, val);
327 val = T0 & 0xFFFFF0FF;
328 old = env->CP0_EntryHi;
329 env->CP0_EntryHi = val;
334 old = env->CP0_Compare;
335 cpu_mips_store_compare(env, val);
339 val = T0 & 0xFA78FF01;
340 if (T0 & (1 << CP0St_UM))
341 env->hflags |= MIPS_HFLAG_UM;
343 env->hflags &= ~MIPS_HFLAG_UM;
344 if (T0 & (1 << CP0St_ERL))
345 env->hflags |= MIPS_HFLAG_ERL;
347 env->hflags &= ~MIPS_HFLAG_ERL;
348 if (T0 & (1 << CP0St_EXL))
349 env->hflags |= MIPS_HFLAG_EXL;
351 env->hflags &= ~MIPS_HFLAG_EXL;
352 old = env->CP0_Status;
353 env->CP0_Status = val;
354 /* If we unmasked an asserted IRQ, raise it */
356 if (loglevel & CPU_LOG_TB_IN_ASM) {
357 fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
358 old, val, env->CP0_Cause, old & mask, val & mask,
359 env->CP0_Cause & mask);
362 if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
363 !(env->hflags & MIPS_HFLAG_EXL) &&
364 !(env->hflags & MIPS_HFLAG_ERL) &&
365 !(env->hflags & MIPS_HFLAG_DM) &&
366 (env->CP0_Status & env->CP0_Cause & mask)) {
368 fprintf(logfile, "Raise pending IRQs\n");
369 env->interrupt_request |= CPU_INTERRUPT_HARD;
370 do_raise_exception(EXCP_EXT_INTERRUPT);
371 } else if (!(val & 0x00000001) && (old & 0x00000001)) {
372 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
378 val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300);
379 old = env->CP0_Cause;
380 env->CP0_Cause = val;
382 /* Check if we ever asserted a software IRQ */
383 for (i = 0; i < 2; i++) {
385 if ((val & mask) & !(old & mask))
400 #if defined(MIPS_USES_R4K_TLB)
401 val = (env->CP0_Config0 & 0x8017FF80) | (T0 & 0x7E000001);
403 val = (env->CP0_Config0 & 0xFE17FF80) | (T0 & 0x00000001);
405 old = env->CP0_Config0;
406 env->CP0_Config0 = val;
412 rn = "bad config selector";
418 old = env->CP0_WatchLo;
419 env->CP0_WatchLo = val;
423 val = T0 & 0x40FF0FF8;
424 old = env->CP0_WatchHi;
425 env->CP0_WatchHi = val;
429 val = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
430 if (T0 & (1 << CP0DB_DM))
431 env->hflags |= MIPS_HFLAG_DM;
433 env->hflags &= ~MIPS_HFLAG_DM;
434 old = env->CP0_Debug;
435 env->CP0_Debug = val;
447 val = T0 & 0xFFFFFCF6;
448 old = env->CP0_TagLo;
449 env->CP0_TagLo = val;
461 old = env->CP0_ErrorEPC;
462 env->CP0_ErrorEPC = val;
467 old = env->CP0_DESAVE;
468 env->CP0_DESAVE = val;
478 #if defined MIPS_DEBUG_DISAS
479 if (loglevel & CPU_LOG_TB_IN_ASM) {
480 fprintf(logfile, "%08x mtc0 %s %08x => %08x (%d %d %08x)\n",
481 env->PC, rn, T0, val, reg, sel, old);
488 #if defined(MIPS_USES_R4K_TLB)
489 __attribute__ (( regparm(1) ))
490 static void invalidate_tb (int idx)
493 target_ulong addr, end;
495 tlb = &env->tlb[idx];
498 end = addr + (tlb->end - tlb->VPN);
499 tb_invalidate_page_range(addr, end);
503 end = addr + (tlb->end - tlb->VPN);
504 tb_invalidate_page_range(addr, end);
508 __attribute__ (( regparm(1) ))
509 static void fill_tb (int idx)
514 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
515 tlb = &env->tlb[idx];
516 tlb->VPN = env->CP0_EntryHi & 0xFFFFE000;
517 tlb->ASID = env->CP0_EntryHi & 0x000000FF;
518 size = env->CP0_PageMask >> 13;
519 size = 4 * (size + 1);
520 tlb->end = tlb->VPN + (1 << (8 + size));
521 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
522 tlb->V[0] = env->CP0_EntryLo0 & 2;
523 tlb->D[0] = env->CP0_EntryLo0 & 4;
524 tlb->C[0] = (env->CP0_EntryLo0 >> 3) & 0x7;
525 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
526 tlb->V[1] = env->CP0_EntryLo1 & 2;
527 tlb->D[1] = env->CP0_EntryLo1 & 4;
528 tlb->C[1] = (env->CP0_EntryLo1 >> 3) & 0x7;
529 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
534 /* Wildly undefined effects for CP0_index containing a too high value and
535 MIPS_TLB_NB not being a power of two. But so does real silicon. */
536 invalidate_tb(env->CP0_index & (MIPS_TLB_NB - 1));
537 fill_tb(env->CP0_index & (MIPS_TLB_NB - 1));
542 int r = cpu_mips_get_random(env);
555 tag = (env->CP0_EntryHi & 0xFFFFE000);
556 ASID = env->CP0_EntryHi & 0x000000FF;
557 for (i = 0; i < MIPS_TLB_NB; i++) {
559 /* Check ASID, virtual page number & size */
560 if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
566 if (i == MIPS_TLB_NB) {
567 env->CP0_index |= 0x80000000;
576 tlb = &env->tlb[env->CP0_index & (MIPS_TLB_NB - 1)];
577 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
578 size = (tlb->end - tlb->VPN) >> 12;
579 env->CP0_PageMask = (size - 1) << 13;
580 env->CP0_EntryLo0 = tlb->V[0] | tlb->D[0] | (tlb->C[0] << 3) |
582 env->CP0_EntryLo1 = tlb->V[1] | tlb->D[1] | (tlb->C[1] << 3) |
587 __attribute__ (( regparm(1) ))
588 void op_dump_ldst (const unsigned char *func)
591 fprintf(logfile, "%s => %08x %08x\n", __func__, T0, T1);
597 fprintf(logfile, "%s %08x at %08x (%08x)\n", __func__,
598 T1, T0, env->CP0_LLAddr);
602 void debug_eret (void)
605 fprintf(logfile, "ERET: pc %08x EPC %08x ErrorEPC %08x (%d)\n",
606 env->PC, env->CP0_EPC, env->CP0_ErrorEPC,
607 env->hflags & MIPS_HFLAG_ERL ? 1 : 0);
611 __attribute__ (( regparm(1) ))
612 void do_pmon (int function)
616 case 2: /* TODO: char inbyte(int waitflag); */
617 if (env->gpr[4] == 0)
620 case 11: /* TODO: char inbyte (void); */
625 printf("%c", env->gpr[4] & 0xFF);
631 unsigned char *fmt = (void *)env->gpr[4];