2 * MIPS emulation micro-operations for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #define CALL_FROM_TB0(func) func();
29 #define CALL_FROM_TB1(func, arg0) func(arg0);
31 #ifndef CALL_FROM_TB1_CONST16
32 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
35 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
37 #ifndef CALL_FROM_TB2_CONST16
38 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
39 CALL_FROM_TB2(func, arg0, arg1);
42 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
45 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
46 func(arg0, arg1, arg2, arg3);
50 #include "op_template.c"
53 #include "op_template.c"
56 #include "op_template.c"
59 #include "op_template.c"
62 #include "op_template.c"
65 #include "op_template.c"
68 #include "op_template.c"
71 #include "op_template.c"
74 #include "op_template.c"
77 #include "op_template.c"
80 #include "op_template.c"
83 #include "op_template.c"
86 #include "op_template.c"
89 #include "op_template.c"
92 #include "op_template.c"
95 #include "op_template.c"
98 #include "op_template.c"
101 #include "op_template.c"
104 #include "op_template.c"
107 #include "op_template.c"
110 #include "op_template.c"
113 #include "op_template.c"
116 #include "op_template.c"
119 #include "op_template.c"
122 #include "op_template.c"
125 #include "op_template.c"
128 #include "op_template.c"
131 #include "op_template.c"
134 #include "op_template.c"
137 #include "op_template.c"
140 #include "op_template.c"
144 #include "op_template.c"
147 #include "op_template.c"
150 #include "op_template.c"
157 #include "fop_template.c"
161 #include "fop_template.c"
165 #include "fop_template.c"
169 #include "fop_template.c"
173 #include "fop_template.c"
177 #include "fop_template.c"
181 #include "fop_template.c"
185 #include "fop_template.c"
189 #include "fop_template.c"
193 #include "fop_template.c"
197 #include "fop_template.c"
201 #include "fop_template.c"
205 #include "fop_template.c"
209 #include "fop_template.c"
213 #include "fop_template.c"
217 #include "fop_template.c"
221 #include "fop_template.c"
225 #include "fop_template.c"
229 #include "fop_template.c"
233 #include "fop_template.c"
237 #include "fop_template.c"
241 #include "fop_template.c"
245 #include "fop_template.c"
249 #include "fop_template.c"
253 #include "fop_template.c"
257 #include "fop_template.c"
261 #include "fop_template.c"
265 #include "fop_template.c"
269 #include "fop_template.c"
273 #include "fop_template.c"
277 #include "fop_template.c"
281 #include "fop_template.c"
285 #include "fop_template.c"
290 void op_dup_T0 (void)
296 void op_load_HI (void)
302 void op_store_HI (void)
308 void op_load_LO (void)
314 void op_store_LO (void)
321 #define MEMSUFFIX _raw
324 #if !defined(CONFIG_USER_ONLY)
325 #define MEMSUFFIX _user
329 #define MEMSUFFIX _kernel
347 if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) {
348 /* operands of same sign, result different sign */
349 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
365 T0 = (int32_t)T0 - (int32_t)T1;
366 if (((tmp ^ T1) & (tmp ^ T0)) >> 31) {
367 /* operands of different sign, first operand and result different sign */
368 CALL_FROM_TB1(do_raise_exception_direct, EXCP_OVERFLOW);
375 T0 = (int32_t)T0 * (int32_t)T1;
382 env->LO = (int32_t)T0 / (int32_t)T1;
383 env->HI = (int32_t)T0 % (int32_t)T1;
430 T0 = (int32_t)T0 >> T1;
445 tmp = T0 << (0x20 - T1);
446 T0 = (T0 >> T1) | tmp;
454 T0 = T1 << (T0 & 0x1F);
460 T0 = (int32_t)T1 >> (T0 & 0x1F);
466 T0 = T1 >> (T0 & 0x1F);
476 tmp = T1 << (0x20 - T0);
477 T0 = (T1 >> T0) | tmp;
487 if (T0 == (target_ulong)-1) {
490 for (n = 0; n < 32; n++) {
491 if (!(T0 & (1 << 31)))
507 for (n = 0; n < 32; n++) {
517 /* 64 bits arithmetic */
518 #if (HOST_LONG_BITS == 64)
519 static inline uint64_t get_HILO (void)
521 return ((uint64_t)env->HI << 32) | (uint64_t)env->LO;
524 static inline void set_HILO (uint64_t HILO)
526 env->LO = HILO & 0xFFFFFFFF;
527 env->HI = HILO >> 32;
532 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
538 set_HILO((uint64_t)T0 * (uint64_t)T1);
546 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
547 set_HILO((int64_t)get_HILO() + tmp);
555 tmp = ((uint64_t)T0 * (uint64_t)T1);
556 set_HILO(get_HILO() + tmp);
564 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
565 set_HILO((int64_t)get_HILO() - tmp);
573 tmp = ((uint64_t)T0 * (uint64_t)T1);
574 set_HILO(get_HILO() - tmp);
580 CALL_FROM_TB0(do_mult);
586 CALL_FROM_TB0(do_multu);
592 CALL_FROM_TB0(do_madd);
598 CALL_FROM_TB0(do_maddu);
604 CALL_FROM_TB0(do_msub);
610 CALL_FROM_TB0(do_msubu);
615 /* Conditional moves */
619 env->gpr[PARAM1] = T0;
626 env->gpr[PARAM1] = T0;
632 if (!(env->fcr31 & PARAM1))
633 env->gpr[PARAM2] = env->gpr[PARAM3];
639 if (env->fcr31 & PARAM1)
640 env->gpr[PARAM2] = env->gpr[PARAM3];
645 #define OP_COND(name, cond) \
646 void glue(op_, name) (void) \
656 OP_COND(eq, T0 == T1);
657 OP_COND(ne, T0 != T1);
658 OP_COND(ge, (int32_t)T0 >= (int32_t)T1);
659 OP_COND(geu, T0 >= T1);
660 OP_COND(lt, (int32_t)T0 < (int32_t)T1);
661 OP_COND(ltu, T0 < T1);
662 OP_COND(gez, (int32_t)T0 >= 0);
663 OP_COND(gtz, (int32_t)T0 > 0);
664 OP_COND(lez, (int32_t)T0 <= 0);
665 OP_COND(ltz, (int32_t)T0 < 0);
668 //#undef USE_DIRECT_JUMP
670 void OPPROTO op_goto_tb0(void)
672 GOTO_TB(op_goto_tb0, PARAM1, 0);
676 void OPPROTO op_goto_tb1(void)
678 GOTO_TB(op_goto_tb1, PARAM1, 1);
682 /* Branch to register */
683 void op_save_breg_target (void)
689 void op_restore_breg_target (void)
701 void op_save_btarget (void)
703 env->btarget = PARAM1;
707 /* Conditional branch */
708 void op_set_bcond (void)
714 void op_save_bcond (void)
720 void op_restore_bcond (void)
726 void op_jnz_T2 (void)
734 void op_mfc0_index (void)
740 void op_mfc0_random (void)
742 CALL_FROM_TB0(do_mfc0_random);
746 void op_mfc0_entrylo0 (void)
748 T0 = env->CP0_EntryLo0;
752 void op_mfc0_entrylo1 (void)
754 T0 = env->CP0_EntryLo1;
758 void op_mfc0_context (void)
760 T0 = env->CP0_Context;
764 void op_mfc0_pagemask (void)
766 T0 = env->CP0_PageMask;
770 void op_mfc0_pagegrain (void)
772 T0 = env->CP0_PageGrain;
776 void op_mfc0_wired (void)
782 void op_mfc0_hwrena (void)
784 T0 = env->CP0_HWREna;
788 void op_mfc0_badvaddr (void)
790 T0 = env->CP0_BadVAddr;
794 void op_mfc0_count (void)
796 CALL_FROM_TB0(do_mfc0_count);
800 void op_mfc0_entryhi (void)
802 T0 = env->CP0_EntryHi;
806 void op_mfc0_compare (void)
808 T0 = env->CP0_Compare;
812 void op_mfc0_status (void)
814 T0 = env->CP0_Status;
815 if (env->hflags & MIPS_HFLAG_UM)
816 T0 |= (1 << CP0St_UM);
817 if (env->hflags & MIPS_HFLAG_ERL)
818 T0 |= (1 << CP0St_ERL);
819 if (env->hflags & MIPS_HFLAG_EXL)
820 T0 |= (1 << CP0St_EXL);
824 void op_mfc0_intctl (void)
826 T0 = env->CP0_IntCtl;
830 void op_mfc0_srsctl (void)
832 T0 = env->CP0_SRSCtl;
836 void op_mfc0_cause (void)
842 void op_mfc0_epc (void)
848 void op_mfc0_prid (void)
854 void op_mfc0_ebase (void)
860 void op_mfc0_config0 (void)
862 T0 = env->CP0_Config0;
866 void op_mfc0_config1 (void)
868 T0 = env->CP0_Config1;
872 void op_mfc0_config2 (void)
874 T0 = env->CP0_Config2;
878 void op_mfc0_config3 (void)
880 T0 = env->CP0_Config3;
884 void op_mfc0_lladdr (void)
886 T0 = env->CP0_LLAddr >> 4;
890 void op_mfc0_watchlo0 (void)
892 T0 = env->CP0_WatchLo;
896 void op_mfc0_watchhi0 (void)
898 T0 = env->CP0_WatchHi;
902 void op_mfc0_xcontext (void)
904 T0 = env->CP0_XContext;
908 void op_mfc0_framemask (void)
910 T0 = env->CP0_Framemask;
914 void op_mfc0_debug (void)
917 if (env->hflags & MIPS_HFLAG_DM)
922 void op_mfc0_depc (void)
928 void op_mfc0_performance0 (void)
930 T0 = env->CP0_Performance0;
934 void op_mfc0_taglo (void)
940 void op_mfc0_datalo (void)
942 T0 = env->CP0_DataLo;
946 void op_mfc0_taghi (void)
952 void op_mfc0_datahi (void)
954 T0 = env->CP0_DataHi;
958 void op_mfc0_errorepc (void)
960 T0 = env->CP0_ErrorEPC;
964 void op_mfc0_desave (void)
966 T0 = env->CP0_DESAVE;
970 void op_mtc0_index (void)
972 env->CP0_index = (env->CP0_index & 0x80000000) | (T0 & (MIPS_TLB_NB - 1));
976 void op_mtc0_entrylo0 (void)
978 /* Large physaddr not implemented */
979 /* 1k pages not implemented */
980 env->CP0_EntryLo0 = T0 & 0x3FFFFFFFUL;
984 void op_mtc0_entrylo1 (void)
986 /* Large physaddr not implemented */
987 /* 1k pages not implemented */
988 env->CP0_EntryLo1 = T0 & 0x3FFFFFFFUL;
992 void op_mtc0_context (void)
994 env->CP0_Context = (env->CP0_Context & ~0x007FFFFF) | (T0 & 0x007FFFF0);
998 void op_mtc0_pagemask (void)
1000 /* 1k pages not implemented */
1001 env->CP0_PageMask = T0 & 0x1FFFE000;
1005 void op_mtc0_pagegrain (void)
1007 /* SmartMIPS not implemented */
1008 /* Large physaddr not implemented */
1009 /* 1k pages not implemented */
1010 env->CP0_PageGrain = 0;
1014 void op_mtc0_wired (void)
1016 env->CP0_Wired = T0 & (MIPS_TLB_NB - 1);
1020 void op_mtc0_hwrena (void)
1022 env->CP0_HWREna = T0 & 0x0000000F;
1026 void op_mtc0_count (void)
1028 CALL_FROM_TB2(cpu_mips_store_count, env, T0);
1032 void op_mtc0_entryhi (void)
1036 /* 1k pages not implemented */
1037 /* Ignore MIPS64 TLB for now */
1038 val = T0 & 0xFFFFE0FF;
1039 old = env->CP0_EntryHi;
1040 env->CP0_EntryHi = val;
1041 /* If the ASID changes, flush qemu's TLB. */
1042 if ((old & 0xFF) != (val & 0xFF))
1043 CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
1047 void op_mtc0_compare (void)
1049 CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1053 void op_mtc0_status (void)
1055 uint32_t val, old, mask;
1057 val = T0 & 0xFA78FF01;
1058 old = env->CP0_Status;
1059 if (T0 & (1 << CP0St_UM))
1060 env->hflags |= MIPS_HFLAG_UM;
1062 env->hflags &= ~MIPS_HFLAG_UM;
1063 if (T0 & (1 << CP0St_ERL))
1064 env->hflags |= MIPS_HFLAG_ERL;
1066 env->hflags &= ~MIPS_HFLAG_ERL;
1067 if (T0 & (1 << CP0St_EXL))
1068 env->hflags |= MIPS_HFLAG_EXL;
1070 env->hflags &= ~MIPS_HFLAG_EXL;
1071 env->CP0_Status = val;
1072 /* If we unmasked an asserted IRQ, raise it */
1074 if (loglevel & CPU_LOG_TB_IN_ASM)
1075 CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1076 if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
1077 !(env->hflags & MIPS_HFLAG_EXL) &&
1078 !(env->hflags & MIPS_HFLAG_ERL) &&
1079 !(env->hflags & MIPS_HFLAG_DM) &&
1080 (env->CP0_Status & env->CP0_Cause & mask)) {
1081 env->interrupt_request |= CPU_INTERRUPT_HARD;
1083 CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
1084 } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
1085 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1090 void op_mtc0_intctl (void)
1092 /* vectored interrupts not implemented */
1093 env->CP0_IntCtl = 0;
1097 void op_mtc0_srsctl (void)
1099 /* shadow registers not implemented */
1100 env->CP0_SRSCtl = 0;
1104 void op_mtc0_cause (void)
1108 val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x000C00300);
1109 old = env->CP0_Cause;
1110 env->CP0_Cause = val;
1114 /* Check if we ever asserted a software IRQ */
1115 for (i = 0; i < 2; i++) {
1117 if ((val & mask) & !(old & mask))
1118 CALL_FROM_TB1(mips_set_irq, i);
1125 void op_mtc0_epc (void)
1131 void op_mtc0_ebase (void)
1133 /* vectored interrupts not implemented */
1134 /* Multi-CPU not implemented */
1135 env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1139 void op_mtc0_config0 (void)
1141 #if defined(MIPS_USES_R4K_TLB)
1142 /* Fixed mapping MMU not implemented */
1143 env->CP0_Config0 = (env->CP0_Config0 & 0x8017FF88) | (T0 & 0x00000001);
1145 env->CP0_Config0 = (env->CP0_Config0 & 0xFE17FF88) | (T0 & 0x00000001);
1150 void op_mtc0_config2 (void)
1152 /* tertiary/secondary caches not implemented */
1153 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1157 void op_mtc0_watchlo0 (void)
1159 env->CP0_WatchLo = T0;
1163 void op_mtc0_watchhi0 (void)
1165 env->CP0_WatchHi = T0 & 0x40FF0FF8;
1169 void op_mtc0_xcontext (void)
1171 env->CP0_XContext = T0; /* XXX */
1175 void op_mtc0_framemask (void)
1177 env->CP0_Framemask = T0; /* XXX */
1181 void op_mtc0_debug (void)
1183 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1184 if (T0 & (1 << CP0DB_DM))
1185 env->hflags |= MIPS_HFLAG_DM;
1187 env->hflags &= ~MIPS_HFLAG_DM;
1191 void op_mtc0_depc (void)
1197 void op_mtc0_performance0 (void)
1199 env->CP0_Performance0 = T0; /* XXX */
1203 void op_mtc0_taglo (void)
1205 env->CP0_TagLo = T0 & 0xFFFFFCF6;
1209 void op_mtc0_datalo (void)
1211 env->CP0_DataLo = T0; /* XXX */
1215 void op_mtc0_taghi (void)
1217 env->CP0_TagHi = T0; /* XXX */
1221 void op_mtc0_datahi (void)
1223 env->CP0_DataHi = T0; /* XXX */
1227 void op_mtc0_errorepc (void)
1229 env->CP0_ErrorEPC = T0;
1233 void op_mtc0_desave (void)
1235 env->CP0_DESAVE = T0;
1239 #ifdef MIPS_USES_FPU
1242 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1244 # define DEBUG_FPU_STATE() do { } while(0)
1247 void op_cp1_enabled(void)
1249 if (!(env->CP0_Status & (1 << CP0St_CU1))) {
1250 CALL_FROM_TB2(do_raise_exception_err, EXCP_CpU, 1);
1262 /* fetch fcr31, masking unused bits */
1263 T0 = env->fcr31 & 0x0183FFFF;
1269 /* convert MIPS rounding mode in FCR31 to IEEE library */
1270 unsigned int ieee_rm[] = {
1271 float_round_nearest_even,
1272 float_round_to_zero,
1277 #define RESTORE_ROUNDING_MODE \
1278 set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1283 /* XXX should this throw an exception?
1284 * don't write to FCR0.
1289 /* store new fcr31, masking unused bits */
1290 env->fcr31 = T0 & 0x0183FFFF;
1292 /* set rounding mode */
1293 RESTORE_ROUNDING_MODE;
1295 #ifndef CONFIG_SOFTFLOAT
1296 /* no floating point exception for native float */
1297 SET_FP_ENABLE(env->fcr31, 0);
1319 Single precition routines have a "s" suffix, double precision a
1322 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1326 FDT2 = float32_to_float64(WT0, &env->fp_status);
1332 FDT2 = int32_to_float64(WT0, &env->fp_status);
1338 FST2 = float64_to_float32(FDT0, &env->fp_status);
1344 FST2 = int32_to_float32(WT0, &env->fp_status);
1350 WT2 = float32_to_int32(FST0, &env->fp_status);
1356 WT2 = float64_to_int32(FDT0, &env->fp_status);
1363 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1364 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1365 RESTORE_ROUNDING_MODE;
1372 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1373 WT2 = float32_round_to_int(FST0, &env->fp_status);
1374 RESTORE_ROUNDING_MODE;
1381 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fp_status);
1387 WT2 = float32_to_int32_round_to_zero(FST0, &env->fp_status);
1394 set_float_rounding_mode(float_round_up, &env->fp_status);
1395 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1396 RESTORE_ROUNDING_MODE;
1403 set_float_rounding_mode(float_round_up, &env->fp_status);
1404 WT2 = float32_round_to_int(FST0, &env->fp_status);
1405 RESTORE_ROUNDING_MODE;
1412 set_float_rounding_mode(float_round_down, &env->fp_status);
1413 WT2 = float64_round_to_int(FDT0, &env->fp_status);
1414 RESTORE_ROUNDING_MODE;
1421 set_float_rounding_mode(float_round_down, &env->fp_status);
1422 WT2 = float32_round_to_int(FST0, &env->fp_status);
1423 RESTORE_ROUNDING_MODE;
1428 /* binary operations */
1429 #define FLOAT_BINOP(name) \
1432 FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \
1433 DEBUG_FPU_STATE(); \
1437 FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \
1438 DEBUG_FPU_STATE(); \
1446 /* unary operations, modifying fp status */
1447 #define FLOAT_UNOP(name) \
1450 FDT2 = float64_ ## name(FDT0, &env->fp_status); \
1451 DEBUG_FPU_STATE(); \
1455 FST2 = float32_ ## name(FST0, &env->fp_status); \
1456 DEBUG_FPU_STATE(); \
1461 /* unary operations, not modifying fp status */
1462 #define FLOAT_UNOP(name) \
1465 FDT2 = float64_ ## name(FDT0); \
1466 DEBUG_FPU_STATE(); \
1470 FST2 = float32_ ## name(FST0); \
1471 DEBUG_FPU_STATE(); \
1490 #ifdef CONFIG_SOFTFLOAT
1491 #define clear_invalid() do { \
1492 int flags = get_float_exception_flags(&env->fp_status); \
1493 flags &= ~float_flag_invalid; \
1494 set_float_exception_flags(flags, &env->fp_status); \
1497 #define clear_invalid() do { } while(0)
1500 extern void dump_fpu_s(CPUState *env);
1502 #define FOP_COND(fmt, op, sig, cond) \
1503 void op_cmp_ ## fmt ## _ ## op (void) \
1506 SET_FP_COND(env->fcr31); \
1508 CLEAR_FP_COND(env->fcr31); \
1511 /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1512 DEBUG_FPU_STATE(); \
1516 int float64_is_unordered(float64 a, float64 b STATUS_PARAM)
1518 if (float64_is_nan(a) || float64_is_nan(b)) {
1519 float_raise(float_flag_invalid, status);
1527 FOP_COND(d, f, 0, 0)
1528 FOP_COND(d, un, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1529 FOP_COND(d, eq, 0, float64_eq(FDT0, FDT1, &env->fp_status))
1530 FOP_COND(d, ueq, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1531 FOP_COND(d, olt, 0, float64_lt(FDT0, FDT1, &env->fp_status))
1532 FOP_COND(d, ult, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1533 FOP_COND(d, ole, 0, float64_le(FDT0, FDT1, &env->fp_status))
1534 FOP_COND(d, ule, 0, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1535 /* NOTE: the comma operator will make "cond" to eval to false,
1536 * but float*_is_unordered() is still called
1538 FOP_COND(d, sf, 1, (float64_is_unordered(FDT0, FDT1, &env->fp_status), 0))
1539 FOP_COND(d, ngle,1, float64_is_unordered(FDT1, FDT0, &env->fp_status))
1540 FOP_COND(d, seq, 1, float64_eq(FDT0, FDT1, &env->fp_status))
1541 FOP_COND(d, ngl, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_eq(FDT0, FDT1, &env->fp_status))
1542 FOP_COND(d, lt, 1, float64_lt(FDT0, FDT1, &env->fp_status))
1543 FOP_COND(d, nge, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_lt(FDT0, FDT1, &env->fp_status))
1544 FOP_COND(d, le, 1, float64_le(FDT0, FDT1, &env->fp_status))
1545 FOP_COND(d, ngt, 1, float64_is_unordered(FDT1, FDT0, &env->fp_status) || float64_le(FDT0, FDT1, &env->fp_status))
1547 flag float32_is_unordered(float32 a, float32 b STATUS_PARAM)
1549 extern flag float32_is_nan( float32 a );
1550 if (float32_is_nan(a) || float32_is_nan(b)) {
1551 float_raise(float_flag_invalid, status);
1559 /* NOTE: the comma operator will make "cond" to eval to false,
1560 * but float*_is_unordered() is still called
1562 FOP_COND(s, f, 0, 0)
1563 FOP_COND(s, un, 0, float32_is_unordered(FST1, FST0, &env->fp_status))
1564 FOP_COND(s, eq, 0, float32_eq(FST0, FST1, &env->fp_status))
1565 FOP_COND(s, ueq, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1566 FOP_COND(s, olt, 0, float32_lt(FST0, FST1, &env->fp_status))
1567 FOP_COND(s, ult, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1568 FOP_COND(s, ole, 0, float32_le(FST0, FST1, &env->fp_status))
1569 FOP_COND(s, ule, 0, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1570 /* NOTE: the comma operator will make "cond" to eval to false,
1571 * but float*_is_unordered() is still called
1573 FOP_COND(s, sf, 1, (float32_is_unordered(FST0, FST1, &env->fp_status), 0))
1574 FOP_COND(s, ngle,1, float32_is_unordered(FST1, FST0, &env->fp_status))
1575 FOP_COND(s, seq, 1, float32_eq(FST0, FST1, &env->fp_status))
1576 FOP_COND(s, ngl, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_eq(FST0, FST1, &env->fp_status))
1577 FOP_COND(s, lt, 1, float32_lt(FST0, FST1, &env->fp_status))
1578 FOP_COND(s, nge, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_lt(FST0, FST1, &env->fp_status))
1579 FOP_COND(s, le, 1, float32_le(FST0, FST1, &env->fp_status))
1580 FOP_COND(s, ngt, 1, float32_is_unordered(FST1, FST0, &env->fp_status) || float32_le(FST0, FST1, &env->fp_status))
1584 T0 = ! IS_FP_COND_SET(env->fcr31);
1591 T0 = IS_FP_COND_SET(env->fcr31);
1595 #endif /* MIPS_USES_FPU */
1597 #if defined(MIPS_USES_R4K_TLB)
1598 void op_tlbwi (void)
1600 CALL_FROM_TB0(do_tlbwi);
1604 void op_tlbwr (void)
1606 CALL_FROM_TB0(do_tlbwr);
1612 CALL_FROM_TB0(do_tlbp);
1618 CALL_FROM_TB0(do_tlbr);
1626 CALL_FROM_TB1(do_pmon, PARAM1);
1634 T0 = env->CP0_Status;
1635 val = T0 & ~(1 << CP0St_IE);
1637 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1638 env->CP0_Status = val;
1647 T0 = env->CP0_Status;
1648 val = T0 | (1 << CP0St_IE);
1650 const uint32_t mask = 0x0000FF00;
1652 env->CP0_Status = val;
1653 if (!(env->hflags & MIPS_HFLAG_EXL) &&
1654 !(env->hflags & MIPS_HFLAG_ERL) &&
1655 !(env->hflags & MIPS_HFLAG_DM) &&
1656 (env->CP0_Status & env->CP0_Cause & mask)) {
1657 env->interrupt_request |= CPU_INTERRUPT_HARD;
1659 CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
1668 CALL_FROM_TB1(do_raise_exception_direct, EXCP_TRAP);
1673 void op_debug (void)
1675 CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG);
1679 void op_set_lladdr (void)
1681 env->CP0_LLAddr = T2;
1685 void debug_eret (void);
1688 CALL_FROM_TB0(debug_eret);
1689 if (env->hflags & MIPS_HFLAG_ERL) {
1690 env->PC = env->CP0_ErrorEPC;
1691 env->hflags &= ~MIPS_HFLAG_ERL;
1692 env->CP0_Status &= ~(1 << CP0St_ERL);
1694 env->PC = env->CP0_EPC;
1695 env->hflags &= ~MIPS_HFLAG_EXL;
1696 env->CP0_Status &= ~(1 << CP0St_EXL);
1698 env->CP0_LLAddr = 1;
1702 void op_deret (void)
1704 CALL_FROM_TB0(debug_eret);
1705 env->PC = env->CP0_DEPC;
1709 void op_rdhwr_cpunum(void)
1711 if (env->CP0_HWREna & (1 << 0))
1712 T0 = env->CP0_EBase & 0x2ff;
1714 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1718 void op_rdhwr_synci_step(void)
1720 if (env->CP0_HWREna & (1 << 1))
1721 T0 = env->SYNCI_Step;
1723 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1727 void op_rdhwr_cc(void)
1729 if (env->CP0_HWREna & (1 << 2))
1730 T0 = env->CP0_Count;
1732 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1736 void op_rdhwr_ccres(void)
1738 if (env->CP0_HWREna & (1 << 3))
1741 CALL_FROM_TB1(do_raise_exception_direct, EXCP_RI);
1745 void op_save_state (void)
1747 env->hflags = PARAM1;
1751 void op_save_pc (void)
1757 void op_raise_exception (void)
1759 CALL_FROM_TB1(do_raise_exception, PARAM1);
1763 void op_raise_exception_err (void)
1765 CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2);
1769 void op_exit_tb (void)
1778 CALL_FROM_TB1(do_raise_exception, EXCP_HLT);
1782 /* Bitfield operations. */
1785 unsigned int pos = PARAM1;
1786 unsigned int size = PARAM2;
1788 T0 = (T1 >> pos) & ((1 << size) - 1);
1794 unsigned int pos = PARAM1;
1795 unsigned int size = PARAM2;
1796 target_ulong mask = ((1 << size) - 1) << pos;
1798 T0 = (T2 & ~mask) | ((T1 << pos) & mask);
1804 T0 = ((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF);
1810 T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
1816 T0 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
1822 T0 = ((T1 & 0xFF) ^ 0x80) - 0x80;
1828 T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000;