2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 /* no MMU emulation */
40 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
41 target_ulong address, int rw, int access_type)
44 *prot = PAGE_READ | PAGE_WRITE;
48 /* fixed mapping MMU emulation */
49 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
50 target_ulong address, int rw, int access_type)
52 if (address <= (int32_t)0x7FFFFFFFUL) {
53 if (!(env->CP0_Status & (1 << CP0St_ERL)))
54 *physical = address + 0x40000000UL;
57 } else if (address <= (int32_t)0xBFFFFFFFUL)
58 *physical = address & 0x1FFFFFFF;
62 *prot = PAGE_READ | PAGE_WRITE;
66 /* MIPS32/MIPS64 R4000-style MMU emulation */
67 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
68 target_ulong address, int rw, int access_type)
70 uint8_t ASID = env->CP0_EntryHi & 0xFF;
73 for (i = 0; i < env->tlb->tlb_in_use; i++) {
74 r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
75 /* 1k pages are not supported. */
76 target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
77 target_ulong tag = address & ~mask;
78 target_ulong VPN = tlb->VPN & ~mask;
79 #if defined(TARGET_MIPS64)
83 /* Check ASID, virtual page number & size */
84 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
86 int n = !!(address & mask & ~(mask >> 1));
87 /* Check access rights */
88 if (!(n ? tlb->V1 : tlb->V0))
89 return TLBRET_INVALID;
90 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91 *physical = tlb->PFN[n] | (address & (mask >> 1));
93 if (n ? tlb->D1 : tlb->D0)
100 return TLBRET_NOMATCH;
103 static int get_physical_address (CPUState *env, target_ulong *physical,
104 int *prot, target_ulong address,
105 int rw, int access_type)
107 /* User mode can only access useg/xuseg */
108 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
109 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
110 int kernel_mode = !user_mode && !supervisor_mode;
111 #if defined(TARGET_MIPS64)
112 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
113 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
114 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
116 int ret = TLBRET_MATCH;
120 fprintf(logfile, "user mode %d h %08x\n",
121 user_mode, env->hflags);
125 if (address <= (int32_t)0x7FFFFFFFUL) {
127 if (env->CP0_Status & (1 << CP0St_ERL)) {
128 *physical = address & 0xFFFFFFFF;
129 *prot = PAGE_READ | PAGE_WRITE;
131 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
133 #if defined(TARGET_MIPS64)
134 } else if (address < 0x4000000000000000ULL) {
136 if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
137 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
139 ret = TLBRET_BADADDR;
141 } else if (address < 0x8000000000000000ULL) {
143 if ((supervisor_mode || kernel_mode) &&
144 SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
145 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
147 ret = TLBRET_BADADDR;
149 } else if (address < 0xC000000000000000ULL) {
151 /* XXX: Assumes PABITS = 36 (correct for MIPS64R1) */
152 if (kernel_mode && KX &&
153 (address & 0x07FFFFFFFFFFFFFFULL) <= 0x0000000FFFFFFFFFULL) {
154 *physical = address & 0x0000000FFFFFFFFFULL;
155 *prot = PAGE_READ | PAGE_WRITE;
157 ret = TLBRET_BADADDR;
159 } else if (address < 0xFFFFFFFF80000000ULL) {
161 if (kernel_mode && KX &&
162 address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
163 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
165 ret = TLBRET_BADADDR;
168 } else if (address < (int32_t)0xA0000000UL) {
171 *physical = address - (int32_t)0x80000000UL;
172 *prot = PAGE_READ | PAGE_WRITE;
174 ret = TLBRET_BADADDR;
176 } else if (address < (int32_t)0xC0000000UL) {
179 *physical = address - (int32_t)0xA0000000UL;
180 *prot = PAGE_READ | PAGE_WRITE;
182 ret = TLBRET_BADADDR;
184 } else if (address < (int32_t)0xE0000000UL) {
186 if (supervisor_mode || kernel_mode) {
187 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
189 ret = TLBRET_BADADDR;
193 /* XXX: debug segment is not emulated */
195 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
197 ret = TLBRET_BADADDR;
202 fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
203 address, rw, access_type, *physical, *prot, ret);
210 #if defined(CONFIG_USER_ONLY)
211 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
216 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
218 target_ulong phys_addr;
221 if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
226 void cpu_mips_init_mmu (CPUState *env)
229 #endif /* !defined(CONFIG_USER_ONLY) */
231 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
232 int mmu_idx, int is_softmmu)
234 target_ulong physical;
236 int exception = 0, error_code = 0;
242 cpu_dump_state(env, logfile, fprintf, 0);
244 fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
245 __func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu);
251 /* XXX: put correct access by using cpu_restore_state()
253 access_type = ACCESS_INT;
254 if (env->user_mode_only) {
255 /* user mode only emulation */
256 ret = TLBRET_NOMATCH;
259 ret = get_physical_address(env, &physical, &prot,
260 address, rw, access_type);
262 fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
263 __func__, address, ret, physical, prot);
265 if (ret == TLBRET_MATCH) {
266 ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
267 physical & TARGET_PAGE_MASK, prot,
268 mmu_idx, is_softmmu);
269 } else if (ret < 0) {
274 /* Reference to kernel address from user mode or supervisor mode */
275 /* Reference to supervisor address from user mode */
277 exception = EXCP_AdES;
279 exception = EXCP_AdEL;
282 /* No TLB match for a mapped address */
284 exception = EXCP_TLBS;
286 exception = EXCP_TLBL;
290 /* TLB match with no valid bit */
292 exception = EXCP_TLBS;
294 exception = EXCP_TLBL;
297 /* TLB match but 'D' bit is cleared */
298 exception = EXCP_LTLBL;
302 /* Raise exception */
303 env->CP0_BadVAddr = address;
304 env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
305 ((address >> 9) & 0x007ffff0);
307 (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
308 #if defined(TARGET_MIPS64)
309 env->CP0_EntryHi &= env->SEGMask;
310 env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
311 ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
312 ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
314 env->exception_index = exception;
315 env->error_code = error_code;
322 #if defined(CONFIG_USER_ONLY)
323 void do_interrupt (CPUState *env)
325 env->exception_index = EXCP_NONE;
328 void do_interrupt (CPUState *env)
333 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
334 fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
335 __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
337 if (env->exception_index == EXCP_EXT_INTERRUPT &&
338 (env->hflags & MIPS_HFLAG_DM))
339 env->exception_index = EXCP_DINT;
341 switch (env->exception_index) {
343 env->CP0_Debug |= 1 << CP0DB_DSS;
344 /* Debug single step cannot be raised inside a delay slot and
345 * resume will always occur on the next instruction
346 * (but we assume the pc has always been updated during
349 env->CP0_DEPC = env->PC[env->current_tc];
350 goto enter_debug_mode;
352 env->CP0_Debug |= 1 << CP0DB_DINT;
355 env->CP0_Debug |= 1 << CP0DB_DIB;
358 env->CP0_Debug |= 1 << CP0DB_DBp;
361 env->CP0_Debug |= 1 << CP0DB_DDBS;
364 env->CP0_Debug |= 1 << CP0DB_DDBL;
366 if (env->hflags & MIPS_HFLAG_BMASK) {
367 /* If the exception was raised from a delay slot,
368 come back to the jump. */
369 env->CP0_DEPC = env->PC[env->current_tc] - 4;
370 env->hflags &= ~MIPS_HFLAG_BMASK;
372 env->CP0_DEPC = env->PC[env->current_tc];
375 env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
376 env->hflags &= ~(MIPS_HFLAG_KSU);
377 /* EJTAG probe trap enable is not implemented... */
378 if (!(env->CP0_Status & (1 << CP0St_EXL)))
379 env->CP0_Cause &= ~(1 << CP0Ca_BD);
380 env->PC[env->current_tc] = (int32_t)0xBFC00480;
386 env->CP0_Status |= (1 << CP0St_SR);
387 memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
390 env->CP0_Status |= (1 << CP0St_NMI);
392 if (env->hflags & MIPS_HFLAG_BMASK) {
393 /* If the exception was raised from a delay slot,
394 come back to the jump. */
395 env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
396 env->hflags &= ~MIPS_HFLAG_BMASK;
398 env->CP0_ErrorEPC = env->PC[env->current_tc];
400 env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
401 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
402 env->hflags &= ~(MIPS_HFLAG_KSU);
403 if (!(env->CP0_Status & (1 << CP0St_EXL)))
404 env->CP0_Cause &= ~(1 << CP0Ca_BD);
405 env->PC[env->current_tc] = (int32_t)0xBFC00000;
410 case EXCP_EXT_INTERRUPT:
412 if (env->CP0_Cause & (1 << CP0Ca_IV))
417 /* XXX: TODO: manage defered watch exceptions */
427 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
428 #if defined(TARGET_MIPS64)
429 int R = env->CP0_BadVAddr >> 62;
430 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
431 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
432 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
434 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
458 env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
459 (env->error_code << CP0Ca_CE);
475 if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
476 #if defined(TARGET_MIPS64)
477 int R = env->CP0_BadVAddr >> 62;
478 int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
479 int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
480 int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
482 if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
492 if (!(env->CP0_Status & (1 << CP0St_EXL))) {
493 if (env->hflags & MIPS_HFLAG_BMASK) {
494 /* If the exception was raised from a delay slot,
495 come back to the jump. */
496 env->CP0_EPC = env->PC[env->current_tc] - 4;
497 env->CP0_Cause |= (1 << CP0Ca_BD);
499 env->CP0_EPC = env->PC[env->current_tc];
500 env->CP0_Cause &= ~(1 << CP0Ca_BD);
502 env->CP0_Status |= (1 << CP0St_EXL);
503 env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
504 env->hflags &= ~(MIPS_HFLAG_KSU);
506 env->hflags &= ~MIPS_HFLAG_BMASK;
507 if (env->CP0_Status & (1 << CP0St_BEV)) {
508 env->PC[env->current_tc] = (int32_t)0xBFC00200;
510 env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
512 env->PC[env->current_tc] += offset;
513 env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
517 fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
518 env->exception_index);
520 printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
523 if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
524 fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
525 " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
526 __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
527 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
530 env->exception_index = EXCP_NONE;
532 #endif /* !defined(CONFIG_USER_ONLY) */
534 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
539 uint8_t ASID = env->CP0_EntryHi & 0xFF;
542 tlb = &env->tlb->mmu.r4k.tlb[idx];
543 /* The qemu TLB is flushed when the ASID changes, so no need to
544 flush these entries again. */
545 if (tlb->G == 0 && tlb->ASID != ASID) {
549 if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
550 /* For tlbwr, we can shadow the discarded entry into
551 a new (fake) TLB entry, as long as the guest can not
552 tell that it's there. */
553 env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
554 env->tlb->tlb_in_use++;
558 /* 1k pages are not supported. */
559 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
561 addr = tlb->VPN & ~mask;
562 #if defined(TARGET_MIPS64)
563 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
564 addr |= 0x3FFFFF0000000000ULL;
567 end = addr | (mask >> 1);
569 tlb_flush_page (env, addr);
570 addr += TARGET_PAGE_SIZE;
574 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
575 #if defined(TARGET_MIPS64)
576 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
577 addr |= 0x3FFFFF0000000000ULL;
582 tlb_flush_page (env, addr);
583 addr += TARGET_PAGE_SIZE;