1 #if !defined (__MIPS_CPU_H__)
9 typedef union fpr_t fpr_t;
16 #if defined(MIPS_USES_R4K_TLB)
17 typedef struct tlb_t tlb_t;
30 typedef struct CPUMIPSState CPUMIPSState;
32 /* General integer registers */
34 /* Special registers */
38 #if defined(MIPS_USES_FPU)
39 /* Floating point registers */
41 /* Floating point special purpose registers */
48 #if defined(MIPS_USES_R4K_TLB)
53 uint32_t CP0_EntryLo0;
54 uint32_t CP0_EntryLo1;
56 uint32_t CP0_PageMask;
58 uint32_t CP0_BadVAddr;
108 uint32_t CP0_WatchLo;
109 uint32_t CP0_WatchHi;
113 #define CP0DB_LSNM 28
114 #define CP0DB_Doze 27
115 #define CP0DB_Halt 26
117 #define CP0DB_IBEP 24
118 #define CP0DB_DBEP 21
119 #define CP0DB_IEXI 20
132 uint32_t CP0_ErrorEPC;
135 #if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
136 double ft0, ft1, ft2;
138 struct QEMUTimer *timer; /* Internal timer */
139 int interrupt_request;
143 int user_mode_only; /* user mode only simulation */
144 uint32_t hflags; /* CPU State */
145 /* TMASK defines different execution modes */
146 #define MIPS_HFLAGS_TMASK 0x00FF
147 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
148 #define MIPS_HFLAG_UM 0x0001 /* user mode */
149 #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
150 #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
151 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
152 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
153 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
154 #define MIPS_HFLAG_DS 0x0080 /* In / out of delay slot */
155 /* Those flags keep the branch state if the translation is interrupted
156 * between the branch instruction and the delay slot
158 #define MIPS_HFLAG_BMASK 0x0F00
159 #define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
160 #define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
161 #define MIPS_HFLAG_BL 0x0400 /* Likely branch */
162 #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
163 target_ulong btarget; /* Jump / branch target */
164 int bcond; /* Branch condition (if needed) */
165 struct TranslationBlock *current_tb; /* currently executing TB */
166 /* soft mmu support */
167 /* in order to avoid passing too many arguments to the memory
168 write helpers, we store some rarely used information in the CPU
170 target_ulong mem_write_pc; /* host pc at which the memory was
172 unsigned long mem_write_vaddr; /* target virtual addr at which the
173 memory was written */
174 /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
175 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
176 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
177 /* ice debug support */
178 target_ulong breakpoints[MAX_BREAKPOINTS];
180 int singlestep_enabled; /* XXX: should use CPU single step mode instead */
187 /* Memory access type :
188 * may be needed for precise access rights control and precise exceptions.
191 /* 1 bit to define user level / supervisor access */
194 /* 1 bit to indicate direction */
196 /* Type of instruction that generated the access */
197 ACCESS_CODE = 0x10, /* Code fetch access */
198 ACCESS_INT = 0x20, /* Integer load/store access */
199 ACCESS_FLOAT = 0x30, /* floating point load/store access */
235 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
236 /* may change privilege level */
237 EXCP_BRANCH = 0x108, /* branch instruction */
238 EXCP_ERET = 0x10C, /* return from interrupt */
239 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
244 #define EXT_SPECIAL 0x100
245 #define EXT_SPECIAL2 0x200
246 #define EXT_REGIMM 0x300
247 #define EXT_CP0 0x400
248 #define EXT_CP1 0x500
249 #define EXT_CP2 0x600
250 #define EXT_CP3 0x700
253 /* indirect opcode tables */
261 /* arithmetic with immediate */
270 /* Jump and branches */
273 OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
281 OPC_JALX = 0x1D, /* MIPS 16 only */
282 /* Load and stores */
297 /* Floating point load/store */
306 /* Cache and prefetch */
311 /* MIPS special opcodes */
314 OPC_SLL = 0x00 | EXT_SPECIAL,
315 /* NOP is SLL r0, r0, 0 */
316 /* SSNOP is SLL r0, r0, 1 */
317 OPC_SRL = 0x02 | EXT_SPECIAL,
318 OPC_SRA = 0x03 | EXT_SPECIAL,
319 OPC_SLLV = 0x04 | EXT_SPECIAL,
320 OPC_SRLV = 0x06 | EXT_SPECIAL,
321 OPC_SRAV = 0x07 | EXT_SPECIAL,
322 /* Multiplication / division */
323 OPC_MULT = 0x18 | EXT_SPECIAL,
324 OPC_MULTU = 0x19 | EXT_SPECIAL,
325 OPC_DIV = 0x1A | EXT_SPECIAL,
326 OPC_DIVU = 0x1B | EXT_SPECIAL,
327 /* 2 registers arithmetic / logic */
328 OPC_ADD = 0x20 | EXT_SPECIAL,
329 OPC_ADDU = 0x21 | EXT_SPECIAL,
330 OPC_SUB = 0x22 | EXT_SPECIAL,
331 OPC_SUBU = 0x23 | EXT_SPECIAL,
332 OPC_AND = 0x24 | EXT_SPECIAL,
333 OPC_OR = 0x25 | EXT_SPECIAL,
334 OPC_XOR = 0x26 | EXT_SPECIAL,
335 OPC_NOR = 0x27 | EXT_SPECIAL,
336 OPC_SLT = 0x2A | EXT_SPECIAL,
337 OPC_SLTU = 0x2B | EXT_SPECIAL,
339 OPC_JR = 0x08 | EXT_SPECIAL,
340 OPC_JALR = 0x09 | EXT_SPECIAL,
342 OPC_TGE = 0x30 | EXT_SPECIAL,
343 OPC_TGEU = 0x31 | EXT_SPECIAL,
344 OPC_TLT = 0x32 | EXT_SPECIAL,
345 OPC_TLTU = 0x33 | EXT_SPECIAL,
346 OPC_TEQ = 0x34 | EXT_SPECIAL,
347 OPC_TNE = 0x36 | EXT_SPECIAL,
348 /* HI / LO registers load & stores */
349 OPC_MFHI = 0x10 | EXT_SPECIAL,
350 OPC_MTHI = 0x11 | EXT_SPECIAL,
351 OPC_MFLO = 0x12 | EXT_SPECIAL,
352 OPC_MTLO = 0x13 | EXT_SPECIAL,
353 /* Conditional moves */
354 OPC_MOVZ = 0x0A | EXT_SPECIAL,
355 OPC_MOVN = 0x0B | EXT_SPECIAL,
357 OPC_MOVCI = 0x01 | EXT_SPECIAL,
360 OPC_PMON = 0x05 | EXT_SPECIAL,
361 OPC_SYSCALL = 0x0C | EXT_SPECIAL,
362 OPC_BREAK = 0x0D | EXT_SPECIAL,
363 OPC_SYNC = 0x0F | EXT_SPECIAL,
367 /* Mutiply & xxx operations */
368 OPC_MADD = 0x00 | EXT_SPECIAL2,
369 OPC_MADDU = 0x01 | EXT_SPECIAL2,
370 OPC_MUL = 0x02 | EXT_SPECIAL2,
371 OPC_MSUB = 0x04 | EXT_SPECIAL2,
372 OPC_MSUBU = 0x05 | EXT_SPECIAL2,
374 OPC_CLZ = 0x20 | EXT_SPECIAL2,
375 OPC_CLO = 0x21 | EXT_SPECIAL2,
377 OPC_SDBBP = 0x3F | EXT_SPECIAL2,
382 OPC_BLTZ = 0x00 | EXT_REGIMM,
383 OPC_BLTZL = 0x02 | EXT_REGIMM,
384 OPC_BGEZ = 0x01 | EXT_REGIMM,
385 OPC_BGEZL = 0x03 | EXT_REGIMM,
386 OPC_BLTZAL = 0x10 | EXT_REGIMM,
387 OPC_BLTZALL = 0x12 | EXT_REGIMM,
388 OPC_BGEZAL = 0x11 | EXT_REGIMM,
389 OPC_BGEZALL = 0x13 | EXT_REGIMM,
390 OPC_TGEI = 0x08 | EXT_REGIMM,
391 OPC_TGEIU = 0x09 | EXT_REGIMM,
392 OPC_TLTI = 0x0A | EXT_REGIMM,
393 OPC_TLTIU = 0x0B | EXT_REGIMM,
394 OPC_TEQI = 0x0C | EXT_REGIMM,
395 OPC_TNEI = 0x0E | EXT_REGIMM,
399 /* Coprocessor 0 (MMU) */
400 OPC_MFC0 = 0x00 | EXT_CP0,
401 OPC_MTC0 = 0x04 | EXT_CP0,
402 OPC_TLBR = 0x01 | EXT_CP0,
403 OPC_TLBWI = 0x02 | EXT_CP0,
404 OPC_TLBWR = 0x06 | EXT_CP0,
405 OPC_TLBP = 0x08 | EXT_CP0,
406 OPC_ERET = 0x18 | EXT_CP0,
407 OPC_DERET = 0x1F | EXT_CP0,
408 OPC_WAIT = 0x20 | EXT_CP0,
411 int cpu_mips_exec(CPUMIPSState *s);
412 CPUMIPSState *cpu_mips_init(void);
413 uint32_t cpu_mips_get_clock (void);
415 #endif /* !defined (__MIPS_CPU_H__) */