4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(x...) x
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48 #define BUGGY_64(x) NULL
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(x...)
58 //#define MACRO_TEST 1
60 /* global register indexes */
61 static TCGv cpu_env, cpu_T[2], cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst;
63 /* local register indexes (only used inside old micro ops) */
64 static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
65 static TCGv cpu_tmp5, cpu_tmp6;
68 static int x86_64_hregs;
71 typedef struct DisasContext {
72 /* current insn context */
73 int override; /* -1 if no override */
76 target_ulong pc; /* pc = eip + cs_base */
77 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
78 static state change (stop translation) */
79 /* current block context */
80 target_ulong cs_base; /* base of CS segment */
81 int pe; /* protected mode */
82 int code32; /* 32 bit code segment */
84 int lma; /* long mode active */
85 int code64; /* 64 bit code segment */
88 int ss32; /* 32 bit stack segment */
89 int cc_op; /* current CC operation */
90 int addseg; /* non zero if either DS/ES/SS have a non zero base */
91 int f_st; /* currently unused */
92 int vm86; /* vm86 mode */
95 int tf; /* TF cpu flag */
96 int singlestep_enabled; /* "hardware" single step enabled */
97 int jmp_opt; /* use direct block chaining for direct jumps */
98 int mem_index; /* select memory access functions */
99 uint64_t flags; /* all execution flags */
100 struct TranslationBlock *tb;
101 int popl_esp_hack; /* for correct popl with esp base handling */
102 int rip_offset; /* only used in x86_64, but left for simplicity */
104 int cpuid_ext_features;
105 int cpuid_ext2_features;
106 int cpuid_ext3_features;
109 static void gen_eob(DisasContext *s);
110 static void gen_jmp(DisasContext *s, target_ulong eip);
111 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
113 /* i386 arith/logic operations */
133 OP_SHL1, /* undocumented */
157 /* I386 int registers */
158 OR_EAX, /* MUST be even numbered */
167 OR_TMP0 = 16, /* temporary operand register */
169 OR_A0, /* temporary register used when doing address evaluation */
172 static inline void gen_op_movl_T0_0(void)
174 tcg_gen_movi_tl(cpu_T[0], 0);
177 static inline void gen_op_movl_T0_im(int32_t val)
179 tcg_gen_movi_tl(cpu_T[0], val);
182 static inline void gen_op_movl_T0_imu(uint32_t val)
184 tcg_gen_movi_tl(cpu_T[0], val);
187 static inline void gen_op_movl_T1_im(int32_t val)
189 tcg_gen_movi_tl(cpu_T[1], val);
192 static inline void gen_op_movl_T1_imu(uint32_t val)
194 tcg_gen_movi_tl(cpu_T[1], val);
197 static inline void gen_op_movl_A0_im(uint32_t val)
199 tcg_gen_movi_tl(cpu_A0, val);
203 static inline void gen_op_movq_A0_im(int64_t val)
205 tcg_gen_movi_tl(cpu_A0, val);
209 static inline void gen_movtl_T0_im(target_ulong val)
211 tcg_gen_movi_tl(cpu_T[0], val);
214 static inline void gen_movtl_T1_im(target_ulong val)
216 tcg_gen_movi_tl(cpu_T[1], val);
219 static inline void gen_op_andl_T0_ffff(void)
221 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
224 static inline void gen_op_andl_T0_im(uint32_t val)
226 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
229 static inline void gen_op_movl_T0_T1(void)
231 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
234 static inline void gen_op_andl_A0_ffff(void)
236 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
241 #define NB_OP_SIZES 4
243 #else /* !TARGET_X86_64 */
245 #define NB_OP_SIZES 3
247 #endif /* !TARGET_X86_64 */
249 #if defined(WORDS_BIGENDIAN)
250 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
251 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
252 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
253 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
254 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
256 #define REG_B_OFFSET 0
257 #define REG_H_OFFSET 1
258 #define REG_W_OFFSET 0
259 #define REG_L_OFFSET 0
260 #define REG_LH_OFFSET 4
263 static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg)
267 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
268 tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
270 tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
274 tcg_gen_st16_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
278 tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
279 /* high part of register set to zero */
280 tcg_gen_movi_tl(cpu_tmp0, 0);
281 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
285 tcg_gen_st_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));
290 tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
296 static inline void gen_op_mov_reg_T0(int ot, int reg)
298 gen_op_mov_reg_TN(ot, 0, reg);
301 static inline void gen_op_mov_reg_T1(int ot, int reg)
303 gen_op_mov_reg_TN(ot, 1, reg);
306 static inline void gen_op_mov_reg_A0(int size, int reg)
310 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
314 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
315 /* high part of register set to zero */
316 tcg_gen_movi_tl(cpu_tmp0, 0);
317 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
321 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
326 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
332 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
336 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
339 tcg_gen_ld8u_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
344 tcg_gen_ld_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));
349 static inline void gen_op_movl_A0_reg(int reg)
351 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
354 static inline void gen_op_addl_A0_im(int32_t val)
356 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
358 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
363 static inline void gen_op_addq_A0_im(int64_t val)
365 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
369 static void gen_add_A0_im(DisasContext *s, int val)
373 gen_op_addq_A0_im(val);
376 gen_op_addl_A0_im(val);
379 static inline void gen_op_addl_T0_T1(void)
381 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
384 static inline void gen_op_jmp_T0(void)
386 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
389 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
393 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
394 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
395 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
398 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
399 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
401 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
403 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
407 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
408 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
409 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
415 static inline void gen_op_add_reg_T0(int size, int reg)
419 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
420 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
421 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
424 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
425 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
427 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
429 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
433 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
434 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
435 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
441 static inline void gen_op_set_cc_op(int32_t val)
443 tcg_gen_movi_i32(cpu_cc_op, val);
446 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
448 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
450 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
451 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
453 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
457 static inline void gen_op_movl_A0_seg(int reg)
459 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
462 static inline void gen_op_addl_A0_seg(int reg)
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
465 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
467 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
472 static inline void gen_op_movq_A0_seg(int reg)
474 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
477 static inline void gen_op_addq_A0_seg(int reg)
479 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
480 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
483 static inline void gen_op_movq_A0_reg(int reg)
485 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
488 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
490 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
492 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
493 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
497 static inline void gen_op_lds_T0_A0(int idx)
499 int mem_index = (idx >> 2) - 1;
502 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
505 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
509 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
514 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
515 static inline void gen_op_ld_T0_A0(int idx)
517 int mem_index = (idx >> 2) - 1;
520 tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, mem_index);
523 tcg_gen_qemu_ld16u(cpu_T[0], cpu_A0, mem_index);
526 tcg_gen_qemu_ld32u(cpu_T[0], cpu_A0, mem_index);
530 tcg_gen_qemu_ld64(cpu_T[0], cpu_A0, mem_index);
535 static inline void gen_op_ldu_T0_A0(int idx)
537 gen_op_ld_T0_A0(idx);
540 static inline void gen_op_ld_T1_A0(int idx)
542 int mem_index = (idx >> 2) - 1;
545 tcg_gen_qemu_ld8u(cpu_T[1], cpu_A0, mem_index);
548 tcg_gen_qemu_ld16u(cpu_T[1], cpu_A0, mem_index);
551 tcg_gen_qemu_ld32u(cpu_T[1], cpu_A0, mem_index);
555 tcg_gen_qemu_ld64(cpu_T[1], cpu_A0, mem_index);
560 static inline void gen_op_st_T0_A0(int idx)
562 int mem_index = (idx >> 2) - 1;
565 tcg_gen_qemu_st8(cpu_T[0], cpu_A0, mem_index);
568 tcg_gen_qemu_st16(cpu_T[0], cpu_A0, mem_index);
571 tcg_gen_qemu_st32(cpu_T[0], cpu_A0, mem_index);
575 tcg_gen_qemu_st64(cpu_T[0], cpu_A0, mem_index);
580 static inline void gen_op_st_T1_A0(int idx)
582 int mem_index = (idx >> 2) - 1;
585 tcg_gen_qemu_st8(cpu_T[1], cpu_A0, mem_index);
588 tcg_gen_qemu_st16(cpu_T[1], cpu_A0, mem_index);
591 tcg_gen_qemu_st32(cpu_T[1], cpu_A0, mem_index);
595 tcg_gen_qemu_st64(cpu_T[1], cpu_A0, mem_index);
600 static inline void gen_jmp_im(target_ulong pc)
602 tcg_gen_movi_tl(cpu_tmp0, pc);
603 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
606 static inline void gen_string_movl_A0_ESI(DisasContext *s)
610 override = s->override;
614 gen_op_movq_A0_seg(override);
615 gen_op_addq_A0_reg_sN(0, R_ESI);
617 gen_op_movq_A0_reg(R_ESI);
623 if (s->addseg && override < 0)
626 gen_op_movl_A0_seg(override);
627 gen_op_addl_A0_reg_sN(0, R_ESI);
629 gen_op_movl_A0_reg(R_ESI);
632 /* 16 address, always override */
635 gen_op_movl_A0_reg(R_ESI);
636 gen_op_andl_A0_ffff();
637 gen_op_addl_A0_seg(override);
641 static inline void gen_string_movl_A0_EDI(DisasContext *s)
645 gen_op_movq_A0_reg(R_EDI);
650 gen_op_movl_A0_seg(R_ES);
651 gen_op_addl_A0_reg_sN(0, R_EDI);
653 gen_op_movl_A0_reg(R_EDI);
656 gen_op_movl_A0_reg(R_EDI);
657 gen_op_andl_A0_ffff();
658 gen_op_addl_A0_seg(R_ES);
662 static inline void gen_op_movl_T0_Dshift(int ot)
664 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
665 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
668 static void gen_extu(int ot, TCGv reg)
672 tcg_gen_ext8u_tl(reg, reg);
675 tcg_gen_ext16u_tl(reg, reg);
678 tcg_gen_ext32u_tl(reg, reg);
685 static void gen_exts(int ot, TCGv reg)
689 tcg_gen_ext8s_tl(reg, reg);
692 tcg_gen_ext16s_tl(reg, reg);
695 tcg_gen_ext32s_tl(reg, reg);
702 static inline void gen_op_jnz_ecx(int size, int label1)
704 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
705 gen_extu(size + 1, cpu_tmp0);
706 tcg_gen_brcond_tl(TCG_COND_NE, cpu_tmp0, tcg_const_tl(0), label1);
709 static inline void gen_op_jz_ecx(int size, int label1)
711 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
712 gen_extu(size + 1, cpu_tmp0);
713 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), label1);
716 static void *helper_in_func[3] = {
722 static void *helper_out_func[3] = {
728 static void *gen_check_io_func[3] = {
734 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
738 target_ulong next_eip;
741 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
742 if (s->cc_op != CC_OP_DYNAMIC)
743 gen_op_set_cc_op(s->cc_op);
746 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
747 tcg_gen_helper_0_1(gen_check_io_func[ot],
750 if(s->flags & (1ULL << INTERCEPT_IOIO_PROT)) {
752 if (s->cc_op != CC_OP_DYNAMIC)
753 gen_op_set_cc_op(s->cc_op);
757 svm_flags |= (1 << (4 + ot));
758 next_eip = s->pc - s->cs_base;
759 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
760 tcg_gen_helper_0_3(helper_svm_check_io,
762 tcg_const_i32(svm_flags),
763 tcg_const_i32(next_eip - cur_eip));
767 static inline void gen_movs(DisasContext *s, int ot)
769 gen_string_movl_A0_ESI(s);
770 gen_op_ld_T0_A0(ot + s->mem_index);
771 gen_string_movl_A0_EDI(s);
772 gen_op_st_T0_A0(ot + s->mem_index);
773 gen_op_movl_T0_Dshift(ot);
774 gen_op_add_reg_T0(s->aflag, R_ESI);
775 gen_op_add_reg_T0(s->aflag, R_EDI);
778 static inline void gen_update_cc_op(DisasContext *s)
780 if (s->cc_op != CC_OP_DYNAMIC) {
781 gen_op_set_cc_op(s->cc_op);
782 s->cc_op = CC_OP_DYNAMIC;
786 static void gen_op_update1_cc(void)
788 tcg_gen_discard_tl(cpu_cc_src);
789 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
792 static void gen_op_update2_cc(void)
794 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
795 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
798 static inline void gen_op_cmpl_T0_T1_cc(void)
800 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
801 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
804 static inline void gen_op_testl_T0_T1_cc(void)
806 tcg_gen_discard_tl(cpu_cc_src);
807 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
810 static void gen_op_update_neg_cc(void)
812 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
813 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
816 /* compute eflags.C to reg */
817 static void gen_compute_eflags_c(TCGv reg)
819 #if TCG_TARGET_REG_BITS == 32
820 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
821 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
822 (long)cc_table + offsetof(CCTable, compute_c));
823 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
824 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
825 1, &cpu_tmp2_i32, 0, NULL);
827 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
828 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
829 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
830 (long)cc_table + offsetof(CCTable, compute_c));
831 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
832 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
833 1, &cpu_tmp2_i32, 0, NULL);
835 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
838 /* compute all eflags to cc_src */
839 static void gen_compute_eflags(TCGv reg)
841 #if TCG_TARGET_REG_BITS == 32
842 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
843 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
844 (long)cc_table + offsetof(CCTable, compute_all));
845 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
846 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
847 1, &cpu_tmp2_i32, 0, NULL);
849 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
850 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
851 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
852 (long)cc_table + offsetof(CCTable, compute_all));
853 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
854 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
855 1, &cpu_tmp2_i32, 0, NULL);
857 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
860 static inline void gen_setcc_slow_T0(int op)
864 gen_compute_eflags(cpu_T[0]);
865 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
866 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
869 gen_compute_eflags_c(cpu_T[0]);
872 gen_compute_eflags(cpu_T[0]);
873 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
874 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
877 gen_compute_eflags(cpu_tmp0);
878 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
879 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
880 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
883 gen_compute_eflags(cpu_T[0]);
884 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
885 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
888 gen_compute_eflags(cpu_T[0]);
889 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
890 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
893 gen_compute_eflags(cpu_tmp0);
894 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
895 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
896 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
897 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
901 gen_compute_eflags(cpu_tmp0);
902 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
903 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
904 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
905 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
906 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
907 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
912 /* return true if setcc_slow is not needed (WARNING: must be kept in
913 sync with gen_jcc1) */
914 static int is_fast_jcc_case(DisasContext *s, int b)
917 jcc_op = (b >> 1) & 7;
919 /* we optimize the cmp/jcc case */
924 if (jcc_op == JCC_O || jcc_op == JCC_P)
928 /* some jumps are easy to compute */
953 if (jcc_op != JCC_Z && jcc_op != JCC_S)
963 /* generate a conditional jump to label 'l1' according to jump opcode
964 value 'b'. In the fast case, T0 is guaranted not to be used. */
965 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
967 int inv, jcc_op, size, cond;
971 jcc_op = (b >> 1) & 7;
974 /* we optimize the cmp/jcc case */
980 size = cc_op - CC_OP_SUBB;
986 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
990 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
995 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
1003 tcg_gen_brcond_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0,
1004 tcg_const_tl(0), l1);
1010 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
1011 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1012 tcg_const_tl(0), l1);
1015 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
1016 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1017 tcg_const_tl(0), l1);
1019 #ifdef TARGET_X86_64
1021 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1022 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1023 tcg_const_tl(0), l1);
1027 tcg_gen_brcond_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1028 tcg_const_tl(0), l1);
1034 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1037 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1039 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1043 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1044 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1048 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1049 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1051 #ifdef TARGET_X86_64
1054 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1055 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1062 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1066 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1069 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1071 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1075 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1076 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1080 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1081 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1083 #ifdef TARGET_X86_64
1086 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1087 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1094 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1102 /* some jumps are easy to compute */
1144 size = (cc_op - CC_OP_ADDB) & 3;
1147 size = (cc_op - CC_OP_ADDB) & 3;
1155 gen_setcc_slow_T0(jcc_op);
1156 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1157 cpu_T[0], tcg_const_tl(0), l1);
1162 /* XXX: does not work with gdbstub "ice" single step - not a
1164 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1168 l1 = gen_new_label();
1169 l2 = gen_new_label();
1170 gen_op_jnz_ecx(s->aflag, l1);
1172 gen_jmp_tb(s, next_eip, 1);
1177 static inline void gen_stos(DisasContext *s, int ot)
1179 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1180 gen_string_movl_A0_EDI(s);
1181 gen_op_st_T0_A0(ot + s->mem_index);
1182 gen_op_movl_T0_Dshift(ot);
1183 gen_op_add_reg_T0(s->aflag, R_EDI);
1186 static inline void gen_lods(DisasContext *s, int ot)
1188 gen_string_movl_A0_ESI(s);
1189 gen_op_ld_T0_A0(ot + s->mem_index);
1190 gen_op_mov_reg_T0(ot, R_EAX);
1191 gen_op_movl_T0_Dshift(ot);
1192 gen_op_add_reg_T0(s->aflag, R_ESI);
1195 static inline void gen_scas(DisasContext *s, int ot)
1197 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1198 gen_string_movl_A0_EDI(s);
1199 gen_op_ld_T1_A0(ot + s->mem_index);
1200 gen_op_cmpl_T0_T1_cc();
1201 gen_op_movl_T0_Dshift(ot);
1202 gen_op_add_reg_T0(s->aflag, R_EDI);
1205 static inline void gen_cmps(DisasContext *s, int ot)
1207 gen_string_movl_A0_ESI(s);
1208 gen_op_ld_T0_A0(ot + s->mem_index);
1209 gen_string_movl_A0_EDI(s);
1210 gen_op_ld_T1_A0(ot + s->mem_index);
1211 gen_op_cmpl_T0_T1_cc();
1212 gen_op_movl_T0_Dshift(ot);
1213 gen_op_add_reg_T0(s->aflag, R_ESI);
1214 gen_op_add_reg_T0(s->aflag, R_EDI);
1217 static inline void gen_ins(DisasContext *s, int ot)
1219 gen_string_movl_A0_EDI(s);
1220 /* Note: we must do this dummy write first to be restartable in
1221 case of page fault. */
1223 gen_op_st_T0_A0(ot + s->mem_index);
1224 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1225 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1226 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1227 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
1228 gen_op_st_T0_A0(ot + s->mem_index);
1229 gen_op_movl_T0_Dshift(ot);
1230 gen_op_add_reg_T0(s->aflag, R_EDI);
1233 static inline void gen_outs(DisasContext *s, int ot)
1235 gen_string_movl_A0_ESI(s);
1236 gen_op_ld_T0_A0(ot + s->mem_index);
1238 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1239 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1240 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1241 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1242 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
1244 gen_op_movl_T0_Dshift(ot);
1245 gen_op_add_reg_T0(s->aflag, R_ESI);
1248 /* same method as Valgrind : we generate jumps to current or next
1250 #define GEN_REPZ(op) \
1251 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1252 target_ulong cur_eip, target_ulong next_eip) \
1255 gen_update_cc_op(s); \
1256 l2 = gen_jz_ecx_string(s, next_eip); \
1257 gen_ ## op(s, ot); \
1258 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1259 /* a loop would cause two single step exceptions if ECX = 1 \
1260 before rep string_insn */ \
1262 gen_op_jz_ecx(s->aflag, l2); \
1263 gen_jmp(s, cur_eip); \
1266 #define GEN_REPZ2(op) \
1267 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1268 target_ulong cur_eip, \
1269 target_ulong next_eip, \
1273 gen_update_cc_op(s); \
1274 l2 = gen_jz_ecx_string(s, next_eip); \
1275 gen_ ## op(s, ot); \
1276 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1277 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1278 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1280 gen_op_jz_ecx(s->aflag, l2); \
1281 gen_jmp(s, cur_eip); \
1292 static void *helper_fp_arith_ST0_FT0[8] = {
1293 helper_fadd_ST0_FT0,
1294 helper_fmul_ST0_FT0,
1295 helper_fcom_ST0_FT0,
1296 helper_fcom_ST0_FT0,
1297 helper_fsub_ST0_FT0,
1298 helper_fsubr_ST0_FT0,
1299 helper_fdiv_ST0_FT0,
1300 helper_fdivr_ST0_FT0,
1303 /* NOTE the exception in "r" op ordering */
1304 static void *helper_fp_arith_STN_ST0[8] = {
1305 helper_fadd_STN_ST0,
1306 helper_fmul_STN_ST0,
1309 helper_fsubr_STN_ST0,
1310 helper_fsub_STN_ST0,
1311 helper_fdivr_STN_ST0,
1312 helper_fdiv_STN_ST0,
1315 /* if d == OR_TMP0, it means memory operand (address in A0) */
1316 static void gen_op(DisasContext *s1, int op, int ot, int d)
1319 gen_op_mov_TN_reg(ot, 0, d);
1321 gen_op_ld_T0_A0(ot + s1->mem_index);
1325 if (s1->cc_op != CC_OP_DYNAMIC)
1326 gen_op_set_cc_op(s1->cc_op);
1327 gen_compute_eflags_c(cpu_tmp4);
1328 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1329 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1331 gen_op_mov_reg_T0(ot, d);
1333 gen_op_st_T0_A0(ot + s1->mem_index);
1334 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1335 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1336 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1337 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1338 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1339 s1->cc_op = CC_OP_DYNAMIC;
1342 if (s1->cc_op != CC_OP_DYNAMIC)
1343 gen_op_set_cc_op(s1->cc_op);
1344 gen_compute_eflags_c(cpu_tmp4);
1345 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1346 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1348 gen_op_mov_reg_T0(ot, d);
1350 gen_op_st_T0_A0(ot + s1->mem_index);
1351 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1352 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1353 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1354 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1355 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1356 s1->cc_op = CC_OP_DYNAMIC;
1359 gen_op_addl_T0_T1();
1361 gen_op_mov_reg_T0(ot, d);
1363 gen_op_st_T0_A0(ot + s1->mem_index);
1364 gen_op_update2_cc();
1365 s1->cc_op = CC_OP_ADDB + ot;
1368 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1370 gen_op_mov_reg_T0(ot, d);
1372 gen_op_st_T0_A0(ot + s1->mem_index);
1373 gen_op_update2_cc();
1374 s1->cc_op = CC_OP_SUBB + ot;
1378 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1380 gen_op_mov_reg_T0(ot, d);
1382 gen_op_st_T0_A0(ot + s1->mem_index);
1383 gen_op_update1_cc();
1384 s1->cc_op = CC_OP_LOGICB + ot;
1387 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1389 gen_op_mov_reg_T0(ot, d);
1391 gen_op_st_T0_A0(ot + s1->mem_index);
1392 gen_op_update1_cc();
1393 s1->cc_op = CC_OP_LOGICB + ot;
1396 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1398 gen_op_mov_reg_T0(ot, d);
1400 gen_op_st_T0_A0(ot + s1->mem_index);
1401 gen_op_update1_cc();
1402 s1->cc_op = CC_OP_LOGICB + ot;
1405 gen_op_cmpl_T0_T1_cc();
1406 s1->cc_op = CC_OP_SUBB + ot;
1411 /* if d == OR_TMP0, it means memory operand (address in A0) */
1412 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1415 gen_op_mov_TN_reg(ot, 0, d);
1417 gen_op_ld_T0_A0(ot + s1->mem_index);
1418 if (s1->cc_op != CC_OP_DYNAMIC)
1419 gen_op_set_cc_op(s1->cc_op);
1421 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1422 s1->cc_op = CC_OP_INCB + ot;
1424 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1425 s1->cc_op = CC_OP_DECB + ot;
1428 gen_op_mov_reg_T0(ot, d);
1430 gen_op_st_T0_A0(ot + s1->mem_index);
1431 gen_compute_eflags_c(cpu_cc_src);
1432 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1435 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1436 int is_right, int is_arith)
1448 gen_op_ld_T0_A0(ot + s->mem_index);
1450 gen_op_mov_TN_reg(ot, 0, op1);
1452 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1454 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1458 gen_exts(ot, cpu_T[0]);
1459 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1460 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1462 gen_extu(ot, cpu_T[0]);
1463 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1464 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1467 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1468 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1473 gen_op_st_T0_A0(ot + s->mem_index);
1475 gen_op_mov_reg_T0(ot, op1);
1477 /* update eflags if non zero shift */
1478 if (s->cc_op != CC_OP_DYNAMIC)
1479 gen_op_set_cc_op(s->cc_op);
1481 shift_label = gen_new_label();
1482 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), shift_label);
1484 tcg_gen_mov_tl(cpu_cc_src, cpu_T3);
1485 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1487 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1489 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1491 gen_set_label(shift_label);
1492 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1495 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1496 int is_right, int is_arith)
1507 gen_op_ld_T0_A0(ot + s->mem_index);
1509 gen_op_mov_TN_reg(ot, 0, op1);
1515 gen_exts(ot, cpu_T[0]);
1516 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1);
1517 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1519 gen_extu(ot, cpu_T[0]);
1520 tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1);
1521 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1524 tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1);
1525 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1531 gen_op_st_T0_A0(ot + s->mem_index);
1533 gen_op_mov_reg_T0(ot, op1);
1535 /* update eflags if non zero shift */
1537 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0);
1538 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1540 s->cc_op = CC_OP_SARB + ot;
1542 s->cc_op = CC_OP_SHLB + ot;
1546 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1549 tcg_gen_shli_tl(ret, arg1, arg2);
1551 tcg_gen_shri_tl(ret, arg1, -arg2);
1554 /* XXX: add faster immediate case */
1555 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1559 int label1, label2, data_bits;
1568 gen_op_ld_T0_A0(ot + s->mem_index);
1570 gen_op_mov_TN_reg(ot, 0, op1);
1572 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1574 /* Must test zero case to avoid using undefined behaviour in TCG
1576 label1 = gen_new_label();
1577 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label1);
1580 tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], (1 << (3 + ot)) - 1);
1582 tcg_gen_mov_tl(cpu_tmp0, cpu_T[1]);
1584 gen_extu(ot, cpu_T[0]);
1585 tcg_gen_mov_tl(cpu_T3, cpu_T[0]);
1587 data_bits = 8 << ot;
1588 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1589 fix TCG definition) */
1591 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
1592 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1593 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1595 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
1596 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1597 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1599 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1601 gen_set_label(label1);
1604 gen_op_st_T0_A0(ot + s->mem_index);
1606 gen_op_mov_reg_T0(ot, op1);
1609 if (s->cc_op != CC_OP_DYNAMIC)
1610 gen_op_set_cc_op(s->cc_op);
1612 label2 = gen_new_label();
1613 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label2);
1615 gen_compute_eflags(cpu_cc_src);
1616 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1617 tcg_gen_xor_tl(cpu_tmp0, cpu_T3, cpu_T[0]);
1618 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1619 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1620 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1622 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], data_bits - 1);
1624 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_C);
1625 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
1627 tcg_gen_discard_tl(cpu_cc_dst);
1628 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1630 gen_set_label(label2);
1631 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1634 static void *helper_rotc[8] = {
1638 X86_64_ONLY(helper_rclq),
1642 X86_64_ONLY(helper_rcrq),
1645 /* XXX: add faster immediate = 1 case */
1646 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1651 if (s->cc_op != CC_OP_DYNAMIC)
1652 gen_op_set_cc_op(s->cc_op);
1656 gen_op_ld_T0_A0(ot + s->mem_index);
1658 gen_op_mov_TN_reg(ot, 0, op1);
1660 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
1661 cpu_T[0], cpu_T[0], cpu_T[1]);
1664 gen_op_st_T0_A0(ot + s->mem_index);
1666 gen_op_mov_reg_T0(ot, op1);
1669 label1 = gen_new_label();
1670 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(-1), label1);
1672 tcg_gen_mov_tl(cpu_cc_src, cpu_T3);
1673 tcg_gen_discard_tl(cpu_cc_dst);
1674 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1676 gen_set_label(label1);
1677 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1680 /* XXX: add faster immediate case */
1681 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1684 int label1, label2, data_bits;
1694 gen_op_ld_T0_A0(ot + s->mem_index);
1696 gen_op_mov_TN_reg(ot, 0, op1);
1698 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1699 /* Must test zero case to avoid using undefined behaviour in TCG
1701 label1 = gen_new_label();
1702 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
1704 tcg_gen_addi_tl(cpu_tmp5, cpu_T3, -1);
1705 if (ot == OT_WORD) {
1706 /* Note: we implement the Intel behaviour for shift count > 16 */
1708 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
1709 tcg_gen_shli_tl(cpu_tmp0, cpu_T[1], 16);
1710 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1711 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
1713 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1715 /* only needed if count > 16, but a test would complicate */
1716 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
1717 tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp5);
1719 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3);
1721 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1723 /* XXX: not optimal */
1724 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
1725 tcg_gen_shli_tl(cpu_T[1], cpu_T[1], 16);
1726 tcg_gen_or_tl(cpu_T[1], cpu_T[1], cpu_T[0]);
1727 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
1729 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1730 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1731 tcg_gen_shr_tl(cpu_tmp6, cpu_T[1], cpu_tmp0);
1732 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1734 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3);
1735 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
1736 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1737 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1740 data_bits = 8 << ot;
1743 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
1745 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1747 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3);
1748 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3);
1749 tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1750 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1754 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
1756 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1758 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3);
1759 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3);
1760 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1761 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1764 tcg_gen_mov_tl(cpu_T[1], cpu_tmp4);
1766 gen_set_label(label1);
1769 gen_op_st_T0_A0(ot + s->mem_index);
1771 gen_op_mov_reg_T0(ot, op1);
1774 if (s->cc_op != CC_OP_DYNAMIC)
1775 gen_op_set_cc_op(s->cc_op);
1777 label2 = gen_new_label();
1778 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label2);
1780 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1781 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1783 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1785 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1787 gen_set_label(label2);
1788 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1791 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1794 gen_op_mov_TN_reg(ot, 1, s);
1797 gen_rot_rm_T1(s1, ot, d, 0);
1800 gen_rot_rm_T1(s1, ot, d, 1);
1804 gen_shift_rm_T1(s1, ot, d, 0, 0);
1807 gen_shift_rm_T1(s1, ot, d, 1, 0);
1810 gen_shift_rm_T1(s1, ot, d, 1, 1);
1813 gen_rotc_rm_T1(s1, ot, d, 0);
1816 gen_rotc_rm_T1(s1, ot, d, 1);
1821 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1826 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1829 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1832 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1835 /* currently not optimized */
1836 gen_op_movl_T1_im(c);
1837 gen_shift(s1, op, ot, d, OR_TMP1);
1842 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1850 int mod, rm, code, override, must_add_seg;
1852 override = s->override;
1853 must_add_seg = s->addseg;
1856 mod = (modrm >> 6) & 3;
1868 code = ldub_code(s->pc++);
1869 scale = (code >> 6) & 3;
1870 index = ((code >> 3) & 7) | REX_X(s);
1877 if ((base & 7) == 5) {
1879 disp = (int32_t)ldl_code(s->pc);
1881 if (CODE64(s) && !havesib) {
1882 disp += s->pc + s->rip_offset;
1889 disp = (int8_t)ldub_code(s->pc++);
1893 disp = ldl_code(s->pc);
1899 /* for correct popl handling with esp */
1900 if (base == 4 && s->popl_esp_hack)
1901 disp += s->popl_esp_hack;
1902 #ifdef TARGET_X86_64
1903 if (s->aflag == 2) {
1904 gen_op_movq_A0_reg(base);
1906 gen_op_addq_A0_im(disp);
1911 gen_op_movl_A0_reg(base);
1913 gen_op_addl_A0_im(disp);
1916 #ifdef TARGET_X86_64
1917 if (s->aflag == 2) {
1918 gen_op_movq_A0_im(disp);
1922 gen_op_movl_A0_im(disp);
1925 /* XXX: index == 4 is always invalid */
1926 if (havesib && (index != 4 || scale != 0)) {
1927 #ifdef TARGET_X86_64
1928 if (s->aflag == 2) {
1929 gen_op_addq_A0_reg_sN(scale, index);
1933 gen_op_addl_A0_reg_sN(scale, index);
1938 if (base == R_EBP || base == R_ESP)
1943 #ifdef TARGET_X86_64
1944 if (s->aflag == 2) {
1945 gen_op_addq_A0_seg(override);
1949 gen_op_addl_A0_seg(override);
1956 disp = lduw_code(s->pc);
1958 gen_op_movl_A0_im(disp);
1959 rm = 0; /* avoid SS override */
1966 disp = (int8_t)ldub_code(s->pc++);
1970 disp = lduw_code(s->pc);
1976 gen_op_movl_A0_reg(R_EBX);
1977 gen_op_addl_A0_reg_sN(0, R_ESI);
1980 gen_op_movl_A0_reg(R_EBX);
1981 gen_op_addl_A0_reg_sN(0, R_EDI);
1984 gen_op_movl_A0_reg(R_EBP);
1985 gen_op_addl_A0_reg_sN(0, R_ESI);
1988 gen_op_movl_A0_reg(R_EBP);
1989 gen_op_addl_A0_reg_sN(0, R_EDI);
1992 gen_op_movl_A0_reg(R_ESI);
1995 gen_op_movl_A0_reg(R_EDI);
1998 gen_op_movl_A0_reg(R_EBP);
2002 gen_op_movl_A0_reg(R_EBX);
2006 gen_op_addl_A0_im(disp);
2007 gen_op_andl_A0_ffff();
2011 if (rm == 2 || rm == 3 || rm == 6)
2016 gen_op_addl_A0_seg(override);
2026 static void gen_nop_modrm(DisasContext *s, int modrm)
2028 int mod, rm, base, code;
2030 mod = (modrm >> 6) & 3;
2040 code = ldub_code(s->pc++);
2076 /* used for LEA and MOV AX, mem */
2077 static void gen_add_A0_ds_seg(DisasContext *s)
2079 int override, must_add_seg;
2080 must_add_seg = s->addseg;
2082 if (s->override >= 0) {
2083 override = s->override;
2089 #ifdef TARGET_X86_64
2091 gen_op_addq_A0_seg(override);
2095 gen_op_addl_A0_seg(override);
2100 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
2102 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2104 int mod, rm, opreg, disp;
2106 mod = (modrm >> 6) & 3;
2107 rm = (modrm & 7) | REX_B(s);
2111 gen_op_mov_TN_reg(ot, 0, reg);
2112 gen_op_mov_reg_T0(ot, rm);
2114 gen_op_mov_TN_reg(ot, 0, rm);
2116 gen_op_mov_reg_T0(ot, reg);
2119 gen_lea_modrm(s, modrm, &opreg, &disp);
2122 gen_op_mov_TN_reg(ot, 0, reg);
2123 gen_op_st_T0_A0(ot + s->mem_index);
2125 gen_op_ld_T0_A0(ot + s->mem_index);
2127 gen_op_mov_reg_T0(ot, reg);
2132 static inline uint32_t insn_get(DisasContext *s, int ot)
2138 ret = ldub_code(s->pc);
2142 ret = lduw_code(s->pc);
2147 ret = ldl_code(s->pc);
2154 static inline int insn_const_size(unsigned int ot)
2162 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2164 TranslationBlock *tb;
2167 pc = s->cs_base + eip;
2169 /* NOTE: we handle the case where the TB spans two pages here */
2170 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2171 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2172 /* jump to same page: we can use a direct jump */
2173 tcg_gen_goto_tb(tb_num);
2175 tcg_gen_exit_tb((long)tb + tb_num);
2177 /* jump to another page: currently not optimized */
2183 static inline void gen_jcc(DisasContext *s, int b,
2184 target_ulong val, target_ulong next_eip)
2189 if (s->cc_op != CC_OP_DYNAMIC) {
2190 gen_op_set_cc_op(s->cc_op);
2191 s->cc_op = CC_OP_DYNAMIC;
2194 l1 = gen_new_label();
2195 gen_jcc1(s, cc_op, b, l1);
2197 gen_goto_tb(s, 0, next_eip);
2200 gen_goto_tb(s, 1, val);
2204 l1 = gen_new_label();
2205 l2 = gen_new_label();
2206 gen_jcc1(s, cc_op, b, l1);
2208 gen_jmp_im(next_eip);
2218 static void gen_setcc(DisasContext *s, int b)
2220 int inv, jcc_op, l1;
2222 if (is_fast_jcc_case(s, b)) {
2223 /* nominal case: we use a jump */
2224 tcg_gen_movi_tl(cpu_T[0], 0);
2225 l1 = gen_new_label();
2226 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2227 tcg_gen_movi_tl(cpu_T[0], 1);
2230 /* slow case: it is more efficient not to generate a jump,
2231 although it is questionnable whether this optimization is
2234 jcc_op = (b >> 1) & 7;
2235 if (s->cc_op != CC_OP_DYNAMIC)
2236 gen_op_set_cc_op(s->cc_op);
2237 gen_setcc_slow_T0(jcc_op);
2239 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2244 static inline void gen_op_movl_T0_seg(int seg_reg)
2246 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2247 offsetof(CPUX86State,segs[seg_reg].selector));
2250 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2252 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2253 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2254 offsetof(CPUX86State,segs[seg_reg].selector));
2255 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2256 tcg_gen_st_tl(cpu_T[0], cpu_env,
2257 offsetof(CPUX86State,segs[seg_reg].base));
2260 /* move T0 to seg_reg and compute if the CPU state may change. Never
2261 call this function with seg_reg == R_CS */
2262 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2264 if (s->pe && !s->vm86) {
2265 /* XXX: optimize by finding processor state dynamically */
2266 if (s->cc_op != CC_OP_DYNAMIC)
2267 gen_op_set_cc_op(s->cc_op);
2268 gen_jmp_im(cur_eip);
2269 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2270 tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2271 /* abort translation because the addseg value may change or
2272 because ss32 may change. For R_SS, translation must always
2273 stop as a special handling must be done to disable hardware
2274 interrupts for the next instruction */
2275 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2278 gen_op_movl_seg_T0_vm(seg_reg);
2279 if (seg_reg == R_SS)
2284 static inline int svm_is_rep(int prefixes)
2286 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2290 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2291 uint32_t type, uint64_t param)
2293 if(!(s->flags & (INTERCEPT_SVM_MASK)))
2294 /* no SVM activated */
2297 /* CRx and DRx reads/writes */
2298 case SVM_EXIT_READ_CR0 ... SVM_EXIT_EXCP_BASE - 1:
2299 if (s->cc_op != CC_OP_DYNAMIC) {
2300 gen_op_set_cc_op(s->cc_op);
2302 gen_jmp_im(pc_start - s->cs_base);
2303 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2304 tcg_const_i32(type), tcg_const_i64(param));
2305 /* this is a special case as we do not know if the interception occurs
2306 so we assume there was none */
2309 if(s->flags & (1ULL << INTERCEPT_MSR_PROT)) {
2310 if (s->cc_op != CC_OP_DYNAMIC) {
2311 gen_op_set_cc_op(s->cc_op);
2313 gen_jmp_im(pc_start - s->cs_base);
2314 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2315 tcg_const_i32(type), tcg_const_i64(param));
2316 /* this is a special case as we do not know if the interception occurs
2317 so we assume there was none */
2322 if(s->flags & (1ULL << ((type - SVM_EXIT_INTR) + INTERCEPT_INTR))) {
2323 if (s->cc_op != CC_OP_DYNAMIC) {
2324 gen_op_set_cc_op(s->cc_op);
2326 gen_jmp_im(pc_start - s->cs_base);
2327 tcg_gen_helper_0_2(helper_vmexit,
2328 tcg_const_i32(type), tcg_const_i64(param));
2329 /* we can optimize this one so TBs don't get longer
2330 than up to vmexit */
2339 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2341 return gen_svm_check_intercept_param(s, pc_start, type, 0);
2344 static inline void gen_stack_update(DisasContext *s, int addend)
2346 #ifdef TARGET_X86_64
2348 gen_op_add_reg_im(2, R_ESP, addend);
2352 gen_op_add_reg_im(1, R_ESP, addend);
2354 gen_op_add_reg_im(0, R_ESP, addend);
2358 /* generate a push. It depends on ss32, addseg and dflag */
2359 static void gen_push_T0(DisasContext *s)
2361 #ifdef TARGET_X86_64
2363 gen_op_movq_A0_reg(R_ESP);
2365 gen_op_addq_A0_im(-8);
2366 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2368 gen_op_addq_A0_im(-2);
2369 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2371 gen_op_mov_reg_A0(2, R_ESP);
2375 gen_op_movl_A0_reg(R_ESP);
2377 gen_op_addl_A0_im(-2);
2379 gen_op_addl_A0_im(-4);
2382 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2383 gen_op_addl_A0_seg(R_SS);
2386 gen_op_andl_A0_ffff();
2387 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2388 gen_op_addl_A0_seg(R_SS);
2390 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2391 if (s->ss32 && !s->addseg)
2392 gen_op_mov_reg_A0(1, R_ESP);
2394 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2398 /* generate a push. It depends on ss32, addseg and dflag */
2399 /* slower version for T1, only used for call Ev */
2400 static void gen_push_T1(DisasContext *s)
2402 #ifdef TARGET_X86_64
2404 gen_op_movq_A0_reg(R_ESP);
2406 gen_op_addq_A0_im(-8);
2407 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2409 gen_op_addq_A0_im(-2);
2410 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2412 gen_op_mov_reg_A0(2, R_ESP);
2416 gen_op_movl_A0_reg(R_ESP);
2418 gen_op_addl_A0_im(-2);
2420 gen_op_addl_A0_im(-4);
2423 gen_op_addl_A0_seg(R_SS);
2426 gen_op_andl_A0_ffff();
2427 gen_op_addl_A0_seg(R_SS);
2429 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2431 if (s->ss32 && !s->addseg)
2432 gen_op_mov_reg_A0(1, R_ESP);
2434 gen_stack_update(s, (-2) << s->dflag);
2438 /* two step pop is necessary for precise exceptions */
2439 static void gen_pop_T0(DisasContext *s)
2441 #ifdef TARGET_X86_64
2443 gen_op_movq_A0_reg(R_ESP);
2444 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2448 gen_op_movl_A0_reg(R_ESP);
2451 gen_op_addl_A0_seg(R_SS);
2453 gen_op_andl_A0_ffff();
2454 gen_op_addl_A0_seg(R_SS);
2456 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2460 static void gen_pop_update(DisasContext *s)
2462 #ifdef TARGET_X86_64
2463 if (CODE64(s) && s->dflag) {
2464 gen_stack_update(s, 8);
2468 gen_stack_update(s, 2 << s->dflag);
2472 static void gen_stack_A0(DisasContext *s)
2474 gen_op_movl_A0_reg(R_ESP);
2476 gen_op_andl_A0_ffff();
2477 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2479 gen_op_addl_A0_seg(R_SS);
2482 /* NOTE: wrap around in 16 bit not fully handled */
2483 static void gen_pusha(DisasContext *s)
2486 gen_op_movl_A0_reg(R_ESP);
2487 gen_op_addl_A0_im(-16 << s->dflag);
2489 gen_op_andl_A0_ffff();
2490 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2492 gen_op_addl_A0_seg(R_SS);
2493 for(i = 0;i < 8; i++) {
2494 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2495 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2496 gen_op_addl_A0_im(2 << s->dflag);
2498 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2501 /* NOTE: wrap around in 16 bit not fully handled */
2502 static void gen_popa(DisasContext *s)
2505 gen_op_movl_A0_reg(R_ESP);
2507 gen_op_andl_A0_ffff();
2508 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2509 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2511 gen_op_addl_A0_seg(R_SS);
2512 for(i = 0;i < 8; i++) {
2513 /* ESP is not reloaded */
2515 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2516 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2518 gen_op_addl_A0_im(2 << s->dflag);
2520 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2523 static void gen_enter(DisasContext *s, int esp_addend, int level)
2528 #ifdef TARGET_X86_64
2530 ot = s->dflag ? OT_QUAD : OT_WORD;
2533 gen_op_movl_A0_reg(R_ESP);
2534 gen_op_addq_A0_im(-opsize);
2535 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2538 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2539 gen_op_st_T0_A0(ot + s->mem_index);
2541 /* XXX: must save state */
2542 tcg_gen_helper_0_3(helper_enter64_level,
2543 tcg_const_i32(level),
2544 tcg_const_i32((ot == OT_QUAD)),
2547 gen_op_mov_reg_T1(ot, R_EBP);
2548 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2549 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2553 ot = s->dflag + OT_WORD;
2554 opsize = 2 << s->dflag;
2556 gen_op_movl_A0_reg(R_ESP);
2557 gen_op_addl_A0_im(-opsize);
2559 gen_op_andl_A0_ffff();
2560 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2562 gen_op_addl_A0_seg(R_SS);
2564 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2565 gen_op_st_T0_A0(ot + s->mem_index);
2567 /* XXX: must save state */
2568 tcg_gen_helper_0_3(helper_enter_level,
2569 tcg_const_i32(level),
2570 tcg_const_i32(s->dflag),
2573 gen_op_mov_reg_T1(ot, R_EBP);
2574 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2575 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2579 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2581 if (s->cc_op != CC_OP_DYNAMIC)
2582 gen_op_set_cc_op(s->cc_op);
2583 gen_jmp_im(cur_eip);
2584 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
2588 /* an interrupt is different from an exception because of the
2590 static void gen_interrupt(DisasContext *s, int intno,
2591 target_ulong cur_eip, target_ulong next_eip)
2593 if (s->cc_op != CC_OP_DYNAMIC)
2594 gen_op_set_cc_op(s->cc_op);
2595 gen_jmp_im(cur_eip);
2596 tcg_gen_helper_0_2(helper_raise_interrupt,
2597 tcg_const_i32(intno),
2598 tcg_const_i32(next_eip - cur_eip));
2602 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2604 if (s->cc_op != CC_OP_DYNAMIC)
2605 gen_op_set_cc_op(s->cc_op);
2606 gen_jmp_im(cur_eip);
2607 tcg_gen_helper_0_0(helper_debug);
2611 /* generate a generic end of block. Trace exception is also generated
2613 static void gen_eob(DisasContext *s)
2615 if (s->cc_op != CC_OP_DYNAMIC)
2616 gen_op_set_cc_op(s->cc_op);
2617 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2618 tcg_gen_helper_0_0(helper_reset_inhibit_irq);
2620 if (s->singlestep_enabled) {
2621 tcg_gen_helper_0_0(helper_debug);
2623 tcg_gen_helper_0_0(helper_single_step);
2630 /* generate a jump to eip. No segment change must happen before as a
2631 direct call to the next block may occur */
2632 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2635 if (s->cc_op != CC_OP_DYNAMIC) {
2636 gen_op_set_cc_op(s->cc_op);
2637 s->cc_op = CC_OP_DYNAMIC;
2639 gen_goto_tb(s, tb_num, eip);
2647 static void gen_jmp(DisasContext *s, target_ulong eip)
2649 gen_jmp_tb(s, eip, 0);
2652 static inline void gen_ldq_env_A0(int idx, int offset)
2654 int mem_index = (idx >> 2) - 1;
2655 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2656 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2659 static inline void gen_stq_env_A0(int idx, int offset)
2661 int mem_index = (idx >> 2) - 1;
2662 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2663 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2666 static inline void gen_ldo_env_A0(int idx, int offset)
2668 int mem_index = (idx >> 2) - 1;
2669 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2670 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2671 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2672 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2673 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2676 static inline void gen_sto_env_A0(int idx, int offset)
2678 int mem_index = (idx >> 2) - 1;
2679 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2680 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2681 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2682 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2683 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2686 static inline void gen_op_movo(int d_offset, int s_offset)
2688 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2689 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2690 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2691 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2694 static inline void gen_op_movq(int d_offset, int s_offset)
2696 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2697 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2700 static inline void gen_op_movl(int d_offset, int s_offset)
2702 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2703 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2706 static inline void gen_op_movq_env_0(int d_offset)
2708 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2709 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2712 #define SSE_SPECIAL ((void *)1)
2713 #define SSE_DUMMY ((void *)2)
2715 #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2716 #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2717 helper_ ## x ## ss, helper_ ## x ## sd, }
2719 static void *sse_op_table1[256][4] = {
2720 /* 3DNow! extensions */
2721 [0x0e] = { SSE_DUMMY }, /* femms */
2722 [0x0f] = { SSE_DUMMY }, /* pf... */
2723 /* pure SSE operations */
2724 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2725 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2726 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2727 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2728 [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
2729 [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
2730 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2731 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2733 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2734 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2735 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2736 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2737 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2738 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2739 [0x2e] = { helper_ucomiss, helper_ucomisd },
2740 [0x2f] = { helper_comiss, helper_comisd },
2741 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2742 [0x51] = SSE_FOP(sqrt),
2743 [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL },
2744 [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL },
2745 [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */
2746 [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */
2747 [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */
2748 [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */
2749 [0x58] = SSE_FOP(add),
2750 [0x59] = SSE_FOP(mul),
2751 [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
2752 helper_cvtss2sd, helper_cvtsd2ss },
2753 [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
2754 [0x5c] = SSE_FOP(sub),
2755 [0x5d] = SSE_FOP(min),
2756 [0x5e] = SSE_FOP(div),
2757 [0x5f] = SSE_FOP(max),
2759 [0xc2] = SSE_FOP(cmpeq),
2760 [0xc6] = { helper_shufps, helper_shufpd },
2762 /* MMX ops and their SSE extensions */
2763 [0x60] = MMX_OP2(punpcklbw),
2764 [0x61] = MMX_OP2(punpcklwd),
2765 [0x62] = MMX_OP2(punpckldq),
2766 [0x63] = MMX_OP2(packsswb),
2767 [0x64] = MMX_OP2(pcmpgtb),
2768 [0x65] = MMX_OP2(pcmpgtw),
2769 [0x66] = MMX_OP2(pcmpgtl),
2770 [0x67] = MMX_OP2(packuswb),
2771 [0x68] = MMX_OP2(punpckhbw),
2772 [0x69] = MMX_OP2(punpckhwd),
2773 [0x6a] = MMX_OP2(punpckhdq),
2774 [0x6b] = MMX_OP2(packssdw),
2775 [0x6c] = { NULL, helper_punpcklqdq_xmm },
2776 [0x6d] = { NULL, helper_punpckhqdq_xmm },
2777 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2778 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2779 [0x70] = { helper_pshufw_mmx,
2782 helper_pshuflw_xmm },
2783 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2784 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2785 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2786 [0x74] = MMX_OP2(pcmpeqb),
2787 [0x75] = MMX_OP2(pcmpeqw),
2788 [0x76] = MMX_OP2(pcmpeql),
2789 [0x77] = { SSE_DUMMY }, /* emms */
2790 [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps },
2791 [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps },
2792 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2793 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2794 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2795 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2796 [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps },
2797 [0xd1] = MMX_OP2(psrlw),
2798 [0xd2] = MMX_OP2(psrld),
2799 [0xd3] = MMX_OP2(psrlq),
2800 [0xd4] = MMX_OP2(paddq),
2801 [0xd5] = MMX_OP2(pmullw),
2802 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2803 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2804 [0xd8] = MMX_OP2(psubusb),
2805 [0xd9] = MMX_OP2(psubusw),
2806 [0xda] = MMX_OP2(pminub),
2807 [0xdb] = MMX_OP2(pand),
2808 [0xdc] = MMX_OP2(paddusb),
2809 [0xdd] = MMX_OP2(paddusw),
2810 [0xde] = MMX_OP2(pmaxub),
2811 [0xdf] = MMX_OP2(pandn),
2812 [0xe0] = MMX_OP2(pavgb),
2813 [0xe1] = MMX_OP2(psraw),
2814 [0xe2] = MMX_OP2(psrad),
2815 [0xe3] = MMX_OP2(pavgw),
2816 [0xe4] = MMX_OP2(pmulhuw),
2817 [0xe5] = MMX_OP2(pmulhw),
2818 [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq },
2819 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2820 [0xe8] = MMX_OP2(psubsb),
2821 [0xe9] = MMX_OP2(psubsw),
2822 [0xea] = MMX_OP2(pminsw),
2823 [0xeb] = MMX_OP2(por),
2824 [0xec] = MMX_OP2(paddsb),
2825 [0xed] = MMX_OP2(paddsw),
2826 [0xee] = MMX_OP2(pmaxsw),
2827 [0xef] = MMX_OP2(pxor),
2828 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2829 [0xf1] = MMX_OP2(psllw),
2830 [0xf2] = MMX_OP2(pslld),
2831 [0xf3] = MMX_OP2(psllq),
2832 [0xf4] = MMX_OP2(pmuludq),
2833 [0xf5] = MMX_OP2(pmaddwd),
2834 [0xf6] = MMX_OP2(psadbw),
2835 [0xf7] = MMX_OP2(maskmov),
2836 [0xf8] = MMX_OP2(psubb),
2837 [0xf9] = MMX_OP2(psubw),
2838 [0xfa] = MMX_OP2(psubl),
2839 [0xfb] = MMX_OP2(psubq),
2840 [0xfc] = MMX_OP2(paddb),
2841 [0xfd] = MMX_OP2(paddw),
2842 [0xfe] = MMX_OP2(paddl),
2845 static void *sse_op_table2[3 * 8][2] = {
2846 [0 + 2] = MMX_OP2(psrlw),
2847 [0 + 4] = MMX_OP2(psraw),
2848 [0 + 6] = MMX_OP2(psllw),
2849 [8 + 2] = MMX_OP2(psrld),
2850 [8 + 4] = MMX_OP2(psrad),
2851 [8 + 6] = MMX_OP2(pslld),
2852 [16 + 2] = MMX_OP2(psrlq),
2853 [16 + 3] = { NULL, helper_psrldq_xmm },
2854 [16 + 6] = MMX_OP2(psllq),
2855 [16 + 7] = { NULL, helper_pslldq_xmm },
2858 static void *sse_op_table3[4 * 3] = {
2861 X86_64_ONLY(helper_cvtsq2ss),
2862 X86_64_ONLY(helper_cvtsq2sd),
2866 X86_64_ONLY(helper_cvttss2sq),
2867 X86_64_ONLY(helper_cvttsd2sq),
2871 X86_64_ONLY(helper_cvtss2sq),
2872 X86_64_ONLY(helper_cvtsd2sq),
2875 static void *sse_op_table4[8][4] = {
2886 static void *sse_op_table5[256] = {
2887 [0x0c] = helper_pi2fw,
2888 [0x0d] = helper_pi2fd,
2889 [0x1c] = helper_pf2iw,
2890 [0x1d] = helper_pf2id,
2891 [0x8a] = helper_pfnacc,
2892 [0x8e] = helper_pfpnacc,
2893 [0x90] = helper_pfcmpge,
2894 [0x94] = helper_pfmin,
2895 [0x96] = helper_pfrcp,
2896 [0x97] = helper_pfrsqrt,
2897 [0x9a] = helper_pfsub,
2898 [0x9e] = helper_pfadd,
2899 [0xa0] = helper_pfcmpgt,
2900 [0xa4] = helper_pfmax,
2901 [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */
2902 [0xa7] = helper_movq, /* pfrsqit1 */
2903 [0xaa] = helper_pfsubr,
2904 [0xae] = helper_pfacc,
2905 [0xb0] = helper_pfcmpeq,
2906 [0xb4] = helper_pfmul,
2907 [0xb6] = helper_movq, /* pfrcpit2 */
2908 [0xb7] = helper_pmulhrw_mmx,
2909 [0xbb] = helper_pswapd,
2910 [0xbf] = helper_pavgb_mmx /* pavgusb */
2913 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2915 int b1, op1_offset, op2_offset, is_xmm, val, ot;
2916 int modrm, mod, rm, reg, reg_addr, offset_addr;
2920 if (s->prefix & PREFIX_DATA)
2922 else if (s->prefix & PREFIX_REPZ)
2924 else if (s->prefix & PREFIX_REPNZ)
2928 sse_op2 = sse_op_table1[b][b1];
2931 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2941 /* simple MMX/SSE operation */
2942 if (s->flags & HF_TS_MASK) {
2943 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2946 if (s->flags & HF_EM_MASK) {
2948 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2951 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2954 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
2957 tcg_gen_helper_0_0(helper_emms);
2962 tcg_gen_helper_0_0(helper_emms);
2965 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
2966 the static cpu state) */
2968 tcg_gen_helper_0_0(helper_enter_mmx);
2971 modrm = ldub_code(s->pc++);
2972 reg = ((modrm >> 3) & 7);
2975 mod = (modrm >> 6) & 3;
2976 if (sse_op2 == SSE_SPECIAL) {
2979 case 0x0e7: /* movntq */
2982 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2983 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
2985 case 0x1e7: /* movntdq */
2986 case 0x02b: /* movntps */
2987 case 0x12b: /* movntps */
2988 case 0x3f0: /* lddqu */
2991 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
2992 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2994 case 0x6e: /* movd mm, ea */
2995 #ifdef TARGET_X86_64
2996 if (s->dflag == 2) {
2997 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
2998 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3002 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3003 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3004 offsetof(CPUX86State,fpregs[reg].mmx));
3005 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
3008 case 0x16e: /* movd xmm, ea */
3009 #ifdef TARGET_X86_64
3010 if (s->dflag == 2) {
3011 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3012 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3013 offsetof(CPUX86State,xmm_regs[reg]));
3014 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
3018 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3019 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3020 offsetof(CPUX86State,xmm_regs[reg]));
3021 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3022 tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
3025 case 0x6f: /* movq mm, ea */
3027 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3028 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3031 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3032 offsetof(CPUX86State,fpregs[rm].mmx));
3033 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3034 offsetof(CPUX86State,fpregs[reg].mmx));
3037 case 0x010: /* movups */
3038 case 0x110: /* movupd */
3039 case 0x028: /* movaps */
3040 case 0x128: /* movapd */
3041 case 0x16f: /* movdqa xmm, ea */
3042 case 0x26f: /* movdqu xmm, ea */
3044 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3045 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3047 rm = (modrm & 7) | REX_B(s);
3048 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3049 offsetof(CPUX86State,xmm_regs[rm]));
3052 case 0x210: /* movss xmm, ea */
3054 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3055 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3056 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3058 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3059 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3060 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3062 rm = (modrm & 7) | REX_B(s);
3063 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3064 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3067 case 0x310: /* movsd xmm, ea */
3069 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3070 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3072 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3073 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3075 rm = (modrm & 7) | REX_B(s);
3076 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3077 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3080 case 0x012: /* movlps */
3081 case 0x112: /* movlpd */
3083 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3084 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3087 rm = (modrm & 7) | REX_B(s);
3088 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3089 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3092 case 0x212: /* movsldup */
3094 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3095 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3097 rm = (modrm & 7) | REX_B(s);
3098 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3099 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3100 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3101 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3103 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3104 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3105 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3106 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3108 case 0x312: /* movddup */
3110 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3111 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3113 rm = (modrm & 7) | REX_B(s);
3114 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3115 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3117 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3118 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3120 case 0x016: /* movhps */
3121 case 0x116: /* movhpd */
3123 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3124 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3127 rm = (modrm & 7) | REX_B(s);
3128 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3129 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3132 case 0x216: /* movshdup */
3134 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3135 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3137 rm = (modrm & 7) | REX_B(s);
3138 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3139 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3140 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3141 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3143 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3144 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3145 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3146 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3148 case 0x7e: /* movd ea, mm */
3149 #ifdef TARGET_X86_64
3150 if (s->dflag == 2) {
3151 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3152 offsetof(CPUX86State,fpregs[reg].mmx));
3153 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3157 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3158 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3159 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3162 case 0x17e: /* movd ea, xmm */
3163 #ifdef TARGET_X86_64
3164 if (s->dflag == 2) {
3165 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3166 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3167 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3171 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3172 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3173 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3176 case 0x27e: /* movq xmm, ea */
3178 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3179 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3181 rm = (modrm & 7) | REX_B(s);
3182 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3183 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3185 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3187 case 0x7f: /* movq ea, mm */
3189 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3190 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3193 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3194 offsetof(CPUX86State,fpregs[reg].mmx));
3197 case 0x011: /* movups */
3198 case 0x111: /* movupd */
3199 case 0x029: /* movaps */
3200 case 0x129: /* movapd */
3201 case 0x17f: /* movdqa ea, xmm */
3202 case 0x27f: /* movdqu ea, xmm */
3204 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3205 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3207 rm = (modrm & 7) | REX_B(s);
3208 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3209 offsetof(CPUX86State,xmm_regs[reg]));
3212 case 0x211: /* movss ea, xmm */
3214 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3215 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3216 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3218 rm = (modrm & 7) | REX_B(s);
3219 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3220 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3223 case 0x311: /* movsd ea, xmm */
3225 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3226 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3228 rm = (modrm & 7) | REX_B(s);
3229 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3230 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3233 case 0x013: /* movlps */
3234 case 0x113: /* movlpd */
3236 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3237 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3242 case 0x017: /* movhps */
3243 case 0x117: /* movhpd */
3245 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3246 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3251 case 0x71: /* shift mm, im */
3254 case 0x171: /* shift xmm, im */
3257 val = ldub_code(s->pc++);
3259 gen_op_movl_T0_im(val);
3260 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3262 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3263 op1_offset = offsetof(CPUX86State,xmm_t0);
3265 gen_op_movl_T0_im(val);
3266 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3268 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3269 op1_offset = offsetof(CPUX86State,mmx_t0);
3271 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3275 rm = (modrm & 7) | REX_B(s);
3276 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3279 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3281 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3282 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3283 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3285 case 0x050: /* movmskps */
3286 rm = (modrm & 7) | REX_B(s);
3287 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3288 offsetof(CPUX86State,xmm_regs[rm]));
3289 tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
3290 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3291 gen_op_mov_reg_T0(OT_LONG, reg);
3293 case 0x150: /* movmskpd */
3294 rm = (modrm & 7) | REX_B(s);
3295 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3296 offsetof(CPUX86State,xmm_regs[rm]));
3297 tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
3298 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3299 gen_op_mov_reg_T0(OT_LONG, reg);
3301 case 0x02a: /* cvtpi2ps */
3302 case 0x12a: /* cvtpi2pd */
3303 tcg_gen_helper_0_0(helper_enter_mmx);
3305 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3306 op2_offset = offsetof(CPUX86State,mmx_t0);
3307 gen_ldq_env_A0(s->mem_index, op2_offset);
3310 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3312 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3313 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3314 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3317 tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1);
3321 tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1);
3325 case 0x22a: /* cvtsi2ss */
3326 case 0x32a: /* cvtsi2sd */
3327 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3328 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3329 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3330 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3331 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3332 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3333 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
3335 case 0x02c: /* cvttps2pi */
3336 case 0x12c: /* cvttpd2pi */
3337 case 0x02d: /* cvtps2pi */
3338 case 0x12d: /* cvtpd2pi */
3339 tcg_gen_helper_0_0(helper_enter_mmx);
3341 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3342 op2_offset = offsetof(CPUX86State,xmm_t0);
3343 gen_ldo_env_A0(s->mem_index, op2_offset);
3345 rm = (modrm & 7) | REX_B(s);
3346 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3348 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3349 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3350 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3353 tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1);
3356 tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1);
3359 tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1);
3362 tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1);
3366 case 0x22c: /* cvttss2si */
3367 case 0x32c: /* cvttsd2si */
3368 case 0x22d: /* cvtss2si */
3369 case 0x32d: /* cvtsd2si */
3370 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3372 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3374 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3376 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3377 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3379 op2_offset = offsetof(CPUX86State,xmm_t0);
3381 rm = (modrm & 7) | REX_B(s);
3382 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3384 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3386 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3387 if (ot == OT_LONG) {
3388 tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
3389 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3391 tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
3393 gen_op_mov_reg_T0(ot, reg);
3395 case 0xc4: /* pinsrw */
3398 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3399 val = ldub_code(s->pc++);
3402 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3403 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3406 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3407 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3410 case 0xc5: /* pextrw */
3414 val = ldub_code(s->pc++);
3417 rm = (modrm & 7) | REX_B(s);
3418 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3419 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3423 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3424 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3426 reg = ((modrm >> 3) & 7) | rex_r;
3427 gen_op_mov_reg_T0(OT_LONG, reg);
3429 case 0x1d6: /* movq ea, xmm */
3431 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3432 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3434 rm = (modrm & 7) | REX_B(s);
3435 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3436 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3437 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3440 case 0x2d6: /* movq2dq */
3441 tcg_gen_helper_0_0(helper_enter_mmx);
3443 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3444 offsetof(CPUX86State,fpregs[rm].mmx));
3445 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3447 case 0x3d6: /* movdq2q */
3448 tcg_gen_helper_0_0(helper_enter_mmx);
3449 rm = (modrm & 7) | REX_B(s);
3450 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3451 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3453 case 0xd7: /* pmovmskb */
3458 rm = (modrm & 7) | REX_B(s);
3459 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3460 tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
3463 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3464 tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
3466 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3467 reg = ((modrm >> 3) & 7) | rex_r;
3468 gen_op_mov_reg_T0(OT_LONG, reg);
3474 /* generic MMX or SSE operation */
3476 case 0x70: /* pshufx insn */
3477 case 0xc6: /* pshufx insn */
3478 case 0xc2: /* compare insns */
3485 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3487 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3488 op2_offset = offsetof(CPUX86State,xmm_t0);
3489 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3491 /* specific case for SSE single instructions */
3494 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3495 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3498 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3501 gen_ldo_env_A0(s->mem_index, op2_offset);
3504 rm = (modrm & 7) | REX_B(s);
3505 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3508 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3510 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3511 op2_offset = offsetof(CPUX86State,mmx_t0);
3512 gen_ldq_env_A0(s->mem_index, op2_offset);
3515 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3519 case 0x0f: /* 3DNow! data insns */
3520 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3522 val = ldub_code(s->pc++);
3523 sse_op2 = sse_op_table5[val];
3526 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3527 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3528 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3530 case 0x70: /* pshufx insn */
3531 case 0xc6: /* pshufx insn */
3532 val = ldub_code(s->pc++);
3533 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3534 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3535 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3539 val = ldub_code(s->pc++);
3542 sse_op2 = sse_op_table4[val][b1];
3543 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3544 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3545 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3548 /* maskmov : we must prepare A0 */
3551 #ifdef TARGET_X86_64
3552 if (s->aflag == 2) {
3553 gen_op_movq_A0_reg(R_EDI);
3557 gen_op_movl_A0_reg(R_EDI);
3559 gen_op_andl_A0_ffff();
3561 gen_add_A0_ds_seg(s);
3563 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3564 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3565 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0);
3568 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3569 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3570 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3573 if (b == 0x2e || b == 0x2f) {
3574 s->cc_op = CC_OP_EFLAGS;
3579 /* convert one instruction. s->is_jmp is set if the translation must
3580 be stopped. Return the next pc value */
3581 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3583 int b, prefixes, aflag, dflag;
3585 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3586 target_ulong next_eip, tval;
3596 #ifdef TARGET_X86_64
3601 s->rip_offset = 0; /* for relative ip address */
3603 b = ldub_code(s->pc);
3605 /* check prefixes */
3606 #ifdef TARGET_X86_64
3610 prefixes |= PREFIX_REPZ;
3613 prefixes |= PREFIX_REPNZ;
3616 prefixes |= PREFIX_LOCK;
3637 prefixes |= PREFIX_DATA;
3640 prefixes |= PREFIX_ADR;
3644 rex_w = (b >> 3) & 1;
3645 rex_r = (b & 0x4) << 1;
3646 s->rex_x = (b & 0x2) << 2;
3647 REX_B(s) = (b & 0x1) << 3;
3648 x86_64_hregs = 1; /* select uniform byte register addressing */
3652 /* 0x66 is ignored if rex.w is set */
3655 if (prefixes & PREFIX_DATA)
3658 if (!(prefixes & PREFIX_ADR))
3665 prefixes |= PREFIX_REPZ;
3668 prefixes |= PREFIX_REPNZ;
3671 prefixes |= PREFIX_LOCK;
3692 prefixes |= PREFIX_DATA;
3695 prefixes |= PREFIX_ADR;
3698 if (prefixes & PREFIX_DATA)
3700 if (prefixes & PREFIX_ADR)
3704 s->prefix = prefixes;
3708 /* lock generation */
3709 if (prefixes & PREFIX_LOCK)
3710 tcg_gen_helper_0_0(helper_lock);
3712 /* now check op code */
3716 /**************************/
3717 /* extended op code */
3718 b = ldub_code(s->pc++) | 0x100;
3721 /**************************/
3739 ot = dflag + OT_WORD;
3742 case 0: /* OP Ev, Gv */
3743 modrm = ldub_code(s->pc++);
3744 reg = ((modrm >> 3) & 7) | rex_r;
3745 mod = (modrm >> 6) & 3;
3746 rm = (modrm & 7) | REX_B(s);
3748 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3750 } else if (op == OP_XORL && rm == reg) {
3752 /* xor reg, reg optimisation */
3754 s->cc_op = CC_OP_LOGICB + ot;
3755 gen_op_mov_reg_T0(ot, reg);
3756 gen_op_update1_cc();
3761 gen_op_mov_TN_reg(ot, 1, reg);
3762 gen_op(s, op, ot, opreg);
3764 case 1: /* OP Gv, Ev */
3765 modrm = ldub_code(s->pc++);
3766 mod = (modrm >> 6) & 3;
3767 reg = ((modrm >> 3) & 7) | rex_r;
3768 rm = (modrm & 7) | REX_B(s);
3770 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3771 gen_op_ld_T1_A0(ot + s->mem_index);
3772 } else if (op == OP_XORL && rm == reg) {
3775 gen_op_mov_TN_reg(ot, 1, rm);
3777 gen_op(s, op, ot, reg);
3779 case 2: /* OP A, Iv */
3780 val = insn_get(s, ot);
3781 gen_op_movl_T1_im(val);
3782 gen_op(s, op, ot, OR_EAX);
3788 case 0x80: /* GRP1 */
3798 ot = dflag + OT_WORD;
3800 modrm = ldub_code(s->pc++);
3801 mod = (modrm >> 6) & 3;
3802 rm = (modrm & 7) | REX_B(s);
3803 op = (modrm >> 3) & 7;
3809 s->rip_offset = insn_const_size(ot);
3810 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3821 val = insn_get(s, ot);
3824 val = (int8_t)insn_get(s, OT_BYTE);
3827 gen_op_movl_T1_im(val);
3828 gen_op(s, op, ot, opreg);
3832 /**************************/
3833 /* inc, dec, and other misc arith */
3834 case 0x40 ... 0x47: /* inc Gv */
3835 ot = dflag ? OT_LONG : OT_WORD;
3836 gen_inc(s, ot, OR_EAX + (b & 7), 1);
3838 case 0x48 ... 0x4f: /* dec Gv */
3839 ot = dflag ? OT_LONG : OT_WORD;
3840 gen_inc(s, ot, OR_EAX + (b & 7), -1);
3842 case 0xf6: /* GRP3 */
3847 ot = dflag + OT_WORD;
3849 modrm = ldub_code(s->pc++);
3850 mod = (modrm >> 6) & 3;
3851 rm = (modrm & 7) | REX_B(s);
3852 op = (modrm >> 3) & 7;
3855 s->rip_offset = insn_const_size(ot);
3856 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3857 gen_op_ld_T0_A0(ot + s->mem_index);
3859 gen_op_mov_TN_reg(ot, 0, rm);
3864 val = insn_get(s, ot);
3865 gen_op_movl_T1_im(val);
3866 gen_op_testl_T0_T1_cc();
3867 s->cc_op = CC_OP_LOGICB + ot;
3870 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
3872 gen_op_st_T0_A0(ot + s->mem_index);
3874 gen_op_mov_reg_T0(ot, rm);
3878 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
3880 gen_op_st_T0_A0(ot + s->mem_index);
3882 gen_op_mov_reg_T0(ot, rm);
3884 gen_op_update_neg_cc();
3885 s->cc_op = CC_OP_SUBB + ot;
3890 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
3891 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
3892 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
3893 /* XXX: use 32 bit mul which could be faster */
3894 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3895 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3896 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3897 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
3898 s->cc_op = CC_OP_MULB;
3901 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
3902 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
3903 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
3904 /* XXX: use 32 bit mul which could be faster */
3905 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3906 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3907 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3908 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
3909 gen_op_mov_reg_T0(OT_WORD, R_EDX);
3910 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3911 s->cc_op = CC_OP_MULW;
3915 #ifdef TARGET_X86_64
3916 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
3917 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
3918 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
3919 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3920 gen_op_mov_reg_T0(OT_LONG, R_EAX);
3921 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3922 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
3923 gen_op_mov_reg_T0(OT_LONG, R_EDX);
3924 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3928 t0 = tcg_temp_new(TCG_TYPE_I64);
3929 t1 = tcg_temp_new(TCG_TYPE_I64);
3930 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
3931 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
3932 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
3933 tcg_gen_mul_i64(t0, t0, t1);
3934 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
3935 gen_op_mov_reg_T0(OT_LONG, R_EAX);
3936 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3937 tcg_gen_shri_i64(t0, t0, 32);
3938 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
3939 gen_op_mov_reg_T0(OT_LONG, R_EDX);
3940 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3943 s->cc_op = CC_OP_MULL;
3945 #ifdef TARGET_X86_64
3947 tcg_gen_helper_0_1(helper_mulq_EAX_T0, cpu_T[0]);
3948 s->cc_op = CC_OP_MULQ;
3956 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
3957 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
3958 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
3959 /* XXX: use 32 bit mul which could be faster */
3960 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3961 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3962 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3963 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
3964 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3965 s->cc_op = CC_OP_MULB;
3968 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
3969 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
3970 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
3971 /* XXX: use 32 bit mul which could be faster */
3972 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3973 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3974 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3975 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
3976 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3977 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
3978 gen_op_mov_reg_T0(OT_WORD, R_EDX);
3979 s->cc_op = CC_OP_MULW;
3983 #ifdef TARGET_X86_64
3984 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
3985 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
3986 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
3987 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3988 gen_op_mov_reg_T0(OT_LONG, R_EAX);
3989 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3990 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
3991 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3992 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
3993 gen_op_mov_reg_T0(OT_LONG, R_EDX);
3997 t0 = tcg_temp_new(TCG_TYPE_I64);
3998 t1 = tcg_temp_new(TCG_TYPE_I64);
3999 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4000 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4001 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4002 tcg_gen_mul_i64(t0, t0, t1);
4003 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4004 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4005 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4006 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4007 tcg_gen_shri_i64(t0, t0, 32);
4008 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4009 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4010 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4013 s->cc_op = CC_OP_MULL;
4015 #ifdef TARGET_X86_64
4017 tcg_gen_helper_0_1(helper_imulq_EAX_T0, cpu_T[0]);
4018 s->cc_op = CC_OP_MULQ;
4026 gen_jmp_im(pc_start - s->cs_base);
4027 tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
4030 gen_jmp_im(pc_start - s->cs_base);
4031 tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
4035 gen_jmp_im(pc_start - s->cs_base);
4036 tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
4038 #ifdef TARGET_X86_64
4040 gen_jmp_im(pc_start - s->cs_base);
4041 tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
4049 gen_jmp_im(pc_start - s->cs_base);
4050 tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
4053 gen_jmp_im(pc_start - s->cs_base);
4054 tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
4058 gen_jmp_im(pc_start - s->cs_base);
4059 tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
4061 #ifdef TARGET_X86_64
4063 gen_jmp_im(pc_start - s->cs_base);
4064 tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
4074 case 0xfe: /* GRP4 */
4075 case 0xff: /* GRP5 */
4079 ot = dflag + OT_WORD;
4081 modrm = ldub_code(s->pc++);
4082 mod = (modrm >> 6) & 3;
4083 rm = (modrm & 7) | REX_B(s);
4084 op = (modrm >> 3) & 7;
4085 if (op >= 2 && b == 0xfe) {
4089 if (op == 2 || op == 4) {
4090 /* operand size for jumps is 64 bit */
4092 } else if (op == 3 || op == 5) {
4093 /* for call calls, the operand is 16 or 32 bit, even
4095 ot = dflag ? OT_LONG : OT_WORD;
4096 } else if (op == 6) {
4097 /* default push size is 64 bit */
4098 ot = dflag ? OT_QUAD : OT_WORD;
4102 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4103 if (op >= 2 && op != 3 && op != 5)
4104 gen_op_ld_T0_A0(ot + s->mem_index);
4106 gen_op_mov_TN_reg(ot, 0, rm);
4110 case 0: /* inc Ev */
4115 gen_inc(s, ot, opreg, 1);
4117 case 1: /* dec Ev */
4122 gen_inc(s, ot, opreg, -1);
4124 case 2: /* call Ev */
4125 /* XXX: optimize if memory (no 'and' is necessary) */
4127 gen_op_andl_T0_ffff();
4128 next_eip = s->pc - s->cs_base;
4129 gen_movtl_T1_im(next_eip);
4134 case 3: /* lcall Ev */
4135 gen_op_ld_T1_A0(ot + s->mem_index);
4136 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4137 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4139 if (s->pe && !s->vm86) {
4140 if (s->cc_op != CC_OP_DYNAMIC)
4141 gen_op_set_cc_op(s->cc_op);
4142 gen_jmp_im(pc_start - s->cs_base);
4143 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4144 tcg_gen_helper_0_4(helper_lcall_protected,
4145 cpu_tmp2_i32, cpu_T[1],
4146 tcg_const_i32(dflag),
4147 tcg_const_i32(s->pc - pc_start));
4149 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4150 tcg_gen_helper_0_4(helper_lcall_real,
4151 cpu_tmp2_i32, cpu_T[1],
4152 tcg_const_i32(dflag),
4153 tcg_const_i32(s->pc - s->cs_base));
4157 case 4: /* jmp Ev */
4159 gen_op_andl_T0_ffff();
4163 case 5: /* ljmp Ev */
4164 gen_op_ld_T1_A0(ot + s->mem_index);
4165 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4166 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4168 if (s->pe && !s->vm86) {
4169 if (s->cc_op != CC_OP_DYNAMIC)
4170 gen_op_set_cc_op(s->cc_op);
4171 gen_jmp_im(pc_start - s->cs_base);
4172 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4173 tcg_gen_helper_0_3(helper_ljmp_protected,
4176 tcg_const_i32(s->pc - pc_start));
4178 gen_op_movl_seg_T0_vm(R_CS);
4179 gen_op_movl_T0_T1();
4184 case 6: /* push Ev */
4192 case 0x84: /* test Ev, Gv */
4197 ot = dflag + OT_WORD;
4199 modrm = ldub_code(s->pc++);
4200 mod = (modrm >> 6) & 3;
4201 rm = (modrm & 7) | REX_B(s);
4202 reg = ((modrm >> 3) & 7) | rex_r;
4204 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4205 gen_op_mov_TN_reg(ot, 1, reg);
4206 gen_op_testl_T0_T1_cc();
4207 s->cc_op = CC_OP_LOGICB + ot;
4210 case 0xa8: /* test eAX, Iv */
4215 ot = dflag + OT_WORD;
4216 val = insn_get(s, ot);
4218 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4219 gen_op_movl_T1_im(val);
4220 gen_op_testl_T0_T1_cc();
4221 s->cc_op = CC_OP_LOGICB + ot;
4224 case 0x98: /* CWDE/CBW */
4225 #ifdef TARGET_X86_64
4227 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4228 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4229 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4233 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4234 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4235 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4237 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4238 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4239 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4242 case 0x99: /* CDQ/CWD */
4243 #ifdef TARGET_X86_64
4245 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4246 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4247 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4251 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4252 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4253 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4254 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4256 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4257 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4258 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4259 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4262 case 0x1af: /* imul Gv, Ev */
4263 case 0x69: /* imul Gv, Ev, I */
4265 ot = dflag + OT_WORD;
4266 modrm = ldub_code(s->pc++);
4267 reg = ((modrm >> 3) & 7) | rex_r;
4269 s->rip_offset = insn_const_size(ot);
4272 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4274 val = insn_get(s, ot);
4275 gen_op_movl_T1_im(val);
4276 } else if (b == 0x6b) {
4277 val = (int8_t)insn_get(s, OT_BYTE);
4278 gen_op_movl_T1_im(val);
4280 gen_op_mov_TN_reg(ot, 1, reg);
4283 #ifdef TARGET_X86_64
4284 if (ot == OT_QUAD) {
4285 tcg_gen_helper_1_2(helper_imulq_T0_T1, cpu_T[0], cpu_T[0], cpu_T[1]);
4288 if (ot == OT_LONG) {
4289 #ifdef TARGET_X86_64
4290 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4291 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4292 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4293 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4294 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4295 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4299 t0 = tcg_temp_new(TCG_TYPE_I64);
4300 t1 = tcg_temp_new(TCG_TYPE_I64);
4301 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4302 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4303 tcg_gen_mul_i64(t0, t0, t1);
4304 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4305 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4306 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4307 tcg_gen_shri_i64(t0, t0, 32);
4308 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4309 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4313 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4314 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4315 /* XXX: use 32 bit mul which could be faster */
4316 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4317 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4318 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4319 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4321 gen_op_mov_reg_T0(ot, reg);
4322 s->cc_op = CC_OP_MULB + ot;
4325 case 0x1c1: /* xadd Ev, Gv */
4329 ot = dflag + OT_WORD;
4330 modrm = ldub_code(s->pc++);
4331 reg = ((modrm >> 3) & 7) | rex_r;
4332 mod = (modrm >> 6) & 3;
4334 rm = (modrm & 7) | REX_B(s);
4335 gen_op_mov_TN_reg(ot, 0, reg);
4336 gen_op_mov_TN_reg(ot, 1, rm);
4337 gen_op_addl_T0_T1();
4338 gen_op_mov_reg_T1(ot, reg);
4339 gen_op_mov_reg_T0(ot, rm);
4341 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4342 gen_op_mov_TN_reg(ot, 0, reg);
4343 gen_op_ld_T1_A0(ot + s->mem_index);
4344 gen_op_addl_T0_T1();
4345 gen_op_st_T0_A0(ot + s->mem_index);
4346 gen_op_mov_reg_T1(ot, reg);
4348 gen_op_update2_cc();
4349 s->cc_op = CC_OP_ADDB + ot;
4352 case 0x1b1: /* cmpxchg Ev, Gv */
4359 ot = dflag + OT_WORD;
4360 modrm = ldub_code(s->pc++);
4361 reg = ((modrm >> 3) & 7) | rex_r;
4362 mod = (modrm >> 6) & 3;
4363 gen_op_mov_TN_reg(ot, 1, reg);
4365 rm = (modrm & 7) | REX_B(s);
4366 gen_op_mov_TN_reg(ot, 0, rm);
4368 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4369 gen_op_ld_T0_A0(ot + s->mem_index);
4370 rm = 0; /* avoid warning */
4372 label1 = gen_new_label();
4373 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_EAX]));
4374 tcg_gen_sub_tl(cpu_T3, cpu_T3, cpu_T[0]);
4375 gen_extu(ot, cpu_T3);
4376 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
4378 label2 = gen_new_label();
4379 gen_op_mov_reg_T0(ot, R_EAX);
4381 gen_set_label(label1);
4382 gen_op_mov_reg_T1(ot, rm);
4383 gen_set_label(label2);
4385 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
4386 gen_op_mov_reg_T0(ot, R_EAX);
4387 gen_set_label(label1);
4389 gen_op_st_T1_A0(ot + s->mem_index);
4391 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4392 tcg_gen_mov_tl(cpu_cc_dst, cpu_T3);
4393 s->cc_op = CC_OP_SUBB + ot;
4396 case 0x1c7: /* cmpxchg8b */
4397 modrm = ldub_code(s->pc++);
4398 mod = (modrm >> 6) & 3;
4399 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4401 #ifdef TARGET_X86_64
4403 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4405 gen_jmp_im(pc_start - s->cs_base);
4406 if (s->cc_op != CC_OP_DYNAMIC)
4407 gen_op_set_cc_op(s->cc_op);
4408 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4409 tcg_gen_helper_0_1(helper_cmpxchg16b, cpu_A0);
4413 if (!(s->cpuid_features & CPUID_CX8))
4415 gen_jmp_im(pc_start - s->cs_base);
4416 if (s->cc_op != CC_OP_DYNAMIC)
4417 gen_op_set_cc_op(s->cc_op);
4418 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4419 tcg_gen_helper_0_1(helper_cmpxchg8b, cpu_A0);
4421 s->cc_op = CC_OP_EFLAGS;
4424 /**************************/
4426 case 0x50 ... 0x57: /* push */
4427 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4430 case 0x58 ... 0x5f: /* pop */
4432 ot = dflag ? OT_QUAD : OT_WORD;
4434 ot = dflag + OT_WORD;
4437 /* NOTE: order is important for pop %sp */
4439 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4441 case 0x60: /* pusha */
4446 case 0x61: /* popa */
4451 case 0x68: /* push Iv */
4454 ot = dflag ? OT_QUAD : OT_WORD;
4456 ot = dflag + OT_WORD;
4459 val = insn_get(s, ot);
4461 val = (int8_t)insn_get(s, OT_BYTE);
4462 gen_op_movl_T0_im(val);
4465 case 0x8f: /* pop Ev */
4467 ot = dflag ? OT_QUAD : OT_WORD;
4469 ot = dflag + OT_WORD;
4471 modrm = ldub_code(s->pc++);
4472 mod = (modrm >> 6) & 3;
4475 /* NOTE: order is important for pop %sp */
4477 rm = (modrm & 7) | REX_B(s);
4478 gen_op_mov_reg_T0(ot, rm);
4480 /* NOTE: order is important too for MMU exceptions */
4481 s->popl_esp_hack = 1 << ot;
4482 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4483 s->popl_esp_hack = 0;
4487 case 0xc8: /* enter */
4490 val = lduw_code(s->pc);
4492 level = ldub_code(s->pc++);
4493 gen_enter(s, val, level);
4496 case 0xc9: /* leave */
4497 /* XXX: exception not precise (ESP is updated before potential exception) */
4499 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4500 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4501 } else if (s->ss32) {
4502 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4503 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4505 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4506 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4510 ot = dflag ? OT_QUAD : OT_WORD;
4512 ot = dflag + OT_WORD;
4514 gen_op_mov_reg_T0(ot, R_EBP);
4517 case 0x06: /* push es */
4518 case 0x0e: /* push cs */
4519 case 0x16: /* push ss */
4520 case 0x1e: /* push ds */
4523 gen_op_movl_T0_seg(b >> 3);
4526 case 0x1a0: /* push fs */
4527 case 0x1a8: /* push gs */
4528 gen_op_movl_T0_seg((b >> 3) & 7);
4531 case 0x07: /* pop es */
4532 case 0x17: /* pop ss */
4533 case 0x1f: /* pop ds */
4538 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4541 /* if reg == SS, inhibit interrupts/trace. */
4542 /* If several instructions disable interrupts, only the
4544 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4545 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4549 gen_jmp_im(s->pc - s->cs_base);
4553 case 0x1a1: /* pop fs */
4554 case 0x1a9: /* pop gs */
4556 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
4559 gen_jmp_im(s->pc - s->cs_base);
4564 /**************************/
4567 case 0x89: /* mov Gv, Ev */
4571 ot = dflag + OT_WORD;
4572 modrm = ldub_code(s->pc++);
4573 reg = ((modrm >> 3) & 7) | rex_r;
4575 /* generate a generic store */
4576 gen_ldst_modrm(s, modrm, ot, reg, 1);
4579 case 0xc7: /* mov Ev, Iv */
4583 ot = dflag + OT_WORD;
4584 modrm = ldub_code(s->pc++);
4585 mod = (modrm >> 6) & 3;
4587 s->rip_offset = insn_const_size(ot);
4588 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4590 val = insn_get(s, ot);
4591 gen_op_movl_T0_im(val);
4593 gen_op_st_T0_A0(ot + s->mem_index);
4595 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
4598 case 0x8b: /* mov Ev, Gv */
4602 ot = OT_WORD + dflag;
4603 modrm = ldub_code(s->pc++);
4604 reg = ((modrm >> 3) & 7) | rex_r;
4606 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4607 gen_op_mov_reg_T0(ot, reg);
4609 case 0x8e: /* mov seg, Gv */
4610 modrm = ldub_code(s->pc++);
4611 reg = (modrm >> 3) & 7;
4612 if (reg >= 6 || reg == R_CS)
4614 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4615 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4617 /* if reg == SS, inhibit interrupts/trace */
4618 /* If several instructions disable interrupts, only the
4620 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4621 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4625 gen_jmp_im(s->pc - s->cs_base);
4629 case 0x8c: /* mov Gv, seg */
4630 modrm = ldub_code(s->pc++);
4631 reg = (modrm >> 3) & 7;
4632 mod = (modrm >> 6) & 3;
4635 gen_op_movl_T0_seg(reg);
4637 ot = OT_WORD + dflag;
4640 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4643 case 0x1b6: /* movzbS Gv, Eb */
4644 case 0x1b7: /* movzwS Gv, Eb */
4645 case 0x1be: /* movsbS Gv, Eb */
4646 case 0x1bf: /* movswS Gv, Eb */
4649 /* d_ot is the size of destination */
4650 d_ot = dflag + OT_WORD;
4651 /* ot is the size of source */
4652 ot = (b & 1) + OT_BYTE;
4653 modrm = ldub_code(s->pc++);
4654 reg = ((modrm >> 3) & 7) | rex_r;
4655 mod = (modrm >> 6) & 3;
4656 rm = (modrm & 7) | REX_B(s);
4659 gen_op_mov_TN_reg(ot, 0, rm);
4660 switch(ot | (b & 8)) {
4662 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4665 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4668 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4672 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4675 gen_op_mov_reg_T0(d_ot, reg);
4677 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4679 gen_op_lds_T0_A0(ot + s->mem_index);
4681 gen_op_ldu_T0_A0(ot + s->mem_index);
4683 gen_op_mov_reg_T0(d_ot, reg);
4688 case 0x8d: /* lea */
4689 ot = dflag + OT_WORD;
4690 modrm = ldub_code(s->pc++);
4691 mod = (modrm >> 6) & 3;
4694 reg = ((modrm >> 3) & 7) | rex_r;
4695 /* we must ensure that no segment is added */
4699 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4701 gen_op_mov_reg_A0(ot - OT_WORD, reg);
4704 case 0xa0: /* mov EAX, Ov */
4706 case 0xa2: /* mov Ov, EAX */
4709 target_ulong offset_addr;
4714 ot = dflag + OT_WORD;
4715 #ifdef TARGET_X86_64
4716 if (s->aflag == 2) {
4717 offset_addr = ldq_code(s->pc);
4719 gen_op_movq_A0_im(offset_addr);
4724 offset_addr = insn_get(s, OT_LONG);
4726 offset_addr = insn_get(s, OT_WORD);
4728 gen_op_movl_A0_im(offset_addr);
4730 gen_add_A0_ds_seg(s);
4732 gen_op_ld_T0_A0(ot + s->mem_index);
4733 gen_op_mov_reg_T0(ot, R_EAX);
4735 gen_op_mov_TN_reg(ot, 0, R_EAX);
4736 gen_op_st_T0_A0(ot + s->mem_index);
4740 case 0xd7: /* xlat */
4741 #ifdef TARGET_X86_64
4742 if (s->aflag == 2) {
4743 gen_op_movq_A0_reg(R_EBX);
4744 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4745 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4746 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4750 gen_op_movl_A0_reg(R_EBX);
4751 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4752 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4753 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4755 gen_op_andl_A0_ffff();
4757 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
4759 gen_add_A0_ds_seg(s);
4760 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
4761 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
4763 case 0xb0 ... 0xb7: /* mov R, Ib */
4764 val = insn_get(s, OT_BYTE);
4765 gen_op_movl_T0_im(val);
4766 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
4768 case 0xb8 ... 0xbf: /* mov R, Iv */
4769 #ifdef TARGET_X86_64
4773 tmp = ldq_code(s->pc);
4775 reg = (b & 7) | REX_B(s);
4776 gen_movtl_T0_im(tmp);
4777 gen_op_mov_reg_T0(OT_QUAD, reg);
4781 ot = dflag ? OT_LONG : OT_WORD;
4782 val = insn_get(s, ot);
4783 reg = (b & 7) | REX_B(s);
4784 gen_op_movl_T0_im(val);
4785 gen_op_mov_reg_T0(ot, reg);
4789 case 0x91 ... 0x97: /* xchg R, EAX */
4790 ot = dflag + OT_WORD;
4791 reg = (b & 7) | REX_B(s);
4795 case 0x87: /* xchg Ev, Gv */
4799 ot = dflag + OT_WORD;
4800 modrm = ldub_code(s->pc++);
4801 reg = ((modrm >> 3) & 7) | rex_r;
4802 mod = (modrm >> 6) & 3;
4804 rm = (modrm & 7) | REX_B(s);
4806 gen_op_mov_TN_reg(ot, 0, reg);
4807 gen_op_mov_TN_reg(ot, 1, rm);
4808 gen_op_mov_reg_T0(ot, rm);
4809 gen_op_mov_reg_T1(ot, reg);
4811 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4812 gen_op_mov_TN_reg(ot, 0, reg);
4813 /* for xchg, lock is implicit */
4814 if (!(prefixes & PREFIX_LOCK))
4815 tcg_gen_helper_0_0(helper_lock);
4816 gen_op_ld_T1_A0(ot + s->mem_index);
4817 gen_op_st_T0_A0(ot + s->mem_index);
4818 if (!(prefixes & PREFIX_LOCK))
4819 tcg_gen_helper_0_0(helper_unlock);
4820 gen_op_mov_reg_T1(ot, reg);
4823 case 0xc4: /* les Gv */
4828 case 0xc5: /* lds Gv */
4833 case 0x1b2: /* lss Gv */
4836 case 0x1b4: /* lfs Gv */
4839 case 0x1b5: /* lgs Gv */
4842 ot = dflag ? OT_LONG : OT_WORD;
4843 modrm = ldub_code(s->pc++);
4844 reg = ((modrm >> 3) & 7) | rex_r;
4845 mod = (modrm >> 6) & 3;
4848 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4849 gen_op_ld_T1_A0(ot + s->mem_index);
4850 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4851 /* load the segment first to handle exceptions properly */
4852 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4853 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4854 /* then put the data */
4855 gen_op_mov_reg_T1(ot, reg);
4857 gen_jmp_im(s->pc - s->cs_base);
4862 /************************/
4873 ot = dflag + OT_WORD;
4875 modrm = ldub_code(s->pc++);
4876 mod = (modrm >> 6) & 3;
4877 op = (modrm >> 3) & 7;
4883 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4886 opreg = (modrm & 7) | REX_B(s);
4891 gen_shift(s, op, ot, opreg, OR_ECX);
4894 shift = ldub_code(s->pc++);
4896 gen_shifti(s, op, ot, opreg, shift);
4911 case 0x1a4: /* shld imm */
4915 case 0x1a5: /* shld cl */
4919 case 0x1ac: /* shrd imm */
4923 case 0x1ad: /* shrd cl */
4927 ot = dflag + OT_WORD;
4928 modrm = ldub_code(s->pc++);
4929 mod = (modrm >> 6) & 3;
4930 rm = (modrm & 7) | REX_B(s);
4931 reg = ((modrm >> 3) & 7) | rex_r;
4933 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4938 gen_op_mov_TN_reg(ot, 1, reg);
4941 val = ldub_code(s->pc++);
4942 tcg_gen_movi_tl(cpu_T3, val);
4944 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
4946 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
4949 /************************/
4952 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
4953 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
4954 /* XXX: what to do if illegal op ? */
4955 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4958 modrm = ldub_code(s->pc++);
4959 mod = (modrm >> 6) & 3;
4961 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
4964 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4966 case 0x00 ... 0x07: /* fxxxs */
4967 case 0x10 ... 0x17: /* fixxxl */
4968 case 0x20 ... 0x27: /* fxxxl */
4969 case 0x30 ... 0x37: /* fixxx */
4976 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4977 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4978 tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
4981 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4982 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4983 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4986 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4987 (s->mem_index >> 2) - 1);
4988 tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
4992 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
4993 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4994 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4998 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5000 /* fcomp needs pop */
5001 tcg_gen_helper_0_0(helper_fpop);
5005 case 0x08: /* flds */
5006 case 0x0a: /* fsts */
5007 case 0x0b: /* fstps */
5008 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5009 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5010 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5015 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5016 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5017 tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
5020 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5021 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5022 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5025 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5026 (s->mem_index >> 2) - 1);
5027 tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
5031 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5032 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5033 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5038 /* XXX: the corresponding CPUID bit must be tested ! */
5041 tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
5042 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5043 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5046 tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
5047 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5048 (s->mem_index >> 2) - 1);
5052 tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
5053 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5054 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5057 tcg_gen_helper_0_0(helper_fpop);
5062 tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
5063 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5064 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5067 tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
5068 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5069 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5072 tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
5073 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5074 (s->mem_index >> 2) - 1);
5078 tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
5079 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5080 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5084 tcg_gen_helper_0_0(helper_fpop);
5088 case 0x0c: /* fldenv mem */
5089 if (s->cc_op != CC_OP_DYNAMIC)
5090 gen_op_set_cc_op(s->cc_op);
5091 gen_jmp_im(pc_start - s->cs_base);
5092 tcg_gen_helper_0_2(helper_fldenv,
5093 cpu_A0, tcg_const_i32(s->dflag));
5095 case 0x0d: /* fldcw mem */
5096 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5097 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5098 tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
5100 case 0x0e: /* fnstenv mem */
5101 if (s->cc_op != CC_OP_DYNAMIC)
5102 gen_op_set_cc_op(s->cc_op);
5103 gen_jmp_im(pc_start - s->cs_base);
5104 tcg_gen_helper_0_2(helper_fstenv,
5105 cpu_A0, tcg_const_i32(s->dflag));
5107 case 0x0f: /* fnstcw mem */
5108 tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
5109 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5110 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5112 case 0x1d: /* fldt mem */
5113 if (s->cc_op != CC_OP_DYNAMIC)
5114 gen_op_set_cc_op(s->cc_op);
5115 gen_jmp_im(pc_start - s->cs_base);
5116 tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0);
5118 case 0x1f: /* fstpt mem */
5119 if (s->cc_op != CC_OP_DYNAMIC)
5120 gen_op_set_cc_op(s->cc_op);
5121 gen_jmp_im(pc_start - s->cs_base);
5122 tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0);
5123 tcg_gen_helper_0_0(helper_fpop);
5125 case 0x2c: /* frstor mem */
5126 if (s->cc_op != CC_OP_DYNAMIC)
5127 gen_op_set_cc_op(s->cc_op);
5128 gen_jmp_im(pc_start - s->cs_base);
5129 tcg_gen_helper_0_2(helper_frstor,
5130 cpu_A0, tcg_const_i32(s->dflag));
5132 case 0x2e: /* fnsave mem */
5133 if (s->cc_op != CC_OP_DYNAMIC)
5134 gen_op_set_cc_op(s->cc_op);
5135 gen_jmp_im(pc_start - s->cs_base);
5136 tcg_gen_helper_0_2(helper_fsave,
5137 cpu_A0, tcg_const_i32(s->dflag));
5139 case 0x2f: /* fnstsw mem */
5140 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5141 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5142 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5144 case 0x3c: /* fbld */
5145 if (s->cc_op != CC_OP_DYNAMIC)
5146 gen_op_set_cc_op(s->cc_op);
5147 gen_jmp_im(pc_start - s->cs_base);
5148 tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0);
5150 case 0x3e: /* fbstp */
5151 if (s->cc_op != CC_OP_DYNAMIC)
5152 gen_op_set_cc_op(s->cc_op);
5153 gen_jmp_im(pc_start - s->cs_base);
5154 tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0);
5155 tcg_gen_helper_0_0(helper_fpop);
5157 case 0x3d: /* fildll */
5158 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5159 (s->mem_index >> 2) - 1);
5160 tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
5162 case 0x3f: /* fistpll */
5163 tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
5164 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5165 (s->mem_index >> 2) - 1);
5166 tcg_gen_helper_0_0(helper_fpop);
5172 /* register float ops */
5176 case 0x08: /* fld sti */
5177 tcg_gen_helper_0_0(helper_fpush);
5178 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
5180 case 0x09: /* fxchg sti */
5181 case 0x29: /* fxchg4 sti, undocumented op */
5182 case 0x39: /* fxchg7 sti, undocumented op */
5183 tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
5185 case 0x0a: /* grp d9/2 */
5188 /* check exceptions (FreeBSD FPU probe) */
5189 if (s->cc_op != CC_OP_DYNAMIC)
5190 gen_op_set_cc_op(s->cc_op);
5191 gen_jmp_im(pc_start - s->cs_base);
5192 tcg_gen_helper_0_0(helper_fwait);
5198 case 0x0c: /* grp d9/4 */
5201 tcg_gen_helper_0_0(helper_fchs_ST0);
5204 tcg_gen_helper_0_0(helper_fabs_ST0);
5207 tcg_gen_helper_0_0(helper_fldz_FT0);
5208 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5211 tcg_gen_helper_0_0(helper_fxam_ST0);
5217 case 0x0d: /* grp d9/5 */
5221 tcg_gen_helper_0_0(helper_fpush);
5222 tcg_gen_helper_0_0(helper_fld1_ST0);
5225 tcg_gen_helper_0_0(helper_fpush);
5226 tcg_gen_helper_0_0(helper_fldl2t_ST0);
5229 tcg_gen_helper_0_0(helper_fpush);
5230 tcg_gen_helper_0_0(helper_fldl2e_ST0);
5233 tcg_gen_helper_0_0(helper_fpush);
5234 tcg_gen_helper_0_0(helper_fldpi_ST0);
5237 tcg_gen_helper_0_0(helper_fpush);
5238 tcg_gen_helper_0_0(helper_fldlg2_ST0);
5241 tcg_gen_helper_0_0(helper_fpush);
5242 tcg_gen_helper_0_0(helper_fldln2_ST0);
5245 tcg_gen_helper_0_0(helper_fpush);
5246 tcg_gen_helper_0_0(helper_fldz_ST0);
5253 case 0x0e: /* grp d9/6 */
5256 tcg_gen_helper_0_0(helper_f2xm1);
5259 tcg_gen_helper_0_0(helper_fyl2x);
5262 tcg_gen_helper_0_0(helper_fptan);
5264 case 3: /* fpatan */
5265 tcg_gen_helper_0_0(helper_fpatan);
5267 case 4: /* fxtract */
5268 tcg_gen_helper_0_0(helper_fxtract);
5270 case 5: /* fprem1 */
5271 tcg_gen_helper_0_0(helper_fprem1);
5273 case 6: /* fdecstp */
5274 tcg_gen_helper_0_0(helper_fdecstp);
5277 case 7: /* fincstp */
5278 tcg_gen_helper_0_0(helper_fincstp);
5282 case 0x0f: /* grp d9/7 */
5285 tcg_gen_helper_0_0(helper_fprem);
5287 case 1: /* fyl2xp1 */
5288 tcg_gen_helper_0_0(helper_fyl2xp1);
5291 tcg_gen_helper_0_0(helper_fsqrt);
5293 case 3: /* fsincos */
5294 tcg_gen_helper_0_0(helper_fsincos);
5296 case 5: /* fscale */
5297 tcg_gen_helper_0_0(helper_fscale);
5299 case 4: /* frndint */
5300 tcg_gen_helper_0_0(helper_frndint);
5303 tcg_gen_helper_0_0(helper_fsin);
5307 tcg_gen_helper_0_0(helper_fcos);
5311 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5312 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5313 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5319 tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
5321 tcg_gen_helper_0_0(helper_fpop);
5323 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5324 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5328 case 0x02: /* fcom */
5329 case 0x22: /* fcom2, undocumented op */
5330 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5331 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5333 case 0x03: /* fcomp */
5334 case 0x23: /* fcomp3, undocumented op */
5335 case 0x32: /* fcomp5, undocumented op */
5336 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5337 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5338 tcg_gen_helper_0_0(helper_fpop);
5340 case 0x15: /* da/5 */
5342 case 1: /* fucompp */
5343 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5344 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5345 tcg_gen_helper_0_0(helper_fpop);
5346 tcg_gen_helper_0_0(helper_fpop);
5354 case 0: /* feni (287 only, just do nop here) */
5356 case 1: /* fdisi (287 only, just do nop here) */
5359 tcg_gen_helper_0_0(helper_fclex);
5361 case 3: /* fninit */
5362 tcg_gen_helper_0_0(helper_fninit);
5364 case 4: /* fsetpm (287 only, just do nop here) */
5370 case 0x1d: /* fucomi */
5371 if (s->cc_op != CC_OP_DYNAMIC)
5372 gen_op_set_cc_op(s->cc_op);
5373 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5374 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5375 s->cc_op = CC_OP_EFLAGS;
5377 case 0x1e: /* fcomi */
5378 if (s->cc_op != CC_OP_DYNAMIC)
5379 gen_op_set_cc_op(s->cc_op);
5380 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5381 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5382 s->cc_op = CC_OP_EFLAGS;
5384 case 0x28: /* ffree sti */
5385 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5387 case 0x2a: /* fst sti */
5388 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5390 case 0x2b: /* fstp sti */
5391 case 0x0b: /* fstp1 sti, undocumented op */
5392 case 0x3a: /* fstp8 sti, undocumented op */
5393 case 0x3b: /* fstp9 sti, undocumented op */
5394 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5395 tcg_gen_helper_0_0(helper_fpop);
5397 case 0x2c: /* fucom st(i) */
5398 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5399 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5401 case 0x2d: /* fucomp st(i) */
5402 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5403 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5404 tcg_gen_helper_0_0(helper_fpop);
5406 case 0x33: /* de/3 */
5408 case 1: /* fcompp */
5409 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5410 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5411 tcg_gen_helper_0_0(helper_fpop);
5412 tcg_gen_helper_0_0(helper_fpop);
5418 case 0x38: /* ffreep sti, undocumented op */
5419 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5420 tcg_gen_helper_0_0(helper_fpop);
5422 case 0x3c: /* df/4 */
5425 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5426 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5427 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5433 case 0x3d: /* fucomip */
5434 if (s->cc_op != CC_OP_DYNAMIC)
5435 gen_op_set_cc_op(s->cc_op);
5436 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5437 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5438 tcg_gen_helper_0_0(helper_fpop);
5439 s->cc_op = CC_OP_EFLAGS;
5441 case 0x3e: /* fcomip */
5442 if (s->cc_op != CC_OP_DYNAMIC)
5443 gen_op_set_cc_op(s->cc_op);
5444 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5445 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5446 tcg_gen_helper_0_0(helper_fpop);
5447 s->cc_op = CC_OP_EFLAGS;
5449 case 0x10 ... 0x13: /* fcmovxx */
5453 const static uint8_t fcmov_cc[8] = {
5459 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
5461 l1 = gen_new_label();
5462 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
5463 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));
5472 /************************/
5475 case 0xa4: /* movsS */
5480 ot = dflag + OT_WORD;
5482 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5483 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5489 case 0xaa: /* stosS */
5494 ot = dflag + OT_WORD;
5496 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5497 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5502 case 0xac: /* lodsS */
5507 ot = dflag + OT_WORD;
5508 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5509 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5514 case 0xae: /* scasS */
5519 ot = dflag + OT_WORD;
5520 if (prefixes & PREFIX_REPNZ) {
5521 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5522 } else if (prefixes & PREFIX_REPZ) {
5523 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5526 s->cc_op = CC_OP_SUBB + ot;
5530 case 0xa6: /* cmpsS */
5535 ot = dflag + OT_WORD;
5536 if (prefixes & PREFIX_REPNZ) {
5537 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5538 } else if (prefixes & PREFIX_REPZ) {
5539 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5542 s->cc_op = CC_OP_SUBB + ot;
5545 case 0x6c: /* insS */
5550 ot = dflag ? OT_LONG : OT_WORD;
5551 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5552 gen_op_andl_T0_ffff();
5553 gen_check_io(s, ot, pc_start - s->cs_base,
5554 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
5555 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5556 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5561 case 0x6e: /* outsS */
5566 ot = dflag ? OT_LONG : OT_WORD;
5567 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5568 gen_op_andl_T0_ffff();
5569 gen_check_io(s, ot, pc_start - s->cs_base,
5570 svm_is_rep(prefixes) | 4);
5571 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5572 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5578 /************************/
5586 ot = dflag ? OT_LONG : OT_WORD;
5587 val = ldub_code(s->pc++);
5588 gen_op_movl_T0_im(val);
5589 gen_check_io(s, ot, pc_start - s->cs_base,
5590 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5591 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5592 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5593 gen_op_mov_reg_T1(ot, R_EAX);
5600 ot = dflag ? OT_LONG : OT_WORD;
5601 val = ldub_code(s->pc++);
5602 gen_op_movl_T0_im(val);
5603 gen_check_io(s, ot, pc_start - s->cs_base,
5604 svm_is_rep(prefixes));
5605 gen_op_mov_TN_reg(ot, 1, R_EAX);
5607 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5608 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5609 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5610 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5617 ot = dflag ? OT_LONG : OT_WORD;
5618 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5619 gen_op_andl_T0_ffff();
5620 gen_check_io(s, ot, pc_start - s->cs_base,
5621 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5622 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5623 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5624 gen_op_mov_reg_T1(ot, R_EAX);
5631 ot = dflag ? OT_LONG : OT_WORD;
5632 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5633 gen_op_andl_T0_ffff();
5634 gen_check_io(s, ot, pc_start - s->cs_base,
5635 svm_is_rep(prefixes));
5636 gen_op_mov_TN_reg(ot, 1, R_EAX);
5638 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5639 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5640 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5641 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5644 /************************/
5646 case 0xc2: /* ret im */
5647 val = ldsw_code(s->pc);
5650 if (CODE64(s) && s->dflag)
5652 gen_stack_update(s, val + (2 << s->dflag));
5654 gen_op_andl_T0_ffff();
5658 case 0xc3: /* ret */
5662 gen_op_andl_T0_ffff();
5666 case 0xca: /* lret im */
5667 val = ldsw_code(s->pc);
5670 if (s->pe && !s->vm86) {
5671 if (s->cc_op != CC_OP_DYNAMIC)
5672 gen_op_set_cc_op(s->cc_op);
5673 gen_jmp_im(pc_start - s->cs_base);
5674 tcg_gen_helper_0_2(helper_lret_protected,
5675 tcg_const_i32(s->dflag),
5676 tcg_const_i32(val));
5680 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5682 gen_op_andl_T0_ffff();
5683 /* NOTE: keeping EIP updated is not a problem in case of
5687 gen_op_addl_A0_im(2 << s->dflag);
5688 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5689 gen_op_movl_seg_T0_vm(R_CS);
5690 /* add stack offset */
5691 gen_stack_update(s, val + (4 << s->dflag));
5695 case 0xcb: /* lret */
5698 case 0xcf: /* iret */
5699 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET))
5703 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5704 s->cc_op = CC_OP_EFLAGS;
5705 } else if (s->vm86) {
5707 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5709 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5710 s->cc_op = CC_OP_EFLAGS;
5713 if (s->cc_op != CC_OP_DYNAMIC)
5714 gen_op_set_cc_op(s->cc_op);
5715 gen_jmp_im(pc_start - s->cs_base);
5716 tcg_gen_helper_0_2(helper_iret_protected,
5717 tcg_const_i32(s->dflag),
5718 tcg_const_i32(s->pc - s->cs_base));
5719 s->cc_op = CC_OP_EFLAGS;
5723 case 0xe8: /* call im */
5726 tval = (int32_t)insn_get(s, OT_LONG);
5728 tval = (int16_t)insn_get(s, OT_WORD);
5729 next_eip = s->pc - s->cs_base;
5733 gen_movtl_T0_im(next_eip);
5738 case 0x9a: /* lcall im */
5740 unsigned int selector, offset;
5744 ot = dflag ? OT_LONG : OT_WORD;
5745 offset = insn_get(s, ot);
5746 selector = insn_get(s, OT_WORD);
5748 gen_op_movl_T0_im(selector);
5749 gen_op_movl_T1_imu(offset);
5752 case 0xe9: /* jmp im */
5754 tval = (int32_t)insn_get(s, OT_LONG);
5756 tval = (int16_t)insn_get(s, OT_WORD);
5757 tval += s->pc - s->cs_base;
5762 case 0xea: /* ljmp im */
5764 unsigned int selector, offset;
5768 ot = dflag ? OT_LONG : OT_WORD;
5769 offset = insn_get(s, ot);
5770 selector = insn_get(s, OT_WORD);
5772 gen_op_movl_T0_im(selector);
5773 gen_op_movl_T1_imu(offset);
5776 case 0xeb: /* jmp Jb */
5777 tval = (int8_t)insn_get(s, OT_BYTE);
5778 tval += s->pc - s->cs_base;
5783 case 0x70 ... 0x7f: /* jcc Jb */
5784 tval = (int8_t)insn_get(s, OT_BYTE);
5786 case 0x180 ... 0x18f: /* jcc Jv */
5788 tval = (int32_t)insn_get(s, OT_LONG);
5790 tval = (int16_t)insn_get(s, OT_WORD);
5793 next_eip = s->pc - s->cs_base;
5797 gen_jcc(s, b, tval, next_eip);
5800 case 0x190 ... 0x19f: /* setcc Gv */
5801 modrm = ldub_code(s->pc++);
5803 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
5805 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5808 ot = dflag + OT_WORD;
5809 modrm = ldub_code(s->pc++);
5810 reg = ((modrm >> 3) & 7) | rex_r;
5811 mod = (modrm >> 6) & 3;
5813 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5814 gen_op_ld_T1_A0(ot + s->mem_index);
5816 rm = (modrm & 7) | REX_B(s);
5817 gen_op_mov_TN_reg(ot, 1, rm);
5819 if (s->cc_op != CC_OP_DYNAMIC)
5820 gen_op_set_cc_op(s->cc_op);
5821 #ifdef TARGET_X86_64
5822 if (ot == OT_LONG) {
5823 /* XXX: specific Intel behaviour ? */
5824 l1 = gen_new_label();
5825 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5826 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
5828 tcg_gen_movi_tl(cpu_tmp0, 0);
5829 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
5833 l1 = gen_new_label();
5834 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5835 gen_op_mov_reg_T1(ot, reg);
5841 /************************/
5843 case 0x9c: /* pushf */
5844 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF))
5846 if (s->vm86 && s->iopl != 3) {
5847 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5849 if (s->cc_op != CC_OP_DYNAMIC)
5850 gen_op_set_cc_op(s->cc_op);
5851 tcg_gen_helper_1_0(helper_read_eflags, cpu_T[0]);
5855 case 0x9d: /* popf */
5856 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF))
5858 if (s->vm86 && s->iopl != 3) {
5859 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5864 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5865 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
5867 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5868 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
5871 if (s->cpl <= s->iopl) {
5873 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5874 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
5876 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5877 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
5881 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5882 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
5884 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5885 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
5890 s->cc_op = CC_OP_EFLAGS;
5891 /* abort translation because TF flag may change */
5892 gen_jmp_im(s->pc - s->cs_base);
5896 case 0x9e: /* sahf */
5897 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
5899 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
5900 if (s->cc_op != CC_OP_DYNAMIC)
5901 gen_op_set_cc_op(s->cc_op);
5902 gen_compute_eflags(cpu_cc_src);
5903 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
5904 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
5905 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
5906 s->cc_op = CC_OP_EFLAGS;
5908 case 0x9f: /* lahf */
5909 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
5911 if (s->cc_op != CC_OP_DYNAMIC)
5912 gen_op_set_cc_op(s->cc_op);
5913 gen_compute_eflags(cpu_T[0]);
5914 /* Note: gen_compute_eflags() only gives the condition codes */
5915 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
5916 gen_op_mov_reg_T0(OT_BYTE, R_AH);
5918 case 0xf5: /* cmc */
5919 if (s->cc_op != CC_OP_DYNAMIC)
5920 gen_op_set_cc_op(s->cc_op);
5921 gen_compute_eflags(cpu_cc_src);
5922 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
5923 s->cc_op = CC_OP_EFLAGS;
5925 case 0xf8: /* clc */
5926 if (s->cc_op != CC_OP_DYNAMIC)
5927 gen_op_set_cc_op(s->cc_op);
5928 gen_compute_eflags(cpu_cc_src);
5929 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
5930 s->cc_op = CC_OP_EFLAGS;
5932 case 0xf9: /* stc */
5933 if (s->cc_op != CC_OP_DYNAMIC)
5934 gen_op_set_cc_op(s->cc_op);
5935 gen_compute_eflags(cpu_cc_src);
5936 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
5937 s->cc_op = CC_OP_EFLAGS;
5939 case 0xfc: /* cld */
5940 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
5941 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5943 case 0xfd: /* std */
5944 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
5945 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5948 /************************/
5949 /* bit operations */
5950 case 0x1ba: /* bt/bts/btr/btc Gv, im */
5951 ot = dflag + OT_WORD;
5952 modrm = ldub_code(s->pc++);
5953 op = (modrm >> 3) & 7;
5954 mod = (modrm >> 6) & 3;
5955 rm = (modrm & 7) | REX_B(s);
5958 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5959 gen_op_ld_T0_A0(ot + s->mem_index);
5961 gen_op_mov_TN_reg(ot, 0, rm);
5964 val = ldub_code(s->pc++);
5965 gen_op_movl_T1_im(val);
5970 case 0x1a3: /* bt Gv, Ev */
5973 case 0x1ab: /* bts */
5976 case 0x1b3: /* btr */
5979 case 0x1bb: /* btc */
5982 ot = dflag + OT_WORD;
5983 modrm = ldub_code(s->pc++);
5984 reg = ((modrm >> 3) & 7) | rex_r;
5985 mod = (modrm >> 6) & 3;
5986 rm = (modrm & 7) | REX_B(s);
5987 gen_op_mov_TN_reg(OT_LONG, 1, reg);
5989 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5990 /* specific case: we need to add a displacement */
5991 gen_exts(ot, cpu_T[1]);
5992 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
5993 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
5994 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
5995 gen_op_ld_T0_A0(ot + s->mem_index);
5997 gen_op_mov_TN_reg(ot, 0, rm);
6000 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6003 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6004 tcg_gen_movi_tl(cpu_cc_dst, 0);
6007 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6008 tcg_gen_movi_tl(cpu_tmp0, 1);
6009 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6010 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6013 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6014 tcg_gen_movi_tl(cpu_tmp0, 1);
6015 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6016 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6017 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6021 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6022 tcg_gen_movi_tl(cpu_tmp0, 1);
6023 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6024 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6027 s->cc_op = CC_OP_SARB + ot;
6030 gen_op_st_T0_A0(ot + s->mem_index);
6032 gen_op_mov_reg_T0(ot, rm);
6033 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6034 tcg_gen_movi_tl(cpu_cc_dst, 0);
6037 case 0x1bc: /* bsf */
6038 case 0x1bd: /* bsr */
6041 ot = dflag + OT_WORD;
6042 modrm = ldub_code(s->pc++);
6043 reg = ((modrm >> 3) & 7) | rex_r;
6044 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6045 gen_extu(ot, cpu_T[0]);
6046 label1 = gen_new_label();
6047 tcg_gen_movi_tl(cpu_cc_dst, 0);
6048 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), label1);
6050 tcg_gen_helper_1_1(helper_bsr, cpu_T[0], cpu_T[0]);
6052 tcg_gen_helper_1_1(helper_bsf, cpu_T[0], cpu_T[0]);
6054 gen_op_mov_reg_T0(ot, reg);
6055 tcg_gen_movi_tl(cpu_cc_dst, 1);
6056 gen_set_label(label1);
6057 tcg_gen_discard_tl(cpu_cc_src);
6058 s->cc_op = CC_OP_LOGICB + ot;
6061 /************************/
6063 case 0x27: /* daa */
6066 if (s->cc_op != CC_OP_DYNAMIC)
6067 gen_op_set_cc_op(s->cc_op);
6068 tcg_gen_helper_0_0(helper_daa);
6069 s->cc_op = CC_OP_EFLAGS;
6071 case 0x2f: /* das */
6074 if (s->cc_op != CC_OP_DYNAMIC)
6075 gen_op_set_cc_op(s->cc_op);
6076 tcg_gen_helper_0_0(helper_das);
6077 s->cc_op = CC_OP_EFLAGS;
6079 case 0x37: /* aaa */
6082 if (s->cc_op != CC_OP_DYNAMIC)
6083 gen_op_set_cc_op(s->cc_op);
6084 tcg_gen_helper_0_0(helper_aaa);
6085 s->cc_op = CC_OP_EFLAGS;
6087 case 0x3f: /* aas */
6090 if (s->cc_op != CC_OP_DYNAMIC)
6091 gen_op_set_cc_op(s->cc_op);
6092 tcg_gen_helper_0_0(helper_aas);
6093 s->cc_op = CC_OP_EFLAGS;
6095 case 0xd4: /* aam */
6098 val = ldub_code(s->pc++);
6100 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6102 tcg_gen_helper_0_1(helper_aam, tcg_const_i32(val));
6103 s->cc_op = CC_OP_LOGICB;
6106 case 0xd5: /* aad */
6109 val = ldub_code(s->pc++);
6110 tcg_gen_helper_0_1(helper_aad, tcg_const_i32(val));
6111 s->cc_op = CC_OP_LOGICB;
6113 /************************/
6115 case 0x90: /* nop */
6116 /* XXX: xchg + rex handling */
6117 /* XXX: correct lock test for all insn */
6118 if (prefixes & PREFIX_LOCK)
6120 if (prefixes & PREFIX_REPZ) {
6121 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6124 case 0x9b: /* fwait */
6125 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6126 (HF_MP_MASK | HF_TS_MASK)) {
6127 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6129 if (s->cc_op != CC_OP_DYNAMIC)
6130 gen_op_set_cc_op(s->cc_op);
6131 gen_jmp_im(pc_start - s->cs_base);
6132 tcg_gen_helper_0_0(helper_fwait);
6135 case 0xcc: /* int3 */
6136 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
6138 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6140 case 0xcd: /* int N */
6141 val = ldub_code(s->pc++);
6142 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
6144 if (s->vm86 && s->iopl != 3) {
6145 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6147 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6150 case 0xce: /* into */
6153 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
6155 if (s->cc_op != CC_OP_DYNAMIC)
6156 gen_op_set_cc_op(s->cc_op);
6157 gen_jmp_im(pc_start - s->cs_base);
6158 tcg_gen_helper_0_1(helper_into, tcg_const_i32(s->pc - pc_start));
6160 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6161 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP))
6164 gen_debug(s, pc_start - s->cs_base);
6167 tb_flush(cpu_single_env);
6168 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6171 case 0xfa: /* cli */
6173 if (s->cpl <= s->iopl) {
6174 tcg_gen_helper_0_0(helper_cli);
6176 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6180 tcg_gen_helper_0_0(helper_cli);
6182 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6186 case 0xfb: /* sti */
6188 if (s->cpl <= s->iopl) {
6190 tcg_gen_helper_0_0(helper_sti);
6191 /* interruptions are enabled only the first insn after sti */
6192 /* If several instructions disable interrupts, only the
6194 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6195 tcg_gen_helper_0_0(helper_set_inhibit_irq);
6196 /* give a chance to handle pending irqs */
6197 gen_jmp_im(s->pc - s->cs_base);
6200 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6206 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6210 case 0x62: /* bound */
6213 ot = dflag ? OT_LONG : OT_WORD;
6214 modrm = ldub_code(s->pc++);
6215 reg = (modrm >> 3) & 7;
6216 mod = (modrm >> 6) & 3;
6219 gen_op_mov_TN_reg(ot, 0, reg);
6220 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6221 gen_jmp_im(pc_start - s->cs_base);
6222 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6224 tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
6226 tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
6228 case 0x1c8 ... 0x1cf: /* bswap reg */
6229 reg = (b & 7) | REX_B(s);
6230 #ifdef TARGET_X86_64
6232 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6233 tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
6234 gen_op_mov_reg_T0(OT_QUAD, reg);
6238 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6240 tmp0 = tcg_temp_new(TCG_TYPE_I32);
6241 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6242 tcg_gen_bswap_i32(tmp0, tmp0);
6243 tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6244 gen_op_mov_reg_T0(OT_LONG, reg);
6248 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6249 tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
6250 gen_op_mov_reg_T0(OT_LONG, reg);
6254 case 0xd6: /* salc */
6257 if (s->cc_op != CC_OP_DYNAMIC)
6258 gen_op_set_cc_op(s->cc_op);
6259 gen_compute_eflags_c(cpu_T[0]);
6260 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6261 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6263 case 0xe0: /* loopnz */
6264 case 0xe1: /* loopz */
6265 case 0xe2: /* loop */
6266 case 0xe3: /* jecxz */
6270 tval = (int8_t)insn_get(s, OT_BYTE);
6271 next_eip = s->pc - s->cs_base;
6276 l1 = gen_new_label();
6277 l2 = gen_new_label();
6278 l3 = gen_new_label();
6281 case 0: /* loopnz */
6283 if (s->cc_op != CC_OP_DYNAMIC)
6284 gen_op_set_cc_op(s->cc_op);
6285 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6286 gen_op_jz_ecx(s->aflag, l3);
6287 gen_compute_eflags(cpu_tmp0);
6288 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6290 tcg_gen_brcond_tl(TCG_COND_EQ,
6291 cpu_tmp0, tcg_const_tl(0), l1);
6293 tcg_gen_brcond_tl(TCG_COND_NE,
6294 cpu_tmp0, tcg_const_tl(0), l1);
6298 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6299 gen_op_jnz_ecx(s->aflag, l1);
6303 gen_op_jz_ecx(s->aflag, l1);
6308 gen_jmp_im(next_eip);
6317 case 0x130: /* wrmsr */
6318 case 0x132: /* rdmsr */
6320 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6324 retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 0);
6325 tcg_gen_helper_0_0(helper_rdmsr);
6327 retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 1);
6328 tcg_gen_helper_0_0(helper_wrmsr);
6334 case 0x131: /* rdtsc */
6335 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RDTSC))
6337 gen_jmp_im(pc_start - s->cs_base);
6338 tcg_gen_helper_0_0(helper_rdtsc);
6340 case 0x133: /* rdpmc */
6341 gen_jmp_im(pc_start - s->cs_base);
6342 tcg_gen_helper_0_0(helper_rdpmc);
6344 case 0x134: /* sysenter */
6348 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6350 if (s->cc_op != CC_OP_DYNAMIC) {
6351 gen_op_set_cc_op(s->cc_op);
6352 s->cc_op = CC_OP_DYNAMIC;
6354 gen_jmp_im(pc_start - s->cs_base);
6355 tcg_gen_helper_0_0(helper_sysenter);
6359 case 0x135: /* sysexit */
6363 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6365 if (s->cc_op != CC_OP_DYNAMIC) {
6366 gen_op_set_cc_op(s->cc_op);
6367 s->cc_op = CC_OP_DYNAMIC;
6369 gen_jmp_im(pc_start - s->cs_base);
6370 tcg_gen_helper_0_0(helper_sysexit);
6374 #ifdef TARGET_X86_64
6375 case 0x105: /* syscall */
6376 /* XXX: is it usable in real mode ? */
6377 if (s->cc_op != CC_OP_DYNAMIC) {
6378 gen_op_set_cc_op(s->cc_op);
6379 s->cc_op = CC_OP_DYNAMIC;
6381 gen_jmp_im(pc_start - s->cs_base);
6382 tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
6385 case 0x107: /* sysret */
6387 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6389 if (s->cc_op != CC_OP_DYNAMIC) {
6390 gen_op_set_cc_op(s->cc_op);
6391 s->cc_op = CC_OP_DYNAMIC;
6393 gen_jmp_im(pc_start - s->cs_base);
6394 tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
6395 /* condition codes are modified only in long mode */
6397 s->cc_op = CC_OP_EFLAGS;
6402 case 0x1a2: /* cpuid */
6403 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CPUID))
6405 tcg_gen_helper_0_0(helper_cpuid);
6407 case 0xf4: /* hlt */
6409 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6411 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_HLT))
6413 if (s->cc_op != CC_OP_DYNAMIC)
6414 gen_op_set_cc_op(s->cc_op);
6415 gen_jmp_im(s->pc - s->cs_base);
6416 tcg_gen_helper_0_0(helper_hlt);
6421 modrm = ldub_code(s->pc++);
6422 mod = (modrm >> 6) & 3;
6423 op = (modrm >> 3) & 7;
6426 if (!s->pe || s->vm86)
6428 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ))
6430 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6434 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6437 if (!s->pe || s->vm86)
6440 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6442 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE))
6444 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6445 gen_jmp_im(pc_start - s->cs_base);
6446 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6447 tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
6451 if (!s->pe || s->vm86)
6453 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ))
6455 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6459 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6462 if (!s->pe || s->vm86)
6465 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6467 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE))
6469 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6470 gen_jmp_im(pc_start - s->cs_base);
6471 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6472 tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
6477 if (!s->pe || s->vm86)
6479 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6480 if (s->cc_op != CC_OP_DYNAMIC)
6481 gen_op_set_cc_op(s->cc_op);
6483 tcg_gen_helper_0_1(helper_verr, cpu_T[0]);
6485 tcg_gen_helper_0_1(helper_verw, cpu_T[0]);
6486 s->cc_op = CC_OP_EFLAGS;
6493 modrm = ldub_code(s->pc++);
6494 mod = (modrm >> 6) & 3;
6495 op = (modrm >> 3) & 7;
6501 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ))
6503 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6504 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6505 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6506 gen_add_A0_im(s, 2);
6507 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
6509 gen_op_andl_T0_im(0xffffff);
6510 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6515 case 0: /* monitor */
6516 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6519 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MONITOR))
6521 gen_jmp_im(pc_start - s->cs_base);
6522 #ifdef TARGET_X86_64
6523 if (s->aflag == 2) {
6524 gen_op_movq_A0_reg(R_EAX);
6528 gen_op_movl_A0_reg(R_EAX);
6530 gen_op_andl_A0_ffff();
6532 gen_add_A0_ds_seg(s);
6533 tcg_gen_helper_0_1(helper_monitor, cpu_A0);
6536 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6539 if (s->cc_op != CC_OP_DYNAMIC) {
6540 gen_op_set_cc_op(s->cc_op);
6541 s->cc_op = CC_OP_DYNAMIC;
6543 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MWAIT))
6545 gen_jmp_im(s->pc - s->cs_base);
6546 tcg_gen_helper_0_0(helper_mwait);
6553 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ))
6555 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6556 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
6557 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6558 gen_add_A0_im(s, 2);
6559 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
6561 gen_op_andl_T0_im(0xffffff);
6562 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6570 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMRUN))
6572 if (s->cc_op != CC_OP_DYNAMIC)
6573 gen_op_set_cc_op(s->cc_op);
6574 gen_jmp_im(s->pc - s->cs_base);
6575 tcg_gen_helper_0_0(helper_vmrun);
6576 s->cc_op = CC_OP_EFLAGS;
6579 case 1: /* VMMCALL */
6580 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMMCALL))
6582 /* FIXME: cause #UD if hflags & SVM */
6583 tcg_gen_helper_0_0(helper_vmmcall);
6585 case 2: /* VMLOAD */
6586 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMLOAD))
6588 tcg_gen_helper_0_0(helper_vmload);
6590 case 3: /* VMSAVE */
6591 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMSAVE))
6593 tcg_gen_helper_0_0(helper_vmsave);
6596 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_STGI))
6598 tcg_gen_helper_0_0(helper_stgi);
6601 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CLGI))
6603 tcg_gen_helper_0_0(helper_clgi);
6605 case 6: /* SKINIT */
6606 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT))
6608 tcg_gen_helper_0_0(helper_skinit);
6610 case 7: /* INVLPGA */
6611 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPGA))
6613 tcg_gen_helper_0_0(helper_invlpga);
6618 } else if (s->cpl != 0) {
6619 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6621 if (gen_svm_check_intercept(s, pc_start,
6622 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE))
6624 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6625 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
6626 gen_add_A0_im(s, 2);
6627 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6629 gen_op_andl_T0_im(0xffffff);
6631 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
6632 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
6634 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
6635 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
6640 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0))
6642 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
6643 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
6647 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6649 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0))
6651 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6652 tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
6653 gen_jmp_im(s->pc - s->cs_base);
6657 case 7: /* invlpg */
6659 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6662 #ifdef TARGET_X86_64
6663 if (CODE64(s) && rm == 0) {
6665 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6666 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
6667 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6668 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
6675 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPG))
6677 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6678 tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
6679 gen_jmp_im(s->pc - s->cs_base);
6688 case 0x108: /* invd */
6689 case 0x109: /* wbinvd */
6691 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6693 if (gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD))
6698 case 0x63: /* arpl or movslS (x86_64) */
6699 #ifdef TARGET_X86_64
6702 /* d_ot is the size of destination */
6703 d_ot = dflag + OT_WORD;
6705 modrm = ldub_code(s->pc++);
6706 reg = ((modrm >> 3) & 7) | rex_r;
6707 mod = (modrm >> 6) & 3;
6708 rm = (modrm & 7) | REX_B(s);
6711 gen_op_mov_TN_reg(OT_LONG, 0, rm);
6713 if (d_ot == OT_QUAD)
6714 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
6715 gen_op_mov_reg_T0(d_ot, reg);
6717 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6718 if (d_ot == OT_QUAD) {
6719 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
6721 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6723 gen_op_mov_reg_T0(d_ot, reg);
6729 if (!s->pe || s->vm86)
6732 modrm = ldub_code(s->pc++);
6733 reg = (modrm >> 3) & 7;
6734 mod = (modrm >> 6) & 3;
6737 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6738 gen_op_ld_T0_A0(ot + s->mem_index);
6740 gen_op_mov_TN_reg(ot, 0, rm);
6742 gen_op_mov_TN_reg(ot, 1, reg);
6743 tcg_gen_andi_tl(cpu_tmp0, cpu_T[0], 3);
6744 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 3);
6745 tcg_gen_movi_tl(cpu_T3, 0);
6746 label1 = gen_new_label();
6747 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, cpu_T[1], label1);
6748 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~3);
6749 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
6750 tcg_gen_movi_tl(cpu_T3, CC_Z);
6751 gen_set_label(label1);
6753 gen_op_st_T0_A0(ot + s->mem_index);
6755 gen_op_mov_reg_T0(ot, rm);
6757 if (s->cc_op != CC_OP_DYNAMIC)
6758 gen_op_set_cc_op(s->cc_op);
6759 gen_compute_eflags(cpu_cc_src);
6760 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
6761 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T3);
6762 s->cc_op = CC_OP_EFLAGS;
6765 case 0x102: /* lar */
6766 case 0x103: /* lsl */
6769 if (!s->pe || s->vm86)
6771 ot = dflag ? OT_LONG : OT_WORD;
6772 modrm = ldub_code(s->pc++);
6773 reg = ((modrm >> 3) & 7) | rex_r;
6774 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6775 if (s->cc_op != CC_OP_DYNAMIC)
6776 gen_op_set_cc_op(s->cc_op);
6778 tcg_gen_helper_1_1(helper_lar, cpu_T[0], cpu_T[0]);
6780 tcg_gen_helper_1_1(helper_lsl, cpu_T[0], cpu_T[0]);
6781 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
6782 label1 = gen_new_label();
6783 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), label1);
6784 gen_op_mov_reg_T0(ot, reg);
6785 gen_set_label(label1);
6786 s->cc_op = CC_OP_EFLAGS;
6790 modrm = ldub_code(s->pc++);
6791 mod = (modrm >> 6) & 3;
6792 op = (modrm >> 3) & 7;
6794 case 0: /* prefetchnta */
6795 case 1: /* prefetchnt0 */
6796 case 2: /* prefetchnt0 */
6797 case 3: /* prefetchnt0 */
6800 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6801 /* nothing more to do */
6803 default: /* nop (multi byte) */
6804 gen_nop_modrm(s, modrm);
6808 case 0x119 ... 0x11f: /* nop (multi byte) */
6809 modrm = ldub_code(s->pc++);
6810 gen_nop_modrm(s, modrm);
6812 case 0x120: /* mov reg, crN */
6813 case 0x122: /* mov crN, reg */
6815 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6817 modrm = ldub_code(s->pc++);
6818 if ((modrm & 0xc0) != 0xc0)
6820 rm = (modrm & 7) | REX_B(s);
6821 reg = ((modrm >> 3) & 7) | rex_r;
6833 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0 + reg);
6834 gen_op_mov_TN_reg(ot, 0, rm);
6835 tcg_gen_helper_0_2(helper_movl_crN_T0,
6836 tcg_const_i32(reg), cpu_T[0]);
6837 gen_jmp_im(s->pc - s->cs_base);
6840 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0 + reg);
6841 #if !defined(CONFIG_USER_ONLY)
6843 tcg_gen_helper_1_0(helper_movtl_T0_cr8, cpu_T[0]);
6846 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[reg]));
6847 gen_op_mov_reg_T0(ot, rm);
6855 case 0x121: /* mov reg, drN */
6856 case 0x123: /* mov drN, reg */
6858 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6860 modrm = ldub_code(s->pc++);
6861 if ((modrm & 0xc0) != 0xc0)
6863 rm = (modrm & 7) | REX_B(s);
6864 reg = ((modrm >> 3) & 7) | rex_r;
6869 /* XXX: do it dynamically with CR4.DE bit */
6870 if (reg == 4 || reg == 5 || reg >= 8)
6873 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
6874 gen_op_mov_TN_reg(ot, 0, rm);
6875 tcg_gen_helper_0_2(helper_movl_drN_T0,
6876 tcg_const_i32(reg), cpu_T[0]);
6877 gen_jmp_im(s->pc - s->cs_base);
6880 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
6881 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
6882 gen_op_mov_reg_T0(ot, rm);
6886 case 0x106: /* clts */
6888 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6890 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
6891 tcg_gen_helper_0_0(helper_clts);
6892 /* abort block because static cpu state changed */
6893 gen_jmp_im(s->pc - s->cs_base);
6897 /* MMX/3DNow!/SSE/SSE2/SSE3 support */
6898 case 0x1c3: /* MOVNTI reg, mem */
6899 if (!(s->cpuid_features & CPUID_SSE2))
6901 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
6902 modrm = ldub_code(s->pc++);
6903 mod = (modrm >> 6) & 3;
6906 reg = ((modrm >> 3) & 7) | rex_r;
6907 /* generate a generic store */
6908 gen_ldst_modrm(s, modrm, ot, reg, 1);
6911 modrm = ldub_code(s->pc++);
6912 mod = (modrm >> 6) & 3;
6913 op = (modrm >> 3) & 7;
6915 case 0: /* fxsave */
6916 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
6917 (s->flags & HF_EM_MASK))
6919 if (s->flags & HF_TS_MASK) {
6920 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6923 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6924 if (s->cc_op != CC_OP_DYNAMIC)
6925 gen_op_set_cc_op(s->cc_op);
6926 gen_jmp_im(pc_start - s->cs_base);
6927 tcg_gen_helper_0_2(helper_fxsave,
6928 cpu_A0, tcg_const_i32((s->dflag == 2)));
6930 case 1: /* fxrstor */
6931 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
6932 (s->flags & HF_EM_MASK))
6934 if (s->flags & HF_TS_MASK) {
6935 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6938 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6939 if (s->cc_op != CC_OP_DYNAMIC)
6940 gen_op_set_cc_op(s->cc_op);
6941 gen_jmp_im(pc_start - s->cs_base);
6942 tcg_gen_helper_0_2(helper_fxrstor,
6943 cpu_A0, tcg_const_i32((s->dflag == 2)));
6945 case 2: /* ldmxcsr */
6946 case 3: /* stmxcsr */
6947 if (s->flags & HF_TS_MASK) {
6948 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6951 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
6954 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6956 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6957 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
6959 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
6960 gen_op_st_T0_A0(OT_LONG + s->mem_index);
6963 case 5: /* lfence */
6964 case 6: /* mfence */
6965 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
6968 case 7: /* sfence / clflush */
6969 if ((modrm & 0xc7) == 0xc0) {
6971 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
6972 if (!(s->cpuid_features & CPUID_SSE))
6976 if (!(s->cpuid_features & CPUID_CLFLUSH))
6978 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6985 case 0x10d: /* 3DNow! prefetch(w) */
6986 modrm = ldub_code(s->pc++);
6987 mod = (modrm >> 6) & 3;
6990 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6991 /* ignore for now */
6993 case 0x1aa: /* rsm */
6994 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM))
6996 if (!(s->flags & HF_SMM_MASK))
6998 if (s->cc_op != CC_OP_DYNAMIC) {
6999 gen_op_set_cc_op(s->cc_op);
7000 s->cc_op = CC_OP_DYNAMIC;
7002 gen_jmp_im(s->pc - s->cs_base);
7003 tcg_gen_helper_0_0(helper_rsm);
7006 case 0x10e ... 0x10f:
7007 /* 3DNow! instructions, ignore prefixes */
7008 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7009 case 0x110 ... 0x117:
7010 case 0x128 ... 0x12f:
7011 case 0x150 ... 0x177:
7012 case 0x17c ... 0x17f:
7014 case 0x1c4 ... 0x1c6:
7015 case 0x1d0 ... 0x1fe:
7016 gen_sse(s, b, pc_start, rex_r);
7021 /* lock generation */
7022 if (s->prefix & PREFIX_LOCK)
7023 tcg_gen_helper_0_0(helper_unlock);
7026 if (s->prefix & PREFIX_LOCK)
7027 tcg_gen_helper_0_0(helper_unlock);
7028 /* XXX: ensure that no lock was generated */
7029 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7033 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
7038 tcg_gen_helper_0_1(helper_divl_EAX_T0, cpu_T[0]);
7044 void optimize_flags_init(void)
7046 #if TCG_TARGET_REG_BITS == 32
7047 assert(sizeof(CCTable) == (1 << 3));
7049 assert(sizeof(CCTable) == (1 << 4));
7051 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
7053 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
7054 #if TARGET_LONG_BITS > HOST_LONG_BITS
7055 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
7056 TCG_AREG0, offsetof(CPUState, t0), "T0");
7057 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
7058 TCG_AREG0, offsetof(CPUState, t1), "T1");
7059 cpu_A0 = tcg_global_mem_new(TCG_TYPE_TL,
7060 TCG_AREG0, offsetof(CPUState, t2), "A0");
7062 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
7063 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
7064 cpu_A0 = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "A0");
7066 cpu_T3 = tcg_global_mem_new(TCG_TYPE_TL,
7067 TCG_AREG0, offsetof(CPUState, t3), "T3");
7068 #if defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS)
7069 /* XXX: must be suppressed once there are less fixed registers */
7070 cpu_tmp1_i64 = tcg_global_reg2_new_hack(TCG_TYPE_I64, TCG_AREG1, TCG_AREG2, "tmp1");
7072 cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,
7073 TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
7074 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
7075 TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
7076 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
7077 TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
7080 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7081 basic block 'tb'. If search_pc is TRUE, also generate PC
7082 information for each intermediate instruction. */
7083 static inline int gen_intermediate_code_internal(CPUState *env,
7084 TranslationBlock *tb,
7087 DisasContext dc1, *dc = &dc1;
7088 target_ulong pc_ptr;
7089 uint16_t *gen_opc_end;
7092 target_ulong pc_start;
7093 target_ulong cs_base;
7095 /* generate intermediate code */
7097 cs_base = tb->cs_base;
7099 cflags = tb->cflags;
7101 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7102 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7103 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7104 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7106 dc->vm86 = (flags >> VM_SHIFT) & 1;
7107 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7108 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7109 dc->tf = (flags >> TF_SHIFT) & 1;
7110 dc->singlestep_enabled = env->singlestep_enabled;
7111 dc->cc_op = CC_OP_DYNAMIC;
7112 dc->cs_base = cs_base;
7114 dc->popl_esp_hack = 0;
7115 /* select memory access functions */
7117 if (flags & HF_SOFTMMU_MASK) {
7119 dc->mem_index = 2 * 4;
7121 dc->mem_index = 1 * 4;
7123 dc->cpuid_features = env->cpuid_features;
7124 dc->cpuid_ext_features = env->cpuid_ext_features;
7125 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7126 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7127 #ifdef TARGET_X86_64
7128 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7129 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7132 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7133 (flags & HF_INHIBIT_IRQ_MASK)
7134 #ifndef CONFIG_SOFTMMU
7135 || (flags & HF_SOFTMMU_MASK)
7139 /* check addseg logic */
7140 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7141 printf("ERROR addseg\n");
7144 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
7145 #if !(defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS))
7146 cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);
7148 cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);
7149 cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);
7150 cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);
7151 cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL);
7152 cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL);
7153 cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR);
7154 cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR);
7156 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7158 dc->is_jmp = DISAS_NEXT;
7163 if (env->nb_breakpoints > 0) {
7164 for(j = 0; j < env->nb_breakpoints; j++) {
7165 if (env->breakpoints[j] == pc_ptr) {
7166 gen_debug(dc, pc_ptr - dc->cs_base);
7172 j = gen_opc_ptr - gen_opc_buf;
7176 gen_opc_instr_start[lj++] = 0;
7178 gen_opc_pc[lj] = pc_ptr;
7179 gen_opc_cc_op[lj] = dc->cc_op;
7180 gen_opc_instr_start[lj] = 1;
7182 pc_ptr = disas_insn(dc, pc_ptr);
7183 /* stop translation if indicated */
7186 /* if single step mode, we generate only one instruction and
7187 generate an exception */
7188 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7189 the flag and abort the translation to give the irqs a
7190 change to be happen */
7191 if (dc->tf || dc->singlestep_enabled ||
7192 (flags & HF_INHIBIT_IRQ_MASK) ||
7193 (cflags & CF_SINGLE_INSN)) {
7194 gen_jmp_im(pc_ptr - dc->cs_base);
7198 /* if too long translation, stop generation too */
7199 if (gen_opc_ptr >= gen_opc_end ||
7200 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
7201 gen_jmp_im(pc_ptr - dc->cs_base);
7206 *gen_opc_ptr = INDEX_op_end;
7207 /* we don't forget to fill the last values */
7209 j = gen_opc_ptr - gen_opc_buf;
7212 gen_opc_instr_start[lj++] = 0;
7216 if (loglevel & CPU_LOG_TB_CPU) {
7217 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
7219 if (loglevel & CPU_LOG_TB_IN_ASM) {
7221 fprintf(logfile, "----------------\n");
7222 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7223 #ifdef TARGET_X86_64
7228 disas_flags = !dc->code32;
7229 target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
7230 fprintf(logfile, "\n");
7231 if (loglevel & CPU_LOG_TB_OP_OPT) {
7232 fprintf(logfile, "OP before opt:\n");
7233 tcg_dump_ops(&tcg_ctx, logfile);
7234 fprintf(logfile, "\n");
7240 tb->size = pc_ptr - pc_start;
7244 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7246 return gen_intermediate_code_internal(env, tb, 0);
7249 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7251 return gen_intermediate_code_internal(env, tb, 1);
7254 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7255 unsigned long searched_pc, int pc_pos, void *puc)
7259 if (loglevel & CPU_LOG_TB_OP) {
7261 fprintf(logfile, "RESTORE:\n");
7262 for(i = 0;i <= pc_pos; i++) {
7263 if (gen_opc_instr_start[i]) {
7264 fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7267 fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7268 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7269 (uint32_t)tb->cs_base);
7272 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7273 cc_op = gen_opc_cc_op[pc_pos];
7274 if (cc_op != CC_OP_DYNAMIC)