4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(x...) x
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48 #define BUGGY_64(x) NULL
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(x...)
58 //#define MACRO_TEST 1
60 /* global register indexes */
61 static TCGv cpu_env, cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
63 static TCGv cpu_T[2], cpu_T3;
64 /* local register indexes (only used inside old micro ops) */
65 static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
66 static TCGv cpu_tmp5, cpu_tmp6;
68 #include "gen-icount.h"
71 static int x86_64_hregs;
74 typedef struct DisasContext {
75 /* current insn context */
76 int override; /* -1 if no override */
79 target_ulong pc; /* pc = eip + cs_base */
80 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base; /* base of CS segment */
84 int pe; /* protected mode */
85 int code32; /* 32 bit code segment */
87 int lma; /* long mode active */
88 int code64; /* 64 bit code segment */
91 int ss32; /* 32 bit stack segment */
92 int cc_op; /* current CC operation */
93 int addseg; /* non zero if either DS/ES/SS have a non zero base */
94 int f_st; /* currently unused */
95 int vm86; /* vm86 mode */
98 int tf; /* TF cpu flag */
99 int singlestep_enabled; /* "hardware" single step enabled */
100 int jmp_opt; /* use direct block chaining for direct jumps */
101 int mem_index; /* select memory access functions */
102 uint64_t flags; /* all execution flags */
103 struct TranslationBlock *tb;
104 int popl_esp_hack; /* for correct popl with esp base handling */
105 int rip_offset; /* only used in x86_64, but left for simplicity */
107 int cpuid_ext_features;
108 int cpuid_ext2_features;
109 int cpuid_ext3_features;
112 static void gen_eob(DisasContext *s);
113 static void gen_jmp(DisasContext *s, target_ulong eip);
114 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
116 /* i386 arith/logic operations */
136 OP_SHL1, /* undocumented */
160 /* I386 int registers */
161 OR_EAX, /* MUST be even numbered */
170 OR_TMP0 = 16, /* temporary operand register */
172 OR_A0, /* temporary register used when doing address evaluation */
175 static inline void gen_op_movl_T0_0(void)
177 tcg_gen_movi_tl(cpu_T[0], 0);
180 static inline void gen_op_movl_T0_im(int32_t val)
182 tcg_gen_movi_tl(cpu_T[0], val);
185 static inline void gen_op_movl_T0_imu(uint32_t val)
187 tcg_gen_movi_tl(cpu_T[0], val);
190 static inline void gen_op_movl_T1_im(int32_t val)
192 tcg_gen_movi_tl(cpu_T[1], val);
195 static inline void gen_op_movl_T1_imu(uint32_t val)
197 tcg_gen_movi_tl(cpu_T[1], val);
200 static inline void gen_op_movl_A0_im(uint32_t val)
202 tcg_gen_movi_tl(cpu_A0, val);
206 static inline void gen_op_movq_A0_im(int64_t val)
208 tcg_gen_movi_tl(cpu_A0, val);
212 static inline void gen_movtl_T0_im(target_ulong val)
214 tcg_gen_movi_tl(cpu_T[0], val);
217 static inline void gen_movtl_T1_im(target_ulong val)
219 tcg_gen_movi_tl(cpu_T[1], val);
222 static inline void gen_op_andl_T0_ffff(void)
224 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
227 static inline void gen_op_andl_T0_im(uint32_t val)
229 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
232 static inline void gen_op_movl_T0_T1(void)
234 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
237 static inline void gen_op_andl_A0_ffff(void)
239 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
244 #define NB_OP_SIZES 4
246 #else /* !TARGET_X86_64 */
248 #define NB_OP_SIZES 3
250 #endif /* !TARGET_X86_64 */
252 #if defined(WORDS_BIGENDIAN)
253 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
254 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
255 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
256 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
257 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
259 #define REG_B_OFFSET 0
260 #define REG_H_OFFSET 1
261 #define REG_W_OFFSET 0
262 #define REG_L_OFFSET 0
263 #define REG_LH_OFFSET 4
266 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
270 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
271 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
273 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
277 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
281 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
282 /* high part of register set to zero */
283 tcg_gen_movi_tl(cpu_tmp0, 0);
284 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
288 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
293 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
299 static inline void gen_op_mov_reg_T0(int ot, int reg)
301 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
304 static inline void gen_op_mov_reg_T1(int ot, int reg)
306 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
309 static inline void gen_op_mov_reg_A0(int size, int reg)
313 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
317 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
318 /* high part of register set to zero */
319 tcg_gen_movi_tl(cpu_tmp0, 0);
320 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
324 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
329 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
335 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
339 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
342 tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
347 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
352 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
354 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
357 static inline void gen_op_movl_A0_reg(int reg)
359 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
362 static inline void gen_op_addl_A0_im(int32_t val)
364 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
366 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
371 static inline void gen_op_addq_A0_im(int64_t val)
373 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
377 static void gen_add_A0_im(DisasContext *s, int val)
381 gen_op_addq_A0_im(val);
384 gen_op_addl_A0_im(val);
387 static inline void gen_op_addl_T0_T1(void)
389 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
392 static inline void gen_op_jmp_T0(void)
394 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
397 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
401 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
402 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
403 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
406 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
407 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
409 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
411 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
415 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
416 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
417 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
423 static inline void gen_op_add_reg_T0(int size, int reg)
427 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
428 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
429 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
432 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
433 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
435 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
437 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
441 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
442 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
443 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
449 static inline void gen_op_set_cc_op(int32_t val)
451 tcg_gen_movi_i32(cpu_cc_op, val);
454 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
456 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
458 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
459 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
461 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
465 static inline void gen_op_movl_A0_seg(int reg)
467 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
470 static inline void gen_op_addl_A0_seg(int reg)
472 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
473 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
475 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
480 static inline void gen_op_movq_A0_seg(int reg)
482 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
485 static inline void gen_op_addq_A0_seg(int reg)
487 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
488 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
491 static inline void gen_op_movq_A0_reg(int reg)
493 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
496 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
498 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
500 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
501 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
505 static inline void gen_op_lds_T0_A0(int idx)
507 int mem_index = (idx >> 2) - 1;
510 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
513 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
517 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
522 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
524 int mem_index = (idx >> 2) - 1;
527 tcg_gen_qemu_ld8u(t0, a0, mem_index);
530 tcg_gen_qemu_ld16u(t0, a0, mem_index);
533 tcg_gen_qemu_ld32u(t0, a0, mem_index);
537 tcg_gen_qemu_ld64(t0, a0, mem_index);
542 /* XXX: always use ldu or lds */
543 static inline void gen_op_ld_T0_A0(int idx)
545 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
548 static inline void gen_op_ldu_T0_A0(int idx)
550 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
553 static inline void gen_op_ld_T1_A0(int idx)
555 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
558 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
560 int mem_index = (idx >> 2) - 1;
563 tcg_gen_qemu_st8(t0, a0, mem_index);
566 tcg_gen_qemu_st16(t0, a0, mem_index);
569 tcg_gen_qemu_st32(t0, a0, mem_index);
573 tcg_gen_qemu_st64(t0, a0, mem_index);
578 static inline void gen_op_st_T0_A0(int idx)
580 gen_op_st_v(idx, cpu_T[0], cpu_A0);
583 static inline void gen_op_st_T1_A0(int idx)
585 gen_op_st_v(idx, cpu_T[1], cpu_A0);
588 static inline void gen_jmp_im(target_ulong pc)
590 tcg_gen_movi_tl(cpu_tmp0, pc);
591 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
594 static inline void gen_string_movl_A0_ESI(DisasContext *s)
598 override = s->override;
602 gen_op_movq_A0_seg(override);
603 gen_op_addq_A0_reg_sN(0, R_ESI);
605 gen_op_movq_A0_reg(R_ESI);
611 if (s->addseg && override < 0)
614 gen_op_movl_A0_seg(override);
615 gen_op_addl_A0_reg_sN(0, R_ESI);
617 gen_op_movl_A0_reg(R_ESI);
620 /* 16 address, always override */
623 gen_op_movl_A0_reg(R_ESI);
624 gen_op_andl_A0_ffff();
625 gen_op_addl_A0_seg(override);
629 static inline void gen_string_movl_A0_EDI(DisasContext *s)
633 gen_op_movq_A0_reg(R_EDI);
638 gen_op_movl_A0_seg(R_ES);
639 gen_op_addl_A0_reg_sN(0, R_EDI);
641 gen_op_movl_A0_reg(R_EDI);
644 gen_op_movl_A0_reg(R_EDI);
645 gen_op_andl_A0_ffff();
646 gen_op_addl_A0_seg(R_ES);
650 static inline void gen_op_movl_T0_Dshift(int ot)
652 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
653 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
656 static void gen_extu(int ot, TCGv reg)
660 tcg_gen_ext8u_tl(reg, reg);
663 tcg_gen_ext16u_tl(reg, reg);
666 tcg_gen_ext32u_tl(reg, reg);
673 static void gen_exts(int ot, TCGv reg)
677 tcg_gen_ext8s_tl(reg, reg);
680 tcg_gen_ext16s_tl(reg, reg);
683 tcg_gen_ext32s_tl(reg, reg);
690 static inline void gen_op_jnz_ecx(int size, int label1)
692 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
693 gen_extu(size + 1, cpu_tmp0);
694 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
697 static inline void gen_op_jz_ecx(int size, int label1)
699 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
700 gen_extu(size + 1, cpu_tmp0);
701 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
704 static void *helper_in_func[3] = {
710 static void *helper_out_func[3] = {
716 static void *gen_check_io_func[3] = {
722 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
726 target_ulong next_eip;
729 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
730 if (s->cc_op != CC_OP_DYNAMIC)
731 gen_op_set_cc_op(s->cc_op);
734 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
735 tcg_gen_helper_0_1(gen_check_io_func[ot],
738 if(s->flags & HF_SVMI_MASK) {
740 if (s->cc_op != CC_OP_DYNAMIC)
741 gen_op_set_cc_op(s->cc_op);
745 svm_flags |= (1 << (4 + ot));
746 next_eip = s->pc - s->cs_base;
747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
748 tcg_gen_helper_0_3(helper_svm_check_io,
750 tcg_const_i32(svm_flags),
751 tcg_const_i32(next_eip - cur_eip));
755 static inline void gen_movs(DisasContext *s, int ot)
757 gen_string_movl_A0_ESI(s);
758 gen_op_ld_T0_A0(ot + s->mem_index);
759 gen_string_movl_A0_EDI(s);
760 gen_op_st_T0_A0(ot + s->mem_index);
761 gen_op_movl_T0_Dshift(ot);
762 gen_op_add_reg_T0(s->aflag, R_ESI);
763 gen_op_add_reg_T0(s->aflag, R_EDI);
766 static inline void gen_update_cc_op(DisasContext *s)
768 if (s->cc_op != CC_OP_DYNAMIC) {
769 gen_op_set_cc_op(s->cc_op);
770 s->cc_op = CC_OP_DYNAMIC;
774 static void gen_op_update1_cc(void)
776 tcg_gen_discard_tl(cpu_cc_src);
777 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
780 static void gen_op_update2_cc(void)
782 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
783 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
786 static inline void gen_op_cmpl_T0_T1_cc(void)
788 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
789 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
792 static inline void gen_op_testl_T0_T1_cc(void)
794 tcg_gen_discard_tl(cpu_cc_src);
795 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
798 static void gen_op_update_neg_cc(void)
800 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
801 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
804 /* compute eflags.C to reg */
805 static void gen_compute_eflags_c(TCGv reg)
807 #if TCG_TARGET_REG_BITS == 32
808 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
809 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
810 (long)cc_table + offsetof(CCTable, compute_c));
811 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
812 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
813 1, &cpu_tmp2_i32, 0, NULL);
815 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
816 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
817 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
818 (long)cc_table + offsetof(CCTable, compute_c));
819 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
820 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
821 1, &cpu_tmp2_i32, 0, NULL);
823 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
826 /* compute all eflags to cc_src */
827 static void gen_compute_eflags(TCGv reg)
829 #if TCG_TARGET_REG_BITS == 32
830 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
831 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
832 (long)cc_table + offsetof(CCTable, compute_all));
833 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
834 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
835 1, &cpu_tmp2_i32, 0, NULL);
837 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
838 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
839 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
840 (long)cc_table + offsetof(CCTable, compute_all));
841 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
842 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
843 1, &cpu_tmp2_i32, 0, NULL);
845 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
848 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
850 if (s->cc_op != CC_OP_DYNAMIC)
851 gen_op_set_cc_op(s->cc_op);
854 gen_compute_eflags(cpu_T[0]);
855 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
856 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
859 gen_compute_eflags_c(cpu_T[0]);
862 gen_compute_eflags(cpu_T[0]);
863 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
864 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
867 gen_compute_eflags(cpu_tmp0);
868 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
869 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
870 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
873 gen_compute_eflags(cpu_T[0]);
874 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
875 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
878 gen_compute_eflags(cpu_T[0]);
879 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
880 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
883 gen_compute_eflags(cpu_tmp0);
884 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
885 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
886 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
887 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
891 gen_compute_eflags(cpu_tmp0);
892 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
893 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
894 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
895 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
896 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
897 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
902 /* return true if setcc_slow is not needed (WARNING: must be kept in
903 sync with gen_jcc1) */
904 static int is_fast_jcc_case(DisasContext *s, int b)
907 jcc_op = (b >> 1) & 7;
909 /* we optimize the cmp/jcc case */
914 if (jcc_op == JCC_O || jcc_op == JCC_P)
918 /* some jumps are easy to compute */
943 if (jcc_op != JCC_Z && jcc_op != JCC_S)
953 /* generate a conditional jump to label 'l1' according to jump opcode
954 value 'b'. In the fast case, T0 is guaranted not to be used. */
955 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
957 int inv, jcc_op, size, cond;
961 jcc_op = (b >> 1) & 7;
964 /* we optimize the cmp/jcc case */
970 size = cc_op - CC_OP_SUBB;
976 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
980 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
985 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
993 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
999 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
1000 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1004 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
1005 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1008 #ifdef TARGET_X86_64
1010 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1011 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1016 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1023 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1026 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1028 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1032 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1033 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1037 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1038 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1040 #ifdef TARGET_X86_64
1043 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1044 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1051 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1055 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1058 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1060 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1064 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1065 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1069 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1070 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1072 #ifdef TARGET_X86_64
1075 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1076 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1083 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1091 /* some jumps are easy to compute */
1133 size = (cc_op - CC_OP_ADDB) & 3;
1136 size = (cc_op - CC_OP_ADDB) & 3;
1144 gen_setcc_slow_T0(s, jcc_op);
1145 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1151 /* XXX: does not work with gdbstub "ice" single step - not a
1153 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1157 l1 = gen_new_label();
1158 l2 = gen_new_label();
1159 gen_op_jnz_ecx(s->aflag, l1);
1161 gen_jmp_tb(s, next_eip, 1);
1166 static inline void gen_stos(DisasContext *s, int ot)
1168 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1169 gen_string_movl_A0_EDI(s);
1170 gen_op_st_T0_A0(ot + s->mem_index);
1171 gen_op_movl_T0_Dshift(ot);
1172 gen_op_add_reg_T0(s->aflag, R_EDI);
1175 static inline void gen_lods(DisasContext *s, int ot)
1177 gen_string_movl_A0_ESI(s);
1178 gen_op_ld_T0_A0(ot + s->mem_index);
1179 gen_op_mov_reg_T0(ot, R_EAX);
1180 gen_op_movl_T0_Dshift(ot);
1181 gen_op_add_reg_T0(s->aflag, R_ESI);
1184 static inline void gen_scas(DisasContext *s, int ot)
1186 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1187 gen_string_movl_A0_EDI(s);
1188 gen_op_ld_T1_A0(ot + s->mem_index);
1189 gen_op_cmpl_T0_T1_cc();
1190 gen_op_movl_T0_Dshift(ot);
1191 gen_op_add_reg_T0(s->aflag, R_EDI);
1194 static inline void gen_cmps(DisasContext *s, int ot)
1196 gen_string_movl_A0_ESI(s);
1197 gen_op_ld_T0_A0(ot + s->mem_index);
1198 gen_string_movl_A0_EDI(s);
1199 gen_op_ld_T1_A0(ot + s->mem_index);
1200 gen_op_cmpl_T0_T1_cc();
1201 gen_op_movl_T0_Dshift(ot);
1202 gen_op_add_reg_T0(s->aflag, R_ESI);
1203 gen_op_add_reg_T0(s->aflag, R_EDI);
1206 static inline void gen_ins(DisasContext *s, int ot)
1210 gen_string_movl_A0_EDI(s);
1211 /* Note: we must do this dummy write first to be restartable in
1212 case of page fault. */
1214 gen_op_st_T0_A0(ot + s->mem_index);
1215 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1216 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1217 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1218 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
1219 gen_op_st_T0_A0(ot + s->mem_index);
1220 gen_op_movl_T0_Dshift(ot);
1221 gen_op_add_reg_T0(s->aflag, R_EDI);
1226 static inline void gen_outs(DisasContext *s, int ot)
1230 gen_string_movl_A0_ESI(s);
1231 gen_op_ld_T0_A0(ot + s->mem_index);
1233 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1234 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1235 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1236 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1237 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
1239 gen_op_movl_T0_Dshift(ot);
1240 gen_op_add_reg_T0(s->aflag, R_ESI);
1245 /* same method as Valgrind : we generate jumps to current or next
1247 #define GEN_REPZ(op) \
1248 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1249 target_ulong cur_eip, target_ulong next_eip) \
1252 gen_update_cc_op(s); \
1253 l2 = gen_jz_ecx_string(s, next_eip); \
1254 gen_ ## op(s, ot); \
1255 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1256 /* a loop would cause two single step exceptions if ECX = 1 \
1257 before rep string_insn */ \
1259 gen_op_jz_ecx(s->aflag, l2); \
1260 gen_jmp(s, cur_eip); \
1263 #define GEN_REPZ2(op) \
1264 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1265 target_ulong cur_eip, \
1266 target_ulong next_eip, \
1270 gen_update_cc_op(s); \
1271 l2 = gen_jz_ecx_string(s, next_eip); \
1272 gen_ ## op(s, ot); \
1273 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1274 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1275 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1277 gen_op_jz_ecx(s->aflag, l2); \
1278 gen_jmp(s, cur_eip); \
1289 static void *helper_fp_arith_ST0_FT0[8] = {
1290 helper_fadd_ST0_FT0,
1291 helper_fmul_ST0_FT0,
1292 helper_fcom_ST0_FT0,
1293 helper_fcom_ST0_FT0,
1294 helper_fsub_ST0_FT0,
1295 helper_fsubr_ST0_FT0,
1296 helper_fdiv_ST0_FT0,
1297 helper_fdivr_ST0_FT0,
1300 /* NOTE the exception in "r" op ordering */
1301 static void *helper_fp_arith_STN_ST0[8] = {
1302 helper_fadd_STN_ST0,
1303 helper_fmul_STN_ST0,
1306 helper_fsubr_STN_ST0,
1307 helper_fsub_STN_ST0,
1308 helper_fdivr_STN_ST0,
1309 helper_fdiv_STN_ST0,
1312 /* if d == OR_TMP0, it means memory operand (address in A0) */
1313 static void gen_op(DisasContext *s1, int op, int ot, int d)
1316 gen_op_mov_TN_reg(ot, 0, d);
1318 gen_op_ld_T0_A0(ot + s1->mem_index);
1322 if (s1->cc_op != CC_OP_DYNAMIC)
1323 gen_op_set_cc_op(s1->cc_op);
1324 gen_compute_eflags_c(cpu_tmp4);
1325 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1326 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1328 gen_op_mov_reg_T0(ot, d);
1330 gen_op_st_T0_A0(ot + s1->mem_index);
1331 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1332 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1333 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1334 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1335 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1336 s1->cc_op = CC_OP_DYNAMIC;
1339 if (s1->cc_op != CC_OP_DYNAMIC)
1340 gen_op_set_cc_op(s1->cc_op);
1341 gen_compute_eflags_c(cpu_tmp4);
1342 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1343 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1345 gen_op_mov_reg_T0(ot, d);
1347 gen_op_st_T0_A0(ot + s1->mem_index);
1348 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1349 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1350 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1351 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1352 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1353 s1->cc_op = CC_OP_DYNAMIC;
1356 gen_op_addl_T0_T1();
1358 gen_op_mov_reg_T0(ot, d);
1360 gen_op_st_T0_A0(ot + s1->mem_index);
1361 gen_op_update2_cc();
1362 s1->cc_op = CC_OP_ADDB + ot;
1365 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1367 gen_op_mov_reg_T0(ot, d);
1369 gen_op_st_T0_A0(ot + s1->mem_index);
1370 gen_op_update2_cc();
1371 s1->cc_op = CC_OP_SUBB + ot;
1375 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1377 gen_op_mov_reg_T0(ot, d);
1379 gen_op_st_T0_A0(ot + s1->mem_index);
1380 gen_op_update1_cc();
1381 s1->cc_op = CC_OP_LOGICB + ot;
1384 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1386 gen_op_mov_reg_T0(ot, d);
1388 gen_op_st_T0_A0(ot + s1->mem_index);
1389 gen_op_update1_cc();
1390 s1->cc_op = CC_OP_LOGICB + ot;
1393 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1395 gen_op_mov_reg_T0(ot, d);
1397 gen_op_st_T0_A0(ot + s1->mem_index);
1398 gen_op_update1_cc();
1399 s1->cc_op = CC_OP_LOGICB + ot;
1402 gen_op_cmpl_T0_T1_cc();
1403 s1->cc_op = CC_OP_SUBB + ot;
1408 /* if d == OR_TMP0, it means memory operand (address in A0) */
1409 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1412 gen_op_mov_TN_reg(ot, 0, d);
1414 gen_op_ld_T0_A0(ot + s1->mem_index);
1415 if (s1->cc_op != CC_OP_DYNAMIC)
1416 gen_op_set_cc_op(s1->cc_op);
1418 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1419 s1->cc_op = CC_OP_INCB + ot;
1421 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1422 s1->cc_op = CC_OP_DECB + ot;
1425 gen_op_mov_reg_T0(ot, d);
1427 gen_op_st_T0_A0(ot + s1->mem_index);
1428 gen_compute_eflags_c(cpu_cc_src);
1429 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1432 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1433 int is_right, int is_arith)
1446 gen_op_ld_T0_A0(ot + s->mem_index);
1448 gen_op_mov_TN_reg(ot, 0, op1);
1450 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1452 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1456 gen_exts(ot, cpu_T[0]);
1457 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1458 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1460 gen_extu(ot, cpu_T[0]);
1461 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1462 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1465 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1466 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1471 gen_op_st_T0_A0(ot + s->mem_index);
1473 gen_op_mov_reg_T0(ot, op1);
1475 /* update eflags if non zero shift */
1476 if (s->cc_op != CC_OP_DYNAMIC)
1477 gen_op_set_cc_op(s->cc_op);
1479 /* XXX: inefficient */
1480 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1481 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1483 tcg_gen_mov_tl(t0, cpu_T[0]);
1484 tcg_gen_mov_tl(t1, cpu_T3);
1486 shift_label = gen_new_label();
1487 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, shift_label);
1489 tcg_gen_mov_tl(cpu_cc_src, t1);
1490 tcg_gen_mov_tl(cpu_cc_dst, t0);
1492 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1494 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1496 gen_set_label(shift_label);
1497 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1503 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1504 int is_right, int is_arith)
1515 gen_op_ld_T0_A0(ot + s->mem_index);
1517 gen_op_mov_TN_reg(ot, 0, op1);
1523 gen_exts(ot, cpu_T[0]);
1524 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1525 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1527 gen_extu(ot, cpu_T[0]);
1528 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1529 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1532 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1533 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1539 gen_op_st_T0_A0(ot + s->mem_index);
1541 gen_op_mov_reg_T0(ot, op1);
1543 /* update eflags if non zero shift */
1545 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1546 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1548 s->cc_op = CC_OP_SARB + ot;
1550 s->cc_op = CC_OP_SHLB + ot;
1554 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1557 tcg_gen_shli_tl(ret, arg1, arg2);
1559 tcg_gen_shri_tl(ret, arg1, -arg2);
1562 /* XXX: add faster immediate case */
1563 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1567 int label1, label2, data_bits;
1568 TCGv t0, t1, t2, a0;
1570 /* XXX: inefficient, but we must use local temps */
1571 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1572 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1573 t2 = tcg_temp_local_new(TCG_TYPE_TL);
1574 a0 = tcg_temp_local_new(TCG_TYPE_TL);
1582 if (op1 == OR_TMP0) {
1583 tcg_gen_mov_tl(a0, cpu_A0);
1584 gen_op_ld_v(ot + s->mem_index, t0, a0);
1586 gen_op_mov_v_reg(ot, t0, op1);
1589 tcg_gen_mov_tl(t1, cpu_T[1]);
1591 tcg_gen_andi_tl(t1, t1, mask);
1593 /* Must test zero case to avoid using undefined behaviour in TCG
1595 label1 = gen_new_label();
1596 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1599 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1601 tcg_gen_mov_tl(cpu_tmp0, t1);
1604 tcg_gen_mov_tl(t2, t0);
1606 data_bits = 8 << ot;
1607 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1608 fix TCG definition) */
1610 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1611 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1612 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1614 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1615 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1616 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1618 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1620 gen_set_label(label1);
1622 if (op1 == OR_TMP0) {
1623 gen_op_st_v(ot + s->mem_index, t0, a0);
1625 gen_op_mov_reg_v(ot, op1, t0);
1629 if (s->cc_op != CC_OP_DYNAMIC)
1630 gen_op_set_cc_op(s->cc_op);
1632 label2 = gen_new_label();
1633 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1635 gen_compute_eflags(cpu_cc_src);
1636 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1637 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1638 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1639 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1640 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1642 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1644 tcg_gen_andi_tl(t0, t0, CC_C);
1645 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1647 tcg_gen_discard_tl(cpu_cc_dst);
1648 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1650 gen_set_label(label2);
1651 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1659 static void *helper_rotc[8] = {
1663 X86_64_ONLY(helper_rclq),
1667 X86_64_ONLY(helper_rcrq),
1670 /* XXX: add faster immediate = 1 case */
1671 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1676 if (s->cc_op != CC_OP_DYNAMIC)
1677 gen_op_set_cc_op(s->cc_op);
1681 gen_op_ld_T0_A0(ot + s->mem_index);
1683 gen_op_mov_TN_reg(ot, 0, op1);
1685 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
1686 cpu_T[0], cpu_T[0], cpu_T[1]);
1689 gen_op_st_T0_A0(ot + s->mem_index);
1691 gen_op_mov_reg_T0(ot, op1);
1694 label1 = gen_new_label();
1695 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1697 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1698 tcg_gen_discard_tl(cpu_cc_dst);
1699 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1701 gen_set_label(label1);
1702 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1705 /* XXX: add faster immediate case */
1706 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1709 int label1, label2, data_bits;
1711 TCGv t0, t1, t2, a0;
1713 t0 = tcg_temp_local_new(TCG_TYPE_TL);
1714 t1 = tcg_temp_local_new(TCG_TYPE_TL);
1715 t2 = tcg_temp_local_new(TCG_TYPE_TL);
1716 a0 = tcg_temp_local_new(TCG_TYPE_TL);
1724 if (op1 == OR_TMP0) {
1725 tcg_gen_mov_tl(a0, cpu_A0);
1726 gen_op_ld_v(ot + s->mem_index, t0, a0);
1728 gen_op_mov_v_reg(ot, t0, op1);
1731 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1733 tcg_gen_mov_tl(t1, cpu_T[1]);
1734 tcg_gen_mov_tl(t2, cpu_T3);
1736 /* Must test zero case to avoid using undefined behaviour in TCG
1738 label1 = gen_new_label();
1739 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1741 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1742 if (ot == OT_WORD) {
1743 /* Note: we implement the Intel behaviour for shift count > 16 */
1745 tcg_gen_andi_tl(t0, t0, 0xffff);
1746 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1747 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1748 tcg_gen_ext32u_tl(t0, t0);
1750 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1752 /* only needed if count > 16, but a test would complicate */
1753 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1754 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1756 tcg_gen_shr_tl(t0, t0, t2);
1758 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1760 /* XXX: not optimal */
1761 tcg_gen_andi_tl(t0, t0, 0xffff);
1762 tcg_gen_shli_tl(t1, t1, 16);
1763 tcg_gen_or_tl(t1, t1, t0);
1764 tcg_gen_ext32u_tl(t1, t1);
1766 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1767 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1768 tcg_gen_shr_tl(cpu_tmp6, t1, cpu_tmp0);
1769 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1771 tcg_gen_shl_tl(t0, t0, t2);
1772 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2);
1773 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1774 tcg_gen_or_tl(t0, t0, t1);
1777 data_bits = 8 << ot;
1780 tcg_gen_ext32u_tl(t0, t0);
1782 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1784 tcg_gen_shr_tl(t0, t0, t2);
1785 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1786 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1787 tcg_gen_or_tl(t0, t0, t1);
1791 tcg_gen_ext32u_tl(t1, t1);
1793 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1795 tcg_gen_shl_tl(t0, t0, t2);
1796 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2);
1797 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1798 tcg_gen_or_tl(t0, t0, t1);
1801 tcg_gen_mov_tl(t1, cpu_tmp4);
1803 gen_set_label(label1);
1805 if (op1 == OR_TMP0) {
1806 gen_op_st_v(ot + s->mem_index, t0, a0);
1808 gen_op_mov_reg_v(ot, op1, t0);
1812 if (s->cc_op != CC_OP_DYNAMIC)
1813 gen_op_set_cc_op(s->cc_op);
1815 label2 = gen_new_label();
1816 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1818 tcg_gen_mov_tl(cpu_cc_src, t1);
1819 tcg_gen_mov_tl(cpu_cc_dst, t0);
1821 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1823 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1825 gen_set_label(label2);
1826 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1834 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1837 gen_op_mov_TN_reg(ot, 1, s);
1840 gen_rot_rm_T1(s1, ot, d, 0);
1843 gen_rot_rm_T1(s1, ot, d, 1);
1847 gen_shift_rm_T1(s1, ot, d, 0, 0);
1850 gen_shift_rm_T1(s1, ot, d, 1, 0);
1853 gen_shift_rm_T1(s1, ot, d, 1, 1);
1856 gen_rotc_rm_T1(s1, ot, d, 0);
1859 gen_rotc_rm_T1(s1, ot, d, 1);
1864 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1869 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1872 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1875 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1878 /* currently not optimized */
1879 gen_op_movl_T1_im(c);
1880 gen_shift(s1, op, ot, d, OR_TMP1);
1885 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1893 int mod, rm, code, override, must_add_seg;
1895 override = s->override;
1896 must_add_seg = s->addseg;
1899 mod = (modrm >> 6) & 3;
1911 code = ldub_code(s->pc++);
1912 scale = (code >> 6) & 3;
1913 index = ((code >> 3) & 7) | REX_X(s);
1920 if ((base & 7) == 5) {
1922 disp = (int32_t)ldl_code(s->pc);
1924 if (CODE64(s) && !havesib) {
1925 disp += s->pc + s->rip_offset;
1932 disp = (int8_t)ldub_code(s->pc++);
1936 disp = ldl_code(s->pc);
1942 /* for correct popl handling with esp */
1943 if (base == 4 && s->popl_esp_hack)
1944 disp += s->popl_esp_hack;
1945 #ifdef TARGET_X86_64
1946 if (s->aflag == 2) {
1947 gen_op_movq_A0_reg(base);
1949 gen_op_addq_A0_im(disp);
1954 gen_op_movl_A0_reg(base);
1956 gen_op_addl_A0_im(disp);
1959 #ifdef TARGET_X86_64
1960 if (s->aflag == 2) {
1961 gen_op_movq_A0_im(disp);
1965 gen_op_movl_A0_im(disp);
1968 /* XXX: index == 4 is always invalid */
1969 if (havesib && (index != 4 || scale != 0)) {
1970 #ifdef TARGET_X86_64
1971 if (s->aflag == 2) {
1972 gen_op_addq_A0_reg_sN(scale, index);
1976 gen_op_addl_A0_reg_sN(scale, index);
1981 if (base == R_EBP || base == R_ESP)
1986 #ifdef TARGET_X86_64
1987 if (s->aflag == 2) {
1988 gen_op_addq_A0_seg(override);
1992 gen_op_addl_A0_seg(override);
1999 disp = lduw_code(s->pc);
2001 gen_op_movl_A0_im(disp);
2002 rm = 0; /* avoid SS override */
2009 disp = (int8_t)ldub_code(s->pc++);
2013 disp = lduw_code(s->pc);
2019 gen_op_movl_A0_reg(R_EBX);
2020 gen_op_addl_A0_reg_sN(0, R_ESI);
2023 gen_op_movl_A0_reg(R_EBX);
2024 gen_op_addl_A0_reg_sN(0, R_EDI);
2027 gen_op_movl_A0_reg(R_EBP);
2028 gen_op_addl_A0_reg_sN(0, R_ESI);
2031 gen_op_movl_A0_reg(R_EBP);
2032 gen_op_addl_A0_reg_sN(0, R_EDI);
2035 gen_op_movl_A0_reg(R_ESI);
2038 gen_op_movl_A0_reg(R_EDI);
2041 gen_op_movl_A0_reg(R_EBP);
2045 gen_op_movl_A0_reg(R_EBX);
2049 gen_op_addl_A0_im(disp);
2050 gen_op_andl_A0_ffff();
2054 if (rm == 2 || rm == 3 || rm == 6)
2059 gen_op_addl_A0_seg(override);
2069 static void gen_nop_modrm(DisasContext *s, int modrm)
2071 int mod, rm, base, code;
2073 mod = (modrm >> 6) & 3;
2083 code = ldub_code(s->pc++);
2119 /* used for LEA and MOV AX, mem */
2120 static void gen_add_A0_ds_seg(DisasContext *s)
2122 int override, must_add_seg;
2123 must_add_seg = s->addseg;
2125 if (s->override >= 0) {
2126 override = s->override;
2132 #ifdef TARGET_X86_64
2134 gen_op_addq_A0_seg(override);
2138 gen_op_addl_A0_seg(override);
2143 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
2145 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2147 int mod, rm, opreg, disp;
2149 mod = (modrm >> 6) & 3;
2150 rm = (modrm & 7) | REX_B(s);
2154 gen_op_mov_TN_reg(ot, 0, reg);
2155 gen_op_mov_reg_T0(ot, rm);
2157 gen_op_mov_TN_reg(ot, 0, rm);
2159 gen_op_mov_reg_T0(ot, reg);
2162 gen_lea_modrm(s, modrm, &opreg, &disp);
2165 gen_op_mov_TN_reg(ot, 0, reg);
2166 gen_op_st_T0_A0(ot + s->mem_index);
2168 gen_op_ld_T0_A0(ot + s->mem_index);
2170 gen_op_mov_reg_T0(ot, reg);
2175 static inline uint32_t insn_get(DisasContext *s, int ot)
2181 ret = ldub_code(s->pc);
2185 ret = lduw_code(s->pc);
2190 ret = ldl_code(s->pc);
2197 static inline int insn_const_size(unsigned int ot)
2205 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2207 TranslationBlock *tb;
2210 pc = s->cs_base + eip;
2212 /* NOTE: we handle the case where the TB spans two pages here */
2213 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2214 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2215 /* jump to same page: we can use a direct jump */
2216 tcg_gen_goto_tb(tb_num);
2218 tcg_gen_exit_tb((long)tb + tb_num);
2220 /* jump to another page: currently not optimized */
2226 static inline void gen_jcc(DisasContext *s, int b,
2227 target_ulong val, target_ulong next_eip)
2232 if (s->cc_op != CC_OP_DYNAMIC) {
2233 gen_op_set_cc_op(s->cc_op);
2234 s->cc_op = CC_OP_DYNAMIC;
2237 l1 = gen_new_label();
2238 gen_jcc1(s, cc_op, b, l1);
2240 gen_goto_tb(s, 0, next_eip);
2243 gen_goto_tb(s, 1, val);
2247 l1 = gen_new_label();
2248 l2 = gen_new_label();
2249 gen_jcc1(s, cc_op, b, l1);
2251 gen_jmp_im(next_eip);
2261 static void gen_setcc(DisasContext *s, int b)
2263 int inv, jcc_op, l1;
2266 if (is_fast_jcc_case(s, b)) {
2267 /* nominal case: we use a jump */
2268 /* XXX: make it faster by adding new instructions in TCG */
2269 t0 = tcg_temp_local_new(TCG_TYPE_TL);
2270 tcg_gen_movi_tl(t0, 0);
2271 l1 = gen_new_label();
2272 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2273 tcg_gen_movi_tl(t0, 1);
2275 tcg_gen_mov_tl(cpu_T[0], t0);
2278 /* slow case: it is more efficient not to generate a jump,
2279 although it is questionnable whether this optimization is
2282 jcc_op = (b >> 1) & 7;
2283 gen_setcc_slow_T0(s, jcc_op);
2285 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2290 static inline void gen_op_movl_T0_seg(int seg_reg)
2292 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2293 offsetof(CPUX86State,segs[seg_reg].selector));
2296 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2298 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2299 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2300 offsetof(CPUX86State,segs[seg_reg].selector));
2301 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2302 tcg_gen_st_tl(cpu_T[0], cpu_env,
2303 offsetof(CPUX86State,segs[seg_reg].base));
2306 /* move T0 to seg_reg and compute if the CPU state may change. Never
2307 call this function with seg_reg == R_CS */
2308 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2310 if (s->pe && !s->vm86) {
2311 /* XXX: optimize by finding processor state dynamically */
2312 if (s->cc_op != CC_OP_DYNAMIC)
2313 gen_op_set_cc_op(s->cc_op);
2314 gen_jmp_im(cur_eip);
2315 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2316 tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2317 /* abort translation because the addseg value may change or
2318 because ss32 may change. For R_SS, translation must always
2319 stop as a special handling must be done to disable hardware
2320 interrupts for the next instruction */
2321 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2324 gen_op_movl_seg_T0_vm(seg_reg);
2325 if (seg_reg == R_SS)
2330 static inline int svm_is_rep(int prefixes)
2332 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2336 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2337 uint32_t type, uint64_t param)
2339 /* no SVM activated; fast case */
2340 if (likely(!(s->flags & HF_SVMI_MASK)))
2342 if (s->cc_op != CC_OP_DYNAMIC)
2343 gen_op_set_cc_op(s->cc_op);
2344 gen_jmp_im(pc_start - s->cs_base);
2345 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2346 tcg_const_i32(type), tcg_const_i64(param));
2350 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2352 gen_svm_check_intercept_param(s, pc_start, type, 0);
2355 static inline void gen_stack_update(DisasContext *s, int addend)
2357 #ifdef TARGET_X86_64
2359 gen_op_add_reg_im(2, R_ESP, addend);
2363 gen_op_add_reg_im(1, R_ESP, addend);
2365 gen_op_add_reg_im(0, R_ESP, addend);
2369 /* generate a push. It depends on ss32, addseg and dflag */
2370 static void gen_push_T0(DisasContext *s)
2372 #ifdef TARGET_X86_64
2374 gen_op_movq_A0_reg(R_ESP);
2376 gen_op_addq_A0_im(-8);
2377 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2379 gen_op_addq_A0_im(-2);
2380 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2382 gen_op_mov_reg_A0(2, R_ESP);
2386 gen_op_movl_A0_reg(R_ESP);
2388 gen_op_addl_A0_im(-2);
2390 gen_op_addl_A0_im(-4);
2393 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2394 gen_op_addl_A0_seg(R_SS);
2397 gen_op_andl_A0_ffff();
2398 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2399 gen_op_addl_A0_seg(R_SS);
2401 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2402 if (s->ss32 && !s->addseg)
2403 gen_op_mov_reg_A0(1, R_ESP);
2405 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2409 /* generate a push. It depends on ss32, addseg and dflag */
2410 /* slower version for T1, only used for call Ev */
2411 static void gen_push_T1(DisasContext *s)
2413 #ifdef TARGET_X86_64
2415 gen_op_movq_A0_reg(R_ESP);
2417 gen_op_addq_A0_im(-8);
2418 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2420 gen_op_addq_A0_im(-2);
2421 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2423 gen_op_mov_reg_A0(2, R_ESP);
2427 gen_op_movl_A0_reg(R_ESP);
2429 gen_op_addl_A0_im(-2);
2431 gen_op_addl_A0_im(-4);
2434 gen_op_addl_A0_seg(R_SS);
2437 gen_op_andl_A0_ffff();
2438 gen_op_addl_A0_seg(R_SS);
2440 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2442 if (s->ss32 && !s->addseg)
2443 gen_op_mov_reg_A0(1, R_ESP);
2445 gen_stack_update(s, (-2) << s->dflag);
2449 /* two step pop is necessary for precise exceptions */
2450 static void gen_pop_T0(DisasContext *s)
2452 #ifdef TARGET_X86_64
2454 gen_op_movq_A0_reg(R_ESP);
2455 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2459 gen_op_movl_A0_reg(R_ESP);
2462 gen_op_addl_A0_seg(R_SS);
2464 gen_op_andl_A0_ffff();
2465 gen_op_addl_A0_seg(R_SS);
2467 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2471 static void gen_pop_update(DisasContext *s)
2473 #ifdef TARGET_X86_64
2474 if (CODE64(s) && s->dflag) {
2475 gen_stack_update(s, 8);
2479 gen_stack_update(s, 2 << s->dflag);
2483 static void gen_stack_A0(DisasContext *s)
2485 gen_op_movl_A0_reg(R_ESP);
2487 gen_op_andl_A0_ffff();
2488 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2490 gen_op_addl_A0_seg(R_SS);
2493 /* NOTE: wrap around in 16 bit not fully handled */
2494 static void gen_pusha(DisasContext *s)
2497 gen_op_movl_A0_reg(R_ESP);
2498 gen_op_addl_A0_im(-16 << s->dflag);
2500 gen_op_andl_A0_ffff();
2501 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2503 gen_op_addl_A0_seg(R_SS);
2504 for(i = 0;i < 8; i++) {
2505 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2506 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2507 gen_op_addl_A0_im(2 << s->dflag);
2509 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2512 /* NOTE: wrap around in 16 bit not fully handled */
2513 static void gen_popa(DisasContext *s)
2516 gen_op_movl_A0_reg(R_ESP);
2518 gen_op_andl_A0_ffff();
2519 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2520 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2522 gen_op_addl_A0_seg(R_SS);
2523 for(i = 0;i < 8; i++) {
2524 /* ESP is not reloaded */
2526 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2527 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2529 gen_op_addl_A0_im(2 << s->dflag);
2531 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2534 static void gen_enter(DisasContext *s, int esp_addend, int level)
2539 #ifdef TARGET_X86_64
2541 ot = s->dflag ? OT_QUAD : OT_WORD;
2544 gen_op_movl_A0_reg(R_ESP);
2545 gen_op_addq_A0_im(-opsize);
2546 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2549 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2550 gen_op_st_T0_A0(ot + s->mem_index);
2552 /* XXX: must save state */
2553 tcg_gen_helper_0_3(helper_enter64_level,
2554 tcg_const_i32(level),
2555 tcg_const_i32((ot == OT_QUAD)),
2558 gen_op_mov_reg_T1(ot, R_EBP);
2559 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2560 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2564 ot = s->dflag + OT_WORD;
2565 opsize = 2 << s->dflag;
2567 gen_op_movl_A0_reg(R_ESP);
2568 gen_op_addl_A0_im(-opsize);
2570 gen_op_andl_A0_ffff();
2571 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2573 gen_op_addl_A0_seg(R_SS);
2575 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2576 gen_op_st_T0_A0(ot + s->mem_index);
2578 /* XXX: must save state */
2579 tcg_gen_helper_0_3(helper_enter_level,
2580 tcg_const_i32(level),
2581 tcg_const_i32(s->dflag),
2584 gen_op_mov_reg_T1(ot, R_EBP);
2585 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2586 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2590 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2592 if (s->cc_op != CC_OP_DYNAMIC)
2593 gen_op_set_cc_op(s->cc_op);
2594 gen_jmp_im(cur_eip);
2595 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
2599 /* an interrupt is different from an exception because of the
2601 static void gen_interrupt(DisasContext *s, int intno,
2602 target_ulong cur_eip, target_ulong next_eip)
2604 if (s->cc_op != CC_OP_DYNAMIC)
2605 gen_op_set_cc_op(s->cc_op);
2606 gen_jmp_im(cur_eip);
2607 tcg_gen_helper_0_2(helper_raise_interrupt,
2608 tcg_const_i32(intno),
2609 tcg_const_i32(next_eip - cur_eip));
2613 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2615 if (s->cc_op != CC_OP_DYNAMIC)
2616 gen_op_set_cc_op(s->cc_op);
2617 gen_jmp_im(cur_eip);
2618 tcg_gen_helper_0_0(helper_debug);
2622 /* generate a generic end of block. Trace exception is also generated
2624 static void gen_eob(DisasContext *s)
2626 if (s->cc_op != CC_OP_DYNAMIC)
2627 gen_op_set_cc_op(s->cc_op);
2628 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2629 tcg_gen_helper_0_0(helper_reset_inhibit_irq);
2631 if (s->singlestep_enabled) {
2632 tcg_gen_helper_0_0(helper_debug);
2634 tcg_gen_helper_0_0(helper_single_step);
2641 /* generate a jump to eip. No segment change must happen before as a
2642 direct call to the next block may occur */
2643 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2646 if (s->cc_op != CC_OP_DYNAMIC) {
2647 gen_op_set_cc_op(s->cc_op);
2648 s->cc_op = CC_OP_DYNAMIC;
2650 gen_goto_tb(s, tb_num, eip);
2658 static void gen_jmp(DisasContext *s, target_ulong eip)
2660 gen_jmp_tb(s, eip, 0);
2663 static inline void gen_ldq_env_A0(int idx, int offset)
2665 int mem_index = (idx >> 2) - 1;
2666 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2667 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2670 static inline void gen_stq_env_A0(int idx, int offset)
2672 int mem_index = (idx >> 2) - 1;
2673 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2674 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2677 static inline void gen_ldo_env_A0(int idx, int offset)
2679 int mem_index = (idx >> 2) - 1;
2680 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2681 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2682 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2683 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2684 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2687 static inline void gen_sto_env_A0(int idx, int offset)
2689 int mem_index = (idx >> 2) - 1;
2690 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2691 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2692 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2693 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2694 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2697 static inline void gen_op_movo(int d_offset, int s_offset)
2699 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2700 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2701 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2702 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2705 static inline void gen_op_movq(int d_offset, int s_offset)
2707 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2708 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2711 static inline void gen_op_movl(int d_offset, int s_offset)
2713 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2714 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2717 static inline void gen_op_movq_env_0(int d_offset)
2719 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2720 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2723 #define SSE_SPECIAL ((void *)1)
2724 #define SSE_DUMMY ((void *)2)
2726 #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2727 #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2728 helper_ ## x ## ss, helper_ ## x ## sd, }
2730 static void *sse_op_table1[256][4] = {
2731 /* 3DNow! extensions */
2732 [0x0e] = { SSE_DUMMY }, /* femms */
2733 [0x0f] = { SSE_DUMMY }, /* pf... */
2734 /* pure SSE operations */
2735 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2736 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2737 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2738 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2739 [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
2740 [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
2741 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2742 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2744 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2745 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2746 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2747 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2748 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2749 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2750 [0x2e] = { helper_ucomiss, helper_ucomisd },
2751 [0x2f] = { helper_comiss, helper_comisd },
2752 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2753 [0x51] = SSE_FOP(sqrt),
2754 [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL },
2755 [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL },
2756 [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */
2757 [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */
2758 [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */
2759 [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */
2760 [0x58] = SSE_FOP(add),
2761 [0x59] = SSE_FOP(mul),
2762 [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
2763 helper_cvtss2sd, helper_cvtsd2ss },
2764 [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
2765 [0x5c] = SSE_FOP(sub),
2766 [0x5d] = SSE_FOP(min),
2767 [0x5e] = SSE_FOP(div),
2768 [0x5f] = SSE_FOP(max),
2770 [0xc2] = SSE_FOP(cmpeq),
2771 [0xc6] = { helper_shufps, helper_shufpd },
2773 [0x38] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3 */
2774 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3 */
2776 /* MMX ops and their SSE extensions */
2777 [0x60] = MMX_OP2(punpcklbw),
2778 [0x61] = MMX_OP2(punpcklwd),
2779 [0x62] = MMX_OP2(punpckldq),
2780 [0x63] = MMX_OP2(packsswb),
2781 [0x64] = MMX_OP2(pcmpgtb),
2782 [0x65] = MMX_OP2(pcmpgtw),
2783 [0x66] = MMX_OP2(pcmpgtl),
2784 [0x67] = MMX_OP2(packuswb),
2785 [0x68] = MMX_OP2(punpckhbw),
2786 [0x69] = MMX_OP2(punpckhwd),
2787 [0x6a] = MMX_OP2(punpckhdq),
2788 [0x6b] = MMX_OP2(packssdw),
2789 [0x6c] = { NULL, helper_punpcklqdq_xmm },
2790 [0x6d] = { NULL, helper_punpckhqdq_xmm },
2791 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2792 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2793 [0x70] = { helper_pshufw_mmx,
2796 helper_pshuflw_xmm },
2797 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2798 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2799 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2800 [0x74] = MMX_OP2(pcmpeqb),
2801 [0x75] = MMX_OP2(pcmpeqw),
2802 [0x76] = MMX_OP2(pcmpeql),
2803 [0x77] = { SSE_DUMMY }, /* emms */
2804 [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps },
2805 [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps },
2806 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2807 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2808 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2809 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2810 [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps },
2811 [0xd1] = MMX_OP2(psrlw),
2812 [0xd2] = MMX_OP2(psrld),
2813 [0xd3] = MMX_OP2(psrlq),
2814 [0xd4] = MMX_OP2(paddq),
2815 [0xd5] = MMX_OP2(pmullw),
2816 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2817 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2818 [0xd8] = MMX_OP2(psubusb),
2819 [0xd9] = MMX_OP2(psubusw),
2820 [0xda] = MMX_OP2(pminub),
2821 [0xdb] = MMX_OP2(pand),
2822 [0xdc] = MMX_OP2(paddusb),
2823 [0xdd] = MMX_OP2(paddusw),
2824 [0xde] = MMX_OP2(pmaxub),
2825 [0xdf] = MMX_OP2(pandn),
2826 [0xe0] = MMX_OP2(pavgb),
2827 [0xe1] = MMX_OP2(psraw),
2828 [0xe2] = MMX_OP2(psrad),
2829 [0xe3] = MMX_OP2(pavgw),
2830 [0xe4] = MMX_OP2(pmulhuw),
2831 [0xe5] = MMX_OP2(pmulhw),
2832 [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq },
2833 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2834 [0xe8] = MMX_OP2(psubsb),
2835 [0xe9] = MMX_OP2(psubsw),
2836 [0xea] = MMX_OP2(pminsw),
2837 [0xeb] = MMX_OP2(por),
2838 [0xec] = MMX_OP2(paddsb),
2839 [0xed] = MMX_OP2(paddsw),
2840 [0xee] = MMX_OP2(pmaxsw),
2841 [0xef] = MMX_OP2(pxor),
2842 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2843 [0xf1] = MMX_OP2(psllw),
2844 [0xf2] = MMX_OP2(pslld),
2845 [0xf3] = MMX_OP2(psllq),
2846 [0xf4] = MMX_OP2(pmuludq),
2847 [0xf5] = MMX_OP2(pmaddwd),
2848 [0xf6] = MMX_OP2(psadbw),
2849 [0xf7] = MMX_OP2(maskmov),
2850 [0xf8] = MMX_OP2(psubb),
2851 [0xf9] = MMX_OP2(psubw),
2852 [0xfa] = MMX_OP2(psubl),
2853 [0xfb] = MMX_OP2(psubq),
2854 [0xfc] = MMX_OP2(paddb),
2855 [0xfd] = MMX_OP2(paddw),
2856 [0xfe] = MMX_OP2(paddl),
2859 static void *sse_op_table2[3 * 8][2] = {
2860 [0 + 2] = MMX_OP2(psrlw),
2861 [0 + 4] = MMX_OP2(psraw),
2862 [0 + 6] = MMX_OP2(psllw),
2863 [8 + 2] = MMX_OP2(psrld),
2864 [8 + 4] = MMX_OP2(psrad),
2865 [8 + 6] = MMX_OP2(pslld),
2866 [16 + 2] = MMX_OP2(psrlq),
2867 [16 + 3] = { NULL, helper_psrldq_xmm },
2868 [16 + 6] = MMX_OP2(psllq),
2869 [16 + 7] = { NULL, helper_pslldq_xmm },
2872 static void *sse_op_table3[4 * 3] = {
2875 X86_64_ONLY(helper_cvtsq2ss),
2876 X86_64_ONLY(helper_cvtsq2sd),
2880 X86_64_ONLY(helper_cvttss2sq),
2881 X86_64_ONLY(helper_cvttsd2sq),
2885 X86_64_ONLY(helper_cvtss2sq),
2886 X86_64_ONLY(helper_cvtsd2sq),
2889 static void *sse_op_table4[8][4] = {
2900 static void *sse_op_table5[256] = {
2901 [0x0c] = helper_pi2fw,
2902 [0x0d] = helper_pi2fd,
2903 [0x1c] = helper_pf2iw,
2904 [0x1d] = helper_pf2id,
2905 [0x8a] = helper_pfnacc,
2906 [0x8e] = helper_pfpnacc,
2907 [0x90] = helper_pfcmpge,
2908 [0x94] = helper_pfmin,
2909 [0x96] = helper_pfrcp,
2910 [0x97] = helper_pfrsqrt,
2911 [0x9a] = helper_pfsub,
2912 [0x9e] = helper_pfadd,
2913 [0xa0] = helper_pfcmpgt,
2914 [0xa4] = helper_pfmax,
2915 [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */
2916 [0xa7] = helper_movq, /* pfrsqit1 */
2917 [0xaa] = helper_pfsubr,
2918 [0xae] = helper_pfacc,
2919 [0xb0] = helper_pfcmpeq,
2920 [0xb4] = helper_pfmul,
2921 [0xb6] = helper_movq, /* pfrcpit2 */
2922 [0xb7] = helper_pmulhrw_mmx,
2923 [0xbb] = helper_pswapd,
2924 [0xbf] = helper_pavgb_mmx /* pavgusb */
2927 static void *sse_op_table6[256][2] = {
2928 [0x00] = MMX_OP2(pshufb),
2929 [0x01] = MMX_OP2(phaddw),
2930 [0x02] = MMX_OP2(phaddd),
2931 [0x03] = MMX_OP2(phaddsw),
2932 [0x04] = MMX_OP2(pmaddubsw),
2933 [0x05] = MMX_OP2(phsubw),
2934 [0x06] = MMX_OP2(phsubd),
2935 [0x07] = MMX_OP2(phsubsw),
2936 [0x08] = MMX_OP2(psignb),
2937 [0x09] = MMX_OP2(psignw),
2938 [0x0a] = MMX_OP2(psignd),
2939 [0x0b] = MMX_OP2(pmulhrsw),
2940 [0x1c] = MMX_OP2(pabsb),
2941 [0x1d] = MMX_OP2(pabsw),
2942 [0x1e] = MMX_OP2(pabsd),
2945 static void *sse_op_table7[256][2] = {
2946 [0x0f] = MMX_OP2(palignr),
2949 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2951 int b1, op1_offset, op2_offset, is_xmm, val, ot;
2952 int modrm, mod, rm, reg, reg_addr, offset_addr;
2956 if (s->prefix & PREFIX_DATA)
2958 else if (s->prefix & PREFIX_REPZ)
2960 else if (s->prefix & PREFIX_REPNZ)
2964 sse_op2 = sse_op_table1[b][b1];
2967 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2977 /* simple MMX/SSE operation */
2978 if (s->flags & HF_TS_MASK) {
2979 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2982 if (s->flags & HF_EM_MASK) {
2984 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2987 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2988 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
2991 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
2994 tcg_gen_helper_0_0(helper_emms);
2999 tcg_gen_helper_0_0(helper_emms);
3002 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3003 the static cpu state) */
3005 tcg_gen_helper_0_0(helper_enter_mmx);
3008 modrm = ldub_code(s->pc++);
3009 reg = ((modrm >> 3) & 7);
3012 mod = (modrm >> 6) & 3;
3013 if (sse_op2 == SSE_SPECIAL) {
3016 case 0x0e7: /* movntq */
3019 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3020 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3022 case 0x1e7: /* movntdq */
3023 case 0x02b: /* movntps */
3024 case 0x12b: /* movntps */
3025 case 0x3f0: /* lddqu */
3028 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3029 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3031 case 0x6e: /* movd mm, ea */
3032 #ifdef TARGET_X86_64
3033 if (s->dflag == 2) {
3034 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3035 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3039 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3040 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3041 offsetof(CPUX86State,fpregs[reg].mmx));
3042 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
3045 case 0x16e: /* movd xmm, ea */
3046 #ifdef TARGET_X86_64
3047 if (s->dflag == 2) {
3048 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3049 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3050 offsetof(CPUX86State,xmm_regs[reg]));
3051 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
3055 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3056 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3057 offsetof(CPUX86State,xmm_regs[reg]));
3058 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3059 tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
3062 case 0x6f: /* movq mm, ea */
3064 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3065 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3068 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3069 offsetof(CPUX86State,fpregs[rm].mmx));
3070 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3071 offsetof(CPUX86State,fpregs[reg].mmx));
3074 case 0x010: /* movups */
3075 case 0x110: /* movupd */
3076 case 0x028: /* movaps */
3077 case 0x128: /* movapd */
3078 case 0x16f: /* movdqa xmm, ea */
3079 case 0x26f: /* movdqu xmm, ea */
3081 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3082 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3084 rm = (modrm & 7) | REX_B(s);
3085 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3086 offsetof(CPUX86State,xmm_regs[rm]));
3089 case 0x210: /* movss xmm, ea */
3091 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3092 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3093 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3095 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3096 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3097 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3099 rm = (modrm & 7) | REX_B(s);
3100 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3101 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3104 case 0x310: /* movsd xmm, ea */
3106 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3107 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3109 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3110 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3112 rm = (modrm & 7) | REX_B(s);
3113 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3114 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3117 case 0x012: /* movlps */
3118 case 0x112: /* movlpd */
3120 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3121 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3124 rm = (modrm & 7) | REX_B(s);
3125 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3126 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3129 case 0x212: /* movsldup */
3131 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3132 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3134 rm = (modrm & 7) | REX_B(s);
3135 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3136 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3137 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3138 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3140 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3141 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3142 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3143 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3145 case 0x312: /* movddup */
3147 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3148 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3150 rm = (modrm & 7) | REX_B(s);
3151 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3152 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3154 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3155 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3157 case 0x016: /* movhps */
3158 case 0x116: /* movhpd */
3160 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3161 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3164 rm = (modrm & 7) | REX_B(s);
3165 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3166 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3169 case 0x216: /* movshdup */
3171 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3172 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3174 rm = (modrm & 7) | REX_B(s);
3175 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3176 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3177 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3178 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3180 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3181 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3182 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3183 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3185 case 0x7e: /* movd ea, mm */
3186 #ifdef TARGET_X86_64
3187 if (s->dflag == 2) {
3188 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3189 offsetof(CPUX86State,fpregs[reg].mmx));
3190 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3194 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3195 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3196 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3199 case 0x17e: /* movd ea, xmm */
3200 #ifdef TARGET_X86_64
3201 if (s->dflag == 2) {
3202 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3203 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3204 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3208 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3209 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3210 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3213 case 0x27e: /* movq xmm, ea */
3215 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3216 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3218 rm = (modrm & 7) | REX_B(s);
3219 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3220 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3222 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3224 case 0x7f: /* movq ea, mm */
3226 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3227 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3230 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3231 offsetof(CPUX86State,fpregs[reg].mmx));
3234 case 0x011: /* movups */
3235 case 0x111: /* movupd */
3236 case 0x029: /* movaps */
3237 case 0x129: /* movapd */
3238 case 0x17f: /* movdqa ea, xmm */
3239 case 0x27f: /* movdqu ea, xmm */
3241 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3242 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3244 rm = (modrm & 7) | REX_B(s);
3245 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3246 offsetof(CPUX86State,xmm_regs[reg]));
3249 case 0x211: /* movss ea, xmm */
3251 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3252 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3253 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3255 rm = (modrm & 7) | REX_B(s);
3256 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3257 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3260 case 0x311: /* movsd ea, xmm */
3262 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3263 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3265 rm = (modrm & 7) | REX_B(s);
3266 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3267 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3270 case 0x013: /* movlps */
3271 case 0x113: /* movlpd */
3273 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3274 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3279 case 0x017: /* movhps */
3280 case 0x117: /* movhpd */
3282 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3283 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3288 case 0x71: /* shift mm, im */
3291 case 0x171: /* shift xmm, im */
3294 val = ldub_code(s->pc++);
3296 gen_op_movl_T0_im(val);
3297 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3299 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3300 op1_offset = offsetof(CPUX86State,xmm_t0);
3302 gen_op_movl_T0_im(val);
3303 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3305 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3306 op1_offset = offsetof(CPUX86State,mmx_t0);
3308 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3312 rm = (modrm & 7) | REX_B(s);
3313 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3316 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3318 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3319 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3320 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3322 case 0x050: /* movmskps */
3323 rm = (modrm & 7) | REX_B(s);
3324 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3325 offsetof(CPUX86State,xmm_regs[rm]));
3326 tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
3327 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3328 gen_op_mov_reg_T0(OT_LONG, reg);
3330 case 0x150: /* movmskpd */
3331 rm = (modrm & 7) | REX_B(s);
3332 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3333 offsetof(CPUX86State,xmm_regs[rm]));
3334 tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
3335 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3336 gen_op_mov_reg_T0(OT_LONG, reg);
3338 case 0x02a: /* cvtpi2ps */
3339 case 0x12a: /* cvtpi2pd */
3340 tcg_gen_helper_0_0(helper_enter_mmx);
3342 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3343 op2_offset = offsetof(CPUX86State,mmx_t0);
3344 gen_ldq_env_A0(s->mem_index, op2_offset);
3347 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3349 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3350 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3351 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3354 tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1);
3358 tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1);
3362 case 0x22a: /* cvtsi2ss */
3363 case 0x32a: /* cvtsi2sd */
3364 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3365 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3366 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3367 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3368 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3369 if (ot == OT_LONG) {
3370 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3371 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
3373 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_T[0]);
3376 case 0x02c: /* cvttps2pi */
3377 case 0x12c: /* cvttpd2pi */
3378 case 0x02d: /* cvtps2pi */
3379 case 0x12d: /* cvtpd2pi */
3380 tcg_gen_helper_0_0(helper_enter_mmx);
3382 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3383 op2_offset = offsetof(CPUX86State,xmm_t0);
3384 gen_ldo_env_A0(s->mem_index, op2_offset);
3386 rm = (modrm & 7) | REX_B(s);
3387 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3389 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3390 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3391 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3394 tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1);
3397 tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1);
3400 tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1);
3403 tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1);
3407 case 0x22c: /* cvttss2si */
3408 case 0x32c: /* cvttsd2si */
3409 case 0x22d: /* cvtss2si */
3410 case 0x32d: /* cvtsd2si */
3411 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3413 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3415 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3417 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3418 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3420 op2_offset = offsetof(CPUX86State,xmm_t0);
3422 rm = (modrm & 7) | REX_B(s);
3423 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3425 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3427 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3428 if (ot == OT_LONG) {
3429 tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
3430 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3432 tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
3434 gen_op_mov_reg_T0(ot, reg);
3436 case 0xc4: /* pinsrw */
3439 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3440 val = ldub_code(s->pc++);
3443 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3444 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3447 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3448 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3451 case 0xc5: /* pextrw */
3455 val = ldub_code(s->pc++);
3458 rm = (modrm & 7) | REX_B(s);
3459 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3460 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3464 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3465 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3467 reg = ((modrm >> 3) & 7) | rex_r;
3468 gen_op_mov_reg_T0(OT_LONG, reg);
3470 case 0x1d6: /* movq ea, xmm */
3472 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3473 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3475 rm = (modrm & 7) | REX_B(s);
3476 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3477 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3478 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3481 case 0x2d6: /* movq2dq */
3482 tcg_gen_helper_0_0(helper_enter_mmx);
3484 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3485 offsetof(CPUX86State,fpregs[rm].mmx));
3486 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3488 case 0x3d6: /* movdq2q */
3489 tcg_gen_helper_0_0(helper_enter_mmx);
3490 rm = (modrm & 7) | REX_B(s);
3491 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3492 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3494 case 0xd7: /* pmovmskb */
3499 rm = (modrm & 7) | REX_B(s);
3500 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3501 tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
3504 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3505 tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
3507 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3508 reg = ((modrm >> 3) & 7) | rex_r;
3509 gen_op_mov_reg_T0(OT_LONG, reg);
3513 if (!(s->cpuid_ext_features & CPUID_EXT_SSSE3))
3517 modrm = ldub_code(s->pc++);
3519 reg = ((modrm >> 3) & 7) | rex_r;
3520 mod = (modrm >> 6) & 3;
3522 sse_op2 = sse_op_table6[b][b1];
3527 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3529 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3531 op2_offset = offsetof(CPUX86State,xmm_t0);
3532 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3533 gen_ldo_env_A0(s->mem_index, op2_offset);
3536 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3538 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3540 op2_offset = offsetof(CPUX86State,mmx_t0);
3541 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3542 gen_ldq_env_A0(s->mem_index, op2_offset);
3545 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3546 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3547 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3551 if (!(s->cpuid_ext_features & CPUID_EXT_SSSE3))
3555 modrm = ldub_code(s->pc++);
3557 reg = ((modrm >> 3) & 7) | rex_r;
3558 mod = (modrm >> 6) & 3;
3560 sse_op2 = sse_op_table7[b][b1];
3565 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3567 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3569 op2_offset = offsetof(CPUX86State,xmm_t0);
3570 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3571 gen_ldo_env_A0(s->mem_index, op2_offset);
3574 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3576 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3578 op2_offset = offsetof(CPUX86State,mmx_t0);
3579 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3580 gen_ldq_env_A0(s->mem_index, op2_offset);
3583 val = ldub_code(s->pc++);
3585 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3586 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3587 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3593 /* generic MMX or SSE operation */
3595 case 0x70: /* pshufx insn */
3596 case 0xc6: /* pshufx insn */
3597 case 0xc2: /* compare insns */
3604 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3606 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3607 op2_offset = offsetof(CPUX86State,xmm_t0);
3608 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3610 /* specific case for SSE single instructions */
3613 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3614 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3617 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3620 gen_ldo_env_A0(s->mem_index, op2_offset);
3623 rm = (modrm & 7) | REX_B(s);
3624 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3627 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3629 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3630 op2_offset = offsetof(CPUX86State,mmx_t0);
3631 gen_ldq_env_A0(s->mem_index, op2_offset);
3634 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3638 case 0x0f: /* 3DNow! data insns */
3639 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3641 val = ldub_code(s->pc++);
3642 sse_op2 = sse_op_table5[val];
3645 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3646 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3647 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3649 case 0x70: /* pshufx insn */
3650 case 0xc6: /* pshufx insn */
3651 val = ldub_code(s->pc++);
3652 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3653 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3654 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3658 val = ldub_code(s->pc++);
3661 sse_op2 = sse_op_table4[val][b1];
3662 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3663 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3664 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3667 /* maskmov : we must prepare A0 */
3670 #ifdef TARGET_X86_64
3671 if (s->aflag == 2) {
3672 gen_op_movq_A0_reg(R_EDI);
3676 gen_op_movl_A0_reg(R_EDI);
3678 gen_op_andl_A0_ffff();
3680 gen_add_A0_ds_seg(s);
3682 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3683 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3684 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0);
3687 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3688 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3689 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3692 if (b == 0x2e || b == 0x2f) {
3693 s->cc_op = CC_OP_EFLAGS;
3698 /* convert one instruction. s->is_jmp is set if the translation must
3699 be stopped. Return the next pc value */
3700 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3702 int b, prefixes, aflag, dflag;
3704 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3705 target_ulong next_eip, tval;
3708 if (unlikely(loglevel & CPU_LOG_TB_OP))
3709 tcg_gen_debug_insn_start(pc_start);
3717 #ifdef TARGET_X86_64
3722 s->rip_offset = 0; /* for relative ip address */
3724 b = ldub_code(s->pc);
3726 /* check prefixes */
3727 #ifdef TARGET_X86_64
3731 prefixes |= PREFIX_REPZ;
3734 prefixes |= PREFIX_REPNZ;
3737 prefixes |= PREFIX_LOCK;
3758 prefixes |= PREFIX_DATA;
3761 prefixes |= PREFIX_ADR;
3765 rex_w = (b >> 3) & 1;
3766 rex_r = (b & 0x4) << 1;
3767 s->rex_x = (b & 0x2) << 2;
3768 REX_B(s) = (b & 0x1) << 3;
3769 x86_64_hregs = 1; /* select uniform byte register addressing */
3773 /* 0x66 is ignored if rex.w is set */
3776 if (prefixes & PREFIX_DATA)
3779 if (!(prefixes & PREFIX_ADR))
3786 prefixes |= PREFIX_REPZ;
3789 prefixes |= PREFIX_REPNZ;
3792 prefixes |= PREFIX_LOCK;
3813 prefixes |= PREFIX_DATA;
3816 prefixes |= PREFIX_ADR;
3819 if (prefixes & PREFIX_DATA)
3821 if (prefixes & PREFIX_ADR)
3825 s->prefix = prefixes;
3829 /* lock generation */
3830 if (prefixes & PREFIX_LOCK)
3831 tcg_gen_helper_0_0(helper_lock);
3833 /* now check op code */
3837 /**************************/
3838 /* extended op code */
3839 b = ldub_code(s->pc++) | 0x100;
3842 /**************************/
3860 ot = dflag + OT_WORD;
3863 case 0: /* OP Ev, Gv */
3864 modrm = ldub_code(s->pc++);
3865 reg = ((modrm >> 3) & 7) | rex_r;
3866 mod = (modrm >> 6) & 3;
3867 rm = (modrm & 7) | REX_B(s);
3869 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3871 } else if (op == OP_XORL && rm == reg) {
3873 /* xor reg, reg optimisation */
3875 s->cc_op = CC_OP_LOGICB + ot;
3876 gen_op_mov_reg_T0(ot, reg);
3877 gen_op_update1_cc();
3882 gen_op_mov_TN_reg(ot, 1, reg);
3883 gen_op(s, op, ot, opreg);
3885 case 1: /* OP Gv, Ev */
3886 modrm = ldub_code(s->pc++);
3887 mod = (modrm >> 6) & 3;
3888 reg = ((modrm >> 3) & 7) | rex_r;
3889 rm = (modrm & 7) | REX_B(s);
3891 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3892 gen_op_ld_T1_A0(ot + s->mem_index);
3893 } else if (op == OP_XORL && rm == reg) {
3896 gen_op_mov_TN_reg(ot, 1, rm);
3898 gen_op(s, op, ot, reg);
3900 case 2: /* OP A, Iv */
3901 val = insn_get(s, ot);
3902 gen_op_movl_T1_im(val);
3903 gen_op(s, op, ot, OR_EAX);
3912 case 0x80: /* GRP1 */
3921 ot = dflag + OT_WORD;
3923 modrm = ldub_code(s->pc++);
3924 mod = (modrm >> 6) & 3;
3925 rm = (modrm & 7) | REX_B(s);
3926 op = (modrm >> 3) & 7;
3932 s->rip_offset = insn_const_size(ot);
3933 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3944 val = insn_get(s, ot);
3947 val = (int8_t)insn_get(s, OT_BYTE);
3950 gen_op_movl_T1_im(val);
3951 gen_op(s, op, ot, opreg);
3955 /**************************/
3956 /* inc, dec, and other misc arith */
3957 case 0x40 ... 0x47: /* inc Gv */
3958 ot = dflag ? OT_LONG : OT_WORD;
3959 gen_inc(s, ot, OR_EAX + (b & 7), 1);
3961 case 0x48 ... 0x4f: /* dec Gv */
3962 ot = dflag ? OT_LONG : OT_WORD;
3963 gen_inc(s, ot, OR_EAX + (b & 7), -1);
3965 case 0xf6: /* GRP3 */
3970 ot = dflag + OT_WORD;
3972 modrm = ldub_code(s->pc++);
3973 mod = (modrm >> 6) & 3;
3974 rm = (modrm & 7) | REX_B(s);
3975 op = (modrm >> 3) & 7;
3978 s->rip_offset = insn_const_size(ot);
3979 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
3980 gen_op_ld_T0_A0(ot + s->mem_index);
3982 gen_op_mov_TN_reg(ot, 0, rm);
3987 val = insn_get(s, ot);
3988 gen_op_movl_T1_im(val);
3989 gen_op_testl_T0_T1_cc();
3990 s->cc_op = CC_OP_LOGICB + ot;
3993 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
3995 gen_op_st_T0_A0(ot + s->mem_index);
3997 gen_op_mov_reg_T0(ot, rm);
4001 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4003 gen_op_st_T0_A0(ot + s->mem_index);
4005 gen_op_mov_reg_T0(ot, rm);
4007 gen_op_update_neg_cc();
4008 s->cc_op = CC_OP_SUBB + ot;
4013 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4014 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4015 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4016 /* XXX: use 32 bit mul which could be faster */
4017 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4018 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4019 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4020 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4021 s->cc_op = CC_OP_MULB;
4024 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4025 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4026 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4027 /* XXX: use 32 bit mul which could be faster */
4028 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4029 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4030 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4031 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4032 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4033 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4034 s->cc_op = CC_OP_MULW;
4038 #ifdef TARGET_X86_64
4039 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4040 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4041 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4042 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4043 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4044 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4045 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4046 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4047 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4051 t0 = tcg_temp_new(TCG_TYPE_I64);
4052 t1 = tcg_temp_new(TCG_TYPE_I64);
4053 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4054 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4055 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4056 tcg_gen_mul_i64(t0, t0, t1);
4057 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4058 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4059 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4060 tcg_gen_shri_i64(t0, t0, 32);
4061 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4062 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4063 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4066 s->cc_op = CC_OP_MULL;
4068 #ifdef TARGET_X86_64
4070 tcg_gen_helper_0_1(helper_mulq_EAX_T0, cpu_T[0]);
4071 s->cc_op = CC_OP_MULQ;
4079 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4080 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4081 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4082 /* XXX: use 32 bit mul which could be faster */
4083 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4084 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4085 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4086 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4087 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4088 s->cc_op = CC_OP_MULB;
4091 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4092 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4093 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4094 /* XXX: use 32 bit mul which could be faster */
4095 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4096 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4097 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4098 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4099 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4100 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4101 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4102 s->cc_op = CC_OP_MULW;
4106 #ifdef TARGET_X86_64
4107 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4108 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4109 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4110 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4111 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4112 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4113 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4114 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4115 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4116 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4120 t0 = tcg_temp_new(TCG_TYPE_I64);
4121 t1 = tcg_temp_new(TCG_TYPE_I64);
4122 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4123 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4124 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4125 tcg_gen_mul_i64(t0, t0, t1);
4126 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4127 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4128 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4129 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4130 tcg_gen_shri_i64(t0, t0, 32);
4131 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4132 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4133 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4136 s->cc_op = CC_OP_MULL;
4138 #ifdef TARGET_X86_64
4140 tcg_gen_helper_0_1(helper_imulq_EAX_T0, cpu_T[0]);
4141 s->cc_op = CC_OP_MULQ;
4149 gen_jmp_im(pc_start - s->cs_base);
4150 tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
4153 gen_jmp_im(pc_start - s->cs_base);
4154 tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
4158 gen_jmp_im(pc_start - s->cs_base);
4159 tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
4161 #ifdef TARGET_X86_64
4163 gen_jmp_im(pc_start - s->cs_base);
4164 tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
4172 gen_jmp_im(pc_start - s->cs_base);
4173 tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
4176 gen_jmp_im(pc_start - s->cs_base);
4177 tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
4181 gen_jmp_im(pc_start - s->cs_base);
4182 tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
4184 #ifdef TARGET_X86_64
4186 gen_jmp_im(pc_start - s->cs_base);
4187 tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
4197 case 0xfe: /* GRP4 */
4198 case 0xff: /* GRP5 */
4202 ot = dflag + OT_WORD;
4204 modrm = ldub_code(s->pc++);
4205 mod = (modrm >> 6) & 3;
4206 rm = (modrm & 7) | REX_B(s);
4207 op = (modrm >> 3) & 7;
4208 if (op >= 2 && b == 0xfe) {
4212 if (op == 2 || op == 4) {
4213 /* operand size for jumps is 64 bit */
4215 } else if (op == 3 || op == 5) {
4216 /* for call calls, the operand is 16 or 32 bit, even
4218 ot = dflag ? OT_LONG : OT_WORD;
4219 } else if (op == 6) {
4220 /* default push size is 64 bit */
4221 ot = dflag ? OT_QUAD : OT_WORD;
4225 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4226 if (op >= 2 && op != 3 && op != 5)
4227 gen_op_ld_T0_A0(ot + s->mem_index);
4229 gen_op_mov_TN_reg(ot, 0, rm);
4233 case 0: /* inc Ev */
4238 gen_inc(s, ot, opreg, 1);
4240 case 1: /* dec Ev */
4245 gen_inc(s, ot, opreg, -1);
4247 case 2: /* call Ev */
4248 /* XXX: optimize if memory (no 'and' is necessary) */
4250 gen_op_andl_T0_ffff();
4251 next_eip = s->pc - s->cs_base;
4252 gen_movtl_T1_im(next_eip);
4257 case 3: /* lcall Ev */
4258 gen_op_ld_T1_A0(ot + s->mem_index);
4259 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4260 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4262 if (s->pe && !s->vm86) {
4263 if (s->cc_op != CC_OP_DYNAMIC)
4264 gen_op_set_cc_op(s->cc_op);
4265 gen_jmp_im(pc_start - s->cs_base);
4266 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4267 tcg_gen_helper_0_4(helper_lcall_protected,
4268 cpu_tmp2_i32, cpu_T[1],
4269 tcg_const_i32(dflag),
4270 tcg_const_i32(s->pc - pc_start));
4272 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4273 tcg_gen_helper_0_4(helper_lcall_real,
4274 cpu_tmp2_i32, cpu_T[1],
4275 tcg_const_i32(dflag),
4276 tcg_const_i32(s->pc - s->cs_base));
4280 case 4: /* jmp Ev */
4282 gen_op_andl_T0_ffff();
4286 case 5: /* ljmp Ev */
4287 gen_op_ld_T1_A0(ot + s->mem_index);
4288 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4289 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4291 if (s->pe && !s->vm86) {
4292 if (s->cc_op != CC_OP_DYNAMIC)
4293 gen_op_set_cc_op(s->cc_op);
4294 gen_jmp_im(pc_start - s->cs_base);
4295 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4296 tcg_gen_helper_0_3(helper_ljmp_protected,
4299 tcg_const_i32(s->pc - pc_start));
4301 gen_op_movl_seg_T0_vm(R_CS);
4302 gen_op_movl_T0_T1();
4307 case 6: /* push Ev */
4315 case 0x84: /* test Ev, Gv */
4320 ot = dflag + OT_WORD;
4322 modrm = ldub_code(s->pc++);
4323 mod = (modrm >> 6) & 3;
4324 rm = (modrm & 7) | REX_B(s);
4325 reg = ((modrm >> 3) & 7) | rex_r;
4327 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4328 gen_op_mov_TN_reg(ot, 1, reg);
4329 gen_op_testl_T0_T1_cc();
4330 s->cc_op = CC_OP_LOGICB + ot;
4333 case 0xa8: /* test eAX, Iv */
4338 ot = dflag + OT_WORD;
4339 val = insn_get(s, ot);
4341 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4342 gen_op_movl_T1_im(val);
4343 gen_op_testl_T0_T1_cc();
4344 s->cc_op = CC_OP_LOGICB + ot;
4347 case 0x98: /* CWDE/CBW */
4348 #ifdef TARGET_X86_64
4350 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4351 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4352 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4356 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4357 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4358 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4360 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4361 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4362 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4365 case 0x99: /* CDQ/CWD */
4366 #ifdef TARGET_X86_64
4368 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4369 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4370 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4374 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4375 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4376 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4377 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4379 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4380 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4381 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4382 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4385 case 0x1af: /* imul Gv, Ev */
4386 case 0x69: /* imul Gv, Ev, I */
4388 ot = dflag + OT_WORD;
4389 modrm = ldub_code(s->pc++);
4390 reg = ((modrm >> 3) & 7) | rex_r;
4392 s->rip_offset = insn_const_size(ot);
4395 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4397 val = insn_get(s, ot);
4398 gen_op_movl_T1_im(val);
4399 } else if (b == 0x6b) {
4400 val = (int8_t)insn_get(s, OT_BYTE);
4401 gen_op_movl_T1_im(val);
4403 gen_op_mov_TN_reg(ot, 1, reg);
4406 #ifdef TARGET_X86_64
4407 if (ot == OT_QUAD) {
4408 tcg_gen_helper_1_2(helper_imulq_T0_T1, cpu_T[0], cpu_T[0], cpu_T[1]);
4411 if (ot == OT_LONG) {
4412 #ifdef TARGET_X86_64
4413 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4414 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4415 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4416 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4417 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4418 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4422 t0 = tcg_temp_new(TCG_TYPE_I64);
4423 t1 = tcg_temp_new(TCG_TYPE_I64);
4424 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4425 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4426 tcg_gen_mul_i64(t0, t0, t1);
4427 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4428 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4429 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4430 tcg_gen_shri_i64(t0, t0, 32);
4431 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4432 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4436 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4437 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4438 /* XXX: use 32 bit mul which could be faster */
4439 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4440 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4441 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4442 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4444 gen_op_mov_reg_T0(ot, reg);
4445 s->cc_op = CC_OP_MULB + ot;
4448 case 0x1c1: /* xadd Ev, Gv */
4452 ot = dflag + OT_WORD;
4453 modrm = ldub_code(s->pc++);
4454 reg = ((modrm >> 3) & 7) | rex_r;
4455 mod = (modrm >> 6) & 3;
4457 rm = (modrm & 7) | REX_B(s);
4458 gen_op_mov_TN_reg(ot, 0, reg);
4459 gen_op_mov_TN_reg(ot, 1, rm);
4460 gen_op_addl_T0_T1();
4461 gen_op_mov_reg_T1(ot, reg);
4462 gen_op_mov_reg_T0(ot, rm);
4464 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4465 gen_op_mov_TN_reg(ot, 0, reg);
4466 gen_op_ld_T1_A0(ot + s->mem_index);
4467 gen_op_addl_T0_T1();
4468 gen_op_st_T0_A0(ot + s->mem_index);
4469 gen_op_mov_reg_T1(ot, reg);
4471 gen_op_update2_cc();
4472 s->cc_op = CC_OP_ADDB + ot;
4475 case 0x1b1: /* cmpxchg Ev, Gv */
4478 TCGv t0, t1, t2, a0;
4483 ot = dflag + OT_WORD;
4484 modrm = ldub_code(s->pc++);
4485 reg = ((modrm >> 3) & 7) | rex_r;
4486 mod = (modrm >> 6) & 3;
4487 t0 = tcg_temp_local_new(TCG_TYPE_TL);
4488 t1 = tcg_temp_local_new(TCG_TYPE_TL);
4489 t2 = tcg_temp_local_new(TCG_TYPE_TL);
4490 a0 = tcg_temp_local_new(TCG_TYPE_TL);
4491 gen_op_mov_v_reg(ot, t1, reg);
4493 rm = (modrm & 7) | REX_B(s);
4494 gen_op_mov_v_reg(ot, t0, rm);
4496 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4497 tcg_gen_mov_tl(a0, cpu_A0);
4498 gen_op_ld_v(ot + s->mem_index, t0, a0);
4499 rm = 0; /* avoid warning */
4501 label1 = gen_new_label();
4502 tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUState, regs[R_EAX]));
4503 tcg_gen_sub_tl(t2, t2, t0);
4505 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4507 label2 = gen_new_label();
4508 gen_op_mov_reg_v(ot, R_EAX, t0);
4510 gen_set_label(label1);
4511 gen_op_mov_reg_v(ot, rm, t1);
4512 gen_set_label(label2);
4514 tcg_gen_mov_tl(t1, t0);
4515 gen_op_mov_reg_v(ot, R_EAX, t0);
4516 gen_set_label(label1);
4518 gen_op_st_v(ot + s->mem_index, t1, a0);
4520 tcg_gen_mov_tl(cpu_cc_src, t0);
4521 tcg_gen_mov_tl(cpu_cc_dst, t2);
4522 s->cc_op = CC_OP_SUBB + ot;
4529 case 0x1c7: /* cmpxchg8b */
4530 modrm = ldub_code(s->pc++);
4531 mod = (modrm >> 6) & 3;
4532 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4534 #ifdef TARGET_X86_64
4536 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4538 gen_jmp_im(pc_start - s->cs_base);
4539 if (s->cc_op != CC_OP_DYNAMIC)
4540 gen_op_set_cc_op(s->cc_op);
4541 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4542 tcg_gen_helper_0_1(helper_cmpxchg16b, cpu_A0);
4546 if (!(s->cpuid_features & CPUID_CX8))
4548 gen_jmp_im(pc_start - s->cs_base);
4549 if (s->cc_op != CC_OP_DYNAMIC)
4550 gen_op_set_cc_op(s->cc_op);
4551 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4552 tcg_gen_helper_0_1(helper_cmpxchg8b, cpu_A0);
4554 s->cc_op = CC_OP_EFLAGS;
4557 /**************************/
4559 case 0x50 ... 0x57: /* push */
4560 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4563 case 0x58 ... 0x5f: /* pop */
4565 ot = dflag ? OT_QUAD : OT_WORD;
4567 ot = dflag + OT_WORD;
4570 /* NOTE: order is important for pop %sp */
4572 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4574 case 0x60: /* pusha */
4579 case 0x61: /* popa */
4584 case 0x68: /* push Iv */
4587 ot = dflag ? OT_QUAD : OT_WORD;
4589 ot = dflag + OT_WORD;
4592 val = insn_get(s, ot);
4594 val = (int8_t)insn_get(s, OT_BYTE);
4595 gen_op_movl_T0_im(val);
4598 case 0x8f: /* pop Ev */
4600 ot = dflag ? OT_QUAD : OT_WORD;
4602 ot = dflag + OT_WORD;
4604 modrm = ldub_code(s->pc++);
4605 mod = (modrm >> 6) & 3;
4608 /* NOTE: order is important for pop %sp */
4610 rm = (modrm & 7) | REX_B(s);
4611 gen_op_mov_reg_T0(ot, rm);
4613 /* NOTE: order is important too for MMU exceptions */
4614 s->popl_esp_hack = 1 << ot;
4615 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4616 s->popl_esp_hack = 0;
4620 case 0xc8: /* enter */
4623 val = lduw_code(s->pc);
4625 level = ldub_code(s->pc++);
4626 gen_enter(s, val, level);
4629 case 0xc9: /* leave */
4630 /* XXX: exception not precise (ESP is updated before potential exception) */
4632 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4633 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4634 } else if (s->ss32) {
4635 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4636 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4638 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4639 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4643 ot = dflag ? OT_QUAD : OT_WORD;
4645 ot = dflag + OT_WORD;
4647 gen_op_mov_reg_T0(ot, R_EBP);
4650 case 0x06: /* push es */
4651 case 0x0e: /* push cs */
4652 case 0x16: /* push ss */
4653 case 0x1e: /* push ds */
4656 gen_op_movl_T0_seg(b >> 3);
4659 case 0x1a0: /* push fs */
4660 case 0x1a8: /* push gs */
4661 gen_op_movl_T0_seg((b >> 3) & 7);
4664 case 0x07: /* pop es */
4665 case 0x17: /* pop ss */
4666 case 0x1f: /* pop ds */
4671 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4674 /* if reg == SS, inhibit interrupts/trace. */
4675 /* If several instructions disable interrupts, only the
4677 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4678 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4682 gen_jmp_im(s->pc - s->cs_base);
4686 case 0x1a1: /* pop fs */
4687 case 0x1a9: /* pop gs */
4689 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
4692 gen_jmp_im(s->pc - s->cs_base);
4697 /**************************/
4700 case 0x89: /* mov Gv, Ev */
4704 ot = dflag + OT_WORD;
4705 modrm = ldub_code(s->pc++);
4706 reg = ((modrm >> 3) & 7) | rex_r;
4708 /* generate a generic store */
4709 gen_ldst_modrm(s, modrm, ot, reg, 1);
4712 case 0xc7: /* mov Ev, Iv */
4716 ot = dflag + OT_WORD;
4717 modrm = ldub_code(s->pc++);
4718 mod = (modrm >> 6) & 3;
4720 s->rip_offset = insn_const_size(ot);
4721 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4723 val = insn_get(s, ot);
4724 gen_op_movl_T0_im(val);
4726 gen_op_st_T0_A0(ot + s->mem_index);
4728 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
4731 case 0x8b: /* mov Ev, Gv */
4735 ot = OT_WORD + dflag;
4736 modrm = ldub_code(s->pc++);
4737 reg = ((modrm >> 3) & 7) | rex_r;
4739 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4740 gen_op_mov_reg_T0(ot, reg);
4742 case 0x8e: /* mov seg, Gv */
4743 modrm = ldub_code(s->pc++);
4744 reg = (modrm >> 3) & 7;
4745 if (reg >= 6 || reg == R_CS)
4747 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4748 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4750 /* if reg == SS, inhibit interrupts/trace */
4751 /* If several instructions disable interrupts, only the
4753 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4754 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4758 gen_jmp_im(s->pc - s->cs_base);
4762 case 0x8c: /* mov Gv, seg */
4763 modrm = ldub_code(s->pc++);
4764 reg = (modrm >> 3) & 7;
4765 mod = (modrm >> 6) & 3;
4768 gen_op_movl_T0_seg(reg);
4770 ot = OT_WORD + dflag;
4773 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4776 case 0x1b6: /* movzbS Gv, Eb */
4777 case 0x1b7: /* movzwS Gv, Eb */
4778 case 0x1be: /* movsbS Gv, Eb */
4779 case 0x1bf: /* movswS Gv, Eb */
4782 /* d_ot is the size of destination */
4783 d_ot = dflag + OT_WORD;
4784 /* ot is the size of source */
4785 ot = (b & 1) + OT_BYTE;
4786 modrm = ldub_code(s->pc++);
4787 reg = ((modrm >> 3) & 7) | rex_r;
4788 mod = (modrm >> 6) & 3;
4789 rm = (modrm & 7) | REX_B(s);
4792 gen_op_mov_TN_reg(ot, 0, rm);
4793 switch(ot | (b & 8)) {
4795 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4798 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4801 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4805 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4808 gen_op_mov_reg_T0(d_ot, reg);
4810 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4812 gen_op_lds_T0_A0(ot + s->mem_index);
4814 gen_op_ldu_T0_A0(ot + s->mem_index);
4816 gen_op_mov_reg_T0(d_ot, reg);
4821 case 0x8d: /* lea */
4822 ot = dflag + OT_WORD;
4823 modrm = ldub_code(s->pc++);
4824 mod = (modrm >> 6) & 3;
4827 reg = ((modrm >> 3) & 7) | rex_r;
4828 /* we must ensure that no segment is added */
4832 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4834 gen_op_mov_reg_A0(ot - OT_WORD, reg);
4837 case 0xa0: /* mov EAX, Ov */
4839 case 0xa2: /* mov Ov, EAX */
4842 target_ulong offset_addr;
4847 ot = dflag + OT_WORD;
4848 #ifdef TARGET_X86_64
4849 if (s->aflag == 2) {
4850 offset_addr = ldq_code(s->pc);
4852 gen_op_movq_A0_im(offset_addr);
4857 offset_addr = insn_get(s, OT_LONG);
4859 offset_addr = insn_get(s, OT_WORD);
4861 gen_op_movl_A0_im(offset_addr);
4863 gen_add_A0_ds_seg(s);
4865 gen_op_ld_T0_A0(ot + s->mem_index);
4866 gen_op_mov_reg_T0(ot, R_EAX);
4868 gen_op_mov_TN_reg(ot, 0, R_EAX);
4869 gen_op_st_T0_A0(ot + s->mem_index);
4873 case 0xd7: /* xlat */
4874 #ifdef TARGET_X86_64
4875 if (s->aflag == 2) {
4876 gen_op_movq_A0_reg(R_EBX);
4877 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4878 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4879 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4883 gen_op_movl_A0_reg(R_EBX);
4884 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4885 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4886 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4888 gen_op_andl_A0_ffff();
4890 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
4892 gen_add_A0_ds_seg(s);
4893 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
4894 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
4896 case 0xb0 ... 0xb7: /* mov R, Ib */
4897 val = insn_get(s, OT_BYTE);
4898 gen_op_movl_T0_im(val);
4899 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
4901 case 0xb8 ... 0xbf: /* mov R, Iv */
4902 #ifdef TARGET_X86_64
4906 tmp = ldq_code(s->pc);
4908 reg = (b & 7) | REX_B(s);
4909 gen_movtl_T0_im(tmp);
4910 gen_op_mov_reg_T0(OT_QUAD, reg);
4914 ot = dflag ? OT_LONG : OT_WORD;
4915 val = insn_get(s, ot);
4916 reg = (b & 7) | REX_B(s);
4917 gen_op_movl_T0_im(val);
4918 gen_op_mov_reg_T0(ot, reg);
4922 case 0x91 ... 0x97: /* xchg R, EAX */
4923 ot = dflag + OT_WORD;
4924 reg = (b & 7) | REX_B(s);
4928 case 0x87: /* xchg Ev, Gv */
4932 ot = dflag + OT_WORD;
4933 modrm = ldub_code(s->pc++);
4934 reg = ((modrm >> 3) & 7) | rex_r;
4935 mod = (modrm >> 6) & 3;
4937 rm = (modrm & 7) | REX_B(s);
4939 gen_op_mov_TN_reg(ot, 0, reg);
4940 gen_op_mov_TN_reg(ot, 1, rm);
4941 gen_op_mov_reg_T0(ot, rm);
4942 gen_op_mov_reg_T1(ot, reg);
4944 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4945 gen_op_mov_TN_reg(ot, 0, reg);
4946 /* for xchg, lock is implicit */
4947 if (!(prefixes & PREFIX_LOCK))
4948 tcg_gen_helper_0_0(helper_lock);
4949 gen_op_ld_T1_A0(ot + s->mem_index);
4950 gen_op_st_T0_A0(ot + s->mem_index);
4951 if (!(prefixes & PREFIX_LOCK))
4952 tcg_gen_helper_0_0(helper_unlock);
4953 gen_op_mov_reg_T1(ot, reg);
4956 case 0xc4: /* les Gv */
4961 case 0xc5: /* lds Gv */
4966 case 0x1b2: /* lss Gv */
4969 case 0x1b4: /* lfs Gv */
4972 case 0x1b5: /* lgs Gv */
4975 ot = dflag ? OT_LONG : OT_WORD;
4976 modrm = ldub_code(s->pc++);
4977 reg = ((modrm >> 3) & 7) | rex_r;
4978 mod = (modrm >> 6) & 3;
4981 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
4982 gen_op_ld_T1_A0(ot + s->mem_index);
4983 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4984 /* load the segment first to handle exceptions properly */
4985 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4986 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4987 /* then put the data */
4988 gen_op_mov_reg_T1(ot, reg);
4990 gen_jmp_im(s->pc - s->cs_base);
4995 /************************/
5006 ot = dflag + OT_WORD;
5008 modrm = ldub_code(s->pc++);
5009 mod = (modrm >> 6) & 3;
5010 op = (modrm >> 3) & 7;
5016 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5019 opreg = (modrm & 7) | REX_B(s);
5024 gen_shift(s, op, ot, opreg, OR_ECX);
5027 shift = ldub_code(s->pc++);
5029 gen_shifti(s, op, ot, opreg, shift);
5044 case 0x1a4: /* shld imm */
5048 case 0x1a5: /* shld cl */
5052 case 0x1ac: /* shrd imm */
5056 case 0x1ad: /* shrd cl */
5060 ot = dflag + OT_WORD;
5061 modrm = ldub_code(s->pc++);
5062 mod = (modrm >> 6) & 3;
5063 rm = (modrm & 7) | REX_B(s);
5064 reg = ((modrm >> 3) & 7) | rex_r;
5066 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5071 gen_op_mov_TN_reg(ot, 1, reg);
5074 val = ldub_code(s->pc++);
5075 tcg_gen_movi_tl(cpu_T3, val);
5077 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
5079 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5082 /************************/
5085 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5086 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5087 /* XXX: what to do if illegal op ? */
5088 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5091 modrm = ldub_code(s->pc++);
5092 mod = (modrm >> 6) & 3;
5094 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5097 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5099 case 0x00 ... 0x07: /* fxxxs */
5100 case 0x10 ... 0x17: /* fixxxl */
5101 case 0x20 ... 0x27: /* fxxxl */
5102 case 0x30 ... 0x37: /* fixxx */
5109 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5110 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5111 tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
5114 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5115 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5116 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
5119 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5120 (s->mem_index >> 2) - 1);
5121 tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
5125 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5126 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5127 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
5131 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5133 /* fcomp needs pop */
5134 tcg_gen_helper_0_0(helper_fpop);
5138 case 0x08: /* flds */
5139 case 0x0a: /* fsts */
5140 case 0x0b: /* fstps */
5141 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5142 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5143 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5148 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5149 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5150 tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
5153 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5154 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5155 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5158 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5159 (s->mem_index >> 2) - 1);
5160 tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
5164 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5165 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5166 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5171 /* XXX: the corresponding CPUID bit must be tested ! */
5174 tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
5175 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5176 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5179 tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
5180 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5181 (s->mem_index >> 2) - 1);
5185 tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
5186 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5187 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5190 tcg_gen_helper_0_0(helper_fpop);
5195 tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
5196 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5197 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5200 tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
5201 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5202 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5205 tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
5206 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5207 (s->mem_index >> 2) - 1);
5211 tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
5212 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5213 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5217 tcg_gen_helper_0_0(helper_fpop);
5221 case 0x0c: /* fldenv mem */
5222 if (s->cc_op != CC_OP_DYNAMIC)
5223 gen_op_set_cc_op(s->cc_op);
5224 gen_jmp_im(pc_start - s->cs_base);
5225 tcg_gen_helper_0_2(helper_fldenv,
5226 cpu_A0, tcg_const_i32(s->dflag));
5228 case 0x0d: /* fldcw mem */
5229 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5230 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5231 tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
5233 case 0x0e: /* fnstenv mem */
5234 if (s->cc_op != CC_OP_DYNAMIC)
5235 gen_op_set_cc_op(s->cc_op);
5236 gen_jmp_im(pc_start - s->cs_base);
5237 tcg_gen_helper_0_2(helper_fstenv,
5238 cpu_A0, tcg_const_i32(s->dflag));
5240 case 0x0f: /* fnstcw mem */
5241 tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
5242 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5243 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5245 case 0x1d: /* fldt mem */
5246 if (s->cc_op != CC_OP_DYNAMIC)
5247 gen_op_set_cc_op(s->cc_op);
5248 gen_jmp_im(pc_start - s->cs_base);
5249 tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0);
5251 case 0x1f: /* fstpt mem */
5252 if (s->cc_op != CC_OP_DYNAMIC)
5253 gen_op_set_cc_op(s->cc_op);
5254 gen_jmp_im(pc_start - s->cs_base);
5255 tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0);
5256 tcg_gen_helper_0_0(helper_fpop);
5258 case 0x2c: /* frstor mem */
5259 if (s->cc_op != CC_OP_DYNAMIC)
5260 gen_op_set_cc_op(s->cc_op);
5261 gen_jmp_im(pc_start - s->cs_base);
5262 tcg_gen_helper_0_2(helper_frstor,
5263 cpu_A0, tcg_const_i32(s->dflag));
5265 case 0x2e: /* fnsave mem */
5266 if (s->cc_op != CC_OP_DYNAMIC)
5267 gen_op_set_cc_op(s->cc_op);
5268 gen_jmp_im(pc_start - s->cs_base);
5269 tcg_gen_helper_0_2(helper_fsave,
5270 cpu_A0, tcg_const_i32(s->dflag));
5272 case 0x2f: /* fnstsw mem */
5273 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5274 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5275 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5277 case 0x3c: /* fbld */
5278 if (s->cc_op != CC_OP_DYNAMIC)
5279 gen_op_set_cc_op(s->cc_op);
5280 gen_jmp_im(pc_start - s->cs_base);
5281 tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0);
5283 case 0x3e: /* fbstp */
5284 if (s->cc_op != CC_OP_DYNAMIC)
5285 gen_op_set_cc_op(s->cc_op);
5286 gen_jmp_im(pc_start - s->cs_base);
5287 tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0);
5288 tcg_gen_helper_0_0(helper_fpop);
5290 case 0x3d: /* fildll */
5291 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5292 (s->mem_index >> 2) - 1);
5293 tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
5295 case 0x3f: /* fistpll */
5296 tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
5297 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5298 (s->mem_index >> 2) - 1);
5299 tcg_gen_helper_0_0(helper_fpop);
5305 /* register float ops */
5309 case 0x08: /* fld sti */
5310 tcg_gen_helper_0_0(helper_fpush);
5311 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
5313 case 0x09: /* fxchg sti */
5314 case 0x29: /* fxchg4 sti, undocumented op */
5315 case 0x39: /* fxchg7 sti, undocumented op */
5316 tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
5318 case 0x0a: /* grp d9/2 */
5321 /* check exceptions (FreeBSD FPU probe) */
5322 if (s->cc_op != CC_OP_DYNAMIC)
5323 gen_op_set_cc_op(s->cc_op);
5324 gen_jmp_im(pc_start - s->cs_base);
5325 tcg_gen_helper_0_0(helper_fwait);
5331 case 0x0c: /* grp d9/4 */
5334 tcg_gen_helper_0_0(helper_fchs_ST0);
5337 tcg_gen_helper_0_0(helper_fabs_ST0);
5340 tcg_gen_helper_0_0(helper_fldz_FT0);
5341 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5344 tcg_gen_helper_0_0(helper_fxam_ST0);
5350 case 0x0d: /* grp d9/5 */
5354 tcg_gen_helper_0_0(helper_fpush);
5355 tcg_gen_helper_0_0(helper_fld1_ST0);
5358 tcg_gen_helper_0_0(helper_fpush);
5359 tcg_gen_helper_0_0(helper_fldl2t_ST0);
5362 tcg_gen_helper_0_0(helper_fpush);
5363 tcg_gen_helper_0_0(helper_fldl2e_ST0);
5366 tcg_gen_helper_0_0(helper_fpush);
5367 tcg_gen_helper_0_0(helper_fldpi_ST0);
5370 tcg_gen_helper_0_0(helper_fpush);
5371 tcg_gen_helper_0_0(helper_fldlg2_ST0);
5374 tcg_gen_helper_0_0(helper_fpush);
5375 tcg_gen_helper_0_0(helper_fldln2_ST0);
5378 tcg_gen_helper_0_0(helper_fpush);
5379 tcg_gen_helper_0_0(helper_fldz_ST0);
5386 case 0x0e: /* grp d9/6 */
5389 tcg_gen_helper_0_0(helper_f2xm1);
5392 tcg_gen_helper_0_0(helper_fyl2x);
5395 tcg_gen_helper_0_0(helper_fptan);
5397 case 3: /* fpatan */
5398 tcg_gen_helper_0_0(helper_fpatan);
5400 case 4: /* fxtract */
5401 tcg_gen_helper_0_0(helper_fxtract);
5403 case 5: /* fprem1 */
5404 tcg_gen_helper_0_0(helper_fprem1);
5406 case 6: /* fdecstp */
5407 tcg_gen_helper_0_0(helper_fdecstp);
5410 case 7: /* fincstp */
5411 tcg_gen_helper_0_0(helper_fincstp);
5415 case 0x0f: /* grp d9/7 */
5418 tcg_gen_helper_0_0(helper_fprem);
5420 case 1: /* fyl2xp1 */
5421 tcg_gen_helper_0_0(helper_fyl2xp1);
5424 tcg_gen_helper_0_0(helper_fsqrt);
5426 case 3: /* fsincos */
5427 tcg_gen_helper_0_0(helper_fsincos);
5429 case 5: /* fscale */
5430 tcg_gen_helper_0_0(helper_fscale);
5432 case 4: /* frndint */
5433 tcg_gen_helper_0_0(helper_frndint);
5436 tcg_gen_helper_0_0(helper_fsin);
5440 tcg_gen_helper_0_0(helper_fcos);
5444 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5445 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5446 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5452 tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
5454 tcg_gen_helper_0_0(helper_fpop);
5456 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5457 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5461 case 0x02: /* fcom */
5462 case 0x22: /* fcom2, undocumented op */
5463 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5464 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5466 case 0x03: /* fcomp */
5467 case 0x23: /* fcomp3, undocumented op */
5468 case 0x32: /* fcomp5, undocumented op */
5469 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5470 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5471 tcg_gen_helper_0_0(helper_fpop);
5473 case 0x15: /* da/5 */
5475 case 1: /* fucompp */
5476 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5477 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5478 tcg_gen_helper_0_0(helper_fpop);
5479 tcg_gen_helper_0_0(helper_fpop);
5487 case 0: /* feni (287 only, just do nop here) */
5489 case 1: /* fdisi (287 only, just do nop here) */
5492 tcg_gen_helper_0_0(helper_fclex);
5494 case 3: /* fninit */
5495 tcg_gen_helper_0_0(helper_fninit);
5497 case 4: /* fsetpm (287 only, just do nop here) */
5503 case 0x1d: /* fucomi */
5504 if (s->cc_op != CC_OP_DYNAMIC)
5505 gen_op_set_cc_op(s->cc_op);
5506 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5507 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5508 s->cc_op = CC_OP_EFLAGS;
5510 case 0x1e: /* fcomi */
5511 if (s->cc_op != CC_OP_DYNAMIC)
5512 gen_op_set_cc_op(s->cc_op);
5513 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5514 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5515 s->cc_op = CC_OP_EFLAGS;
5517 case 0x28: /* ffree sti */
5518 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5520 case 0x2a: /* fst sti */
5521 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5523 case 0x2b: /* fstp sti */
5524 case 0x0b: /* fstp1 sti, undocumented op */
5525 case 0x3a: /* fstp8 sti, undocumented op */
5526 case 0x3b: /* fstp9 sti, undocumented op */
5527 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5528 tcg_gen_helper_0_0(helper_fpop);
5530 case 0x2c: /* fucom st(i) */
5531 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5532 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5534 case 0x2d: /* fucomp st(i) */
5535 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5536 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5537 tcg_gen_helper_0_0(helper_fpop);
5539 case 0x33: /* de/3 */
5541 case 1: /* fcompp */
5542 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5543 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5544 tcg_gen_helper_0_0(helper_fpop);
5545 tcg_gen_helper_0_0(helper_fpop);
5551 case 0x38: /* ffreep sti, undocumented op */
5552 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5553 tcg_gen_helper_0_0(helper_fpop);
5555 case 0x3c: /* df/4 */
5558 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5559 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5560 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5566 case 0x3d: /* fucomip */
5567 if (s->cc_op != CC_OP_DYNAMIC)
5568 gen_op_set_cc_op(s->cc_op);
5569 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5570 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5571 tcg_gen_helper_0_0(helper_fpop);
5572 s->cc_op = CC_OP_EFLAGS;
5574 case 0x3e: /* fcomip */
5575 if (s->cc_op != CC_OP_DYNAMIC)
5576 gen_op_set_cc_op(s->cc_op);
5577 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5578 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5579 tcg_gen_helper_0_0(helper_fpop);
5580 s->cc_op = CC_OP_EFLAGS;
5582 case 0x10 ... 0x13: /* fcmovxx */
5586 static const uint8_t fcmov_cc[8] = {
5592 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
5593 l1 = gen_new_label();
5594 gen_jcc1(s, s->cc_op, op1, l1);
5595 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));
5604 /************************/
5607 case 0xa4: /* movsS */
5612 ot = dflag + OT_WORD;
5614 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5615 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5621 case 0xaa: /* stosS */
5626 ot = dflag + OT_WORD;
5628 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5629 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5634 case 0xac: /* lodsS */
5639 ot = dflag + OT_WORD;
5640 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5641 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5646 case 0xae: /* scasS */
5651 ot = dflag + OT_WORD;
5652 if (prefixes & PREFIX_REPNZ) {
5653 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5654 } else if (prefixes & PREFIX_REPZ) {
5655 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5658 s->cc_op = CC_OP_SUBB + ot;
5662 case 0xa6: /* cmpsS */
5667 ot = dflag + OT_WORD;
5668 if (prefixes & PREFIX_REPNZ) {
5669 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5670 } else if (prefixes & PREFIX_REPZ) {
5671 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5674 s->cc_op = CC_OP_SUBB + ot;
5677 case 0x6c: /* insS */
5682 ot = dflag ? OT_LONG : OT_WORD;
5683 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5684 gen_op_andl_T0_ffff();
5685 gen_check_io(s, ot, pc_start - s->cs_base,
5686 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
5687 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5688 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5692 gen_jmp(s, s->pc - s->cs_base);
5696 case 0x6e: /* outsS */
5701 ot = dflag ? OT_LONG : OT_WORD;
5702 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5703 gen_op_andl_T0_ffff();
5704 gen_check_io(s, ot, pc_start - s->cs_base,
5705 svm_is_rep(prefixes) | 4);
5706 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5707 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5711 gen_jmp(s, s->pc - s->cs_base);
5716 /************************/
5724 ot = dflag ? OT_LONG : OT_WORD;
5725 val = ldub_code(s->pc++);
5726 gen_op_movl_T0_im(val);
5727 gen_check_io(s, ot, pc_start - s->cs_base,
5728 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5731 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5732 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5733 gen_op_mov_reg_T1(ot, R_EAX);
5736 gen_jmp(s, s->pc - s->cs_base);
5744 ot = dflag ? OT_LONG : OT_WORD;
5745 val = ldub_code(s->pc++);
5746 gen_op_movl_T0_im(val);
5747 gen_check_io(s, ot, pc_start - s->cs_base,
5748 svm_is_rep(prefixes));
5749 gen_op_mov_TN_reg(ot, 1, R_EAX);
5753 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5754 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5755 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5756 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5759 gen_jmp(s, s->pc - s->cs_base);
5767 ot = dflag ? OT_LONG : OT_WORD;
5768 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5769 gen_op_andl_T0_ffff();
5770 gen_check_io(s, ot, pc_start - s->cs_base,
5771 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5774 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5775 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5776 gen_op_mov_reg_T1(ot, R_EAX);
5779 gen_jmp(s, s->pc - s->cs_base);
5787 ot = dflag ? OT_LONG : OT_WORD;
5788 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5789 gen_op_andl_T0_ffff();
5790 gen_check_io(s, ot, pc_start - s->cs_base,
5791 svm_is_rep(prefixes));
5792 gen_op_mov_TN_reg(ot, 1, R_EAX);
5796 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5797 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5798 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5799 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5802 gen_jmp(s, s->pc - s->cs_base);
5806 /************************/
5808 case 0xc2: /* ret im */
5809 val = ldsw_code(s->pc);
5812 if (CODE64(s) && s->dflag)
5814 gen_stack_update(s, val + (2 << s->dflag));
5816 gen_op_andl_T0_ffff();
5820 case 0xc3: /* ret */
5824 gen_op_andl_T0_ffff();
5828 case 0xca: /* lret im */
5829 val = ldsw_code(s->pc);
5832 if (s->pe && !s->vm86) {
5833 if (s->cc_op != CC_OP_DYNAMIC)
5834 gen_op_set_cc_op(s->cc_op);
5835 gen_jmp_im(pc_start - s->cs_base);
5836 tcg_gen_helper_0_2(helper_lret_protected,
5837 tcg_const_i32(s->dflag),
5838 tcg_const_i32(val));
5842 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5844 gen_op_andl_T0_ffff();
5845 /* NOTE: keeping EIP updated is not a problem in case of
5849 gen_op_addl_A0_im(2 << s->dflag);
5850 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5851 gen_op_movl_seg_T0_vm(R_CS);
5852 /* add stack offset */
5853 gen_stack_update(s, val + (4 << s->dflag));
5857 case 0xcb: /* lret */
5860 case 0xcf: /* iret */
5861 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
5864 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5865 s->cc_op = CC_OP_EFLAGS;
5866 } else if (s->vm86) {
5868 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5870 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5871 s->cc_op = CC_OP_EFLAGS;
5874 if (s->cc_op != CC_OP_DYNAMIC)
5875 gen_op_set_cc_op(s->cc_op);
5876 gen_jmp_im(pc_start - s->cs_base);
5877 tcg_gen_helper_0_2(helper_iret_protected,
5878 tcg_const_i32(s->dflag),
5879 tcg_const_i32(s->pc - s->cs_base));
5880 s->cc_op = CC_OP_EFLAGS;
5884 case 0xe8: /* call im */
5887 tval = (int32_t)insn_get(s, OT_LONG);
5889 tval = (int16_t)insn_get(s, OT_WORD);
5890 next_eip = s->pc - s->cs_base;
5894 gen_movtl_T0_im(next_eip);
5899 case 0x9a: /* lcall im */
5901 unsigned int selector, offset;
5905 ot = dflag ? OT_LONG : OT_WORD;
5906 offset = insn_get(s, ot);
5907 selector = insn_get(s, OT_WORD);
5909 gen_op_movl_T0_im(selector);
5910 gen_op_movl_T1_imu(offset);
5913 case 0xe9: /* jmp im */
5915 tval = (int32_t)insn_get(s, OT_LONG);
5917 tval = (int16_t)insn_get(s, OT_WORD);
5918 tval += s->pc - s->cs_base;
5923 case 0xea: /* ljmp im */
5925 unsigned int selector, offset;
5929 ot = dflag ? OT_LONG : OT_WORD;
5930 offset = insn_get(s, ot);
5931 selector = insn_get(s, OT_WORD);
5933 gen_op_movl_T0_im(selector);
5934 gen_op_movl_T1_imu(offset);
5937 case 0xeb: /* jmp Jb */
5938 tval = (int8_t)insn_get(s, OT_BYTE);
5939 tval += s->pc - s->cs_base;
5944 case 0x70 ... 0x7f: /* jcc Jb */
5945 tval = (int8_t)insn_get(s, OT_BYTE);
5947 case 0x180 ... 0x18f: /* jcc Jv */
5949 tval = (int32_t)insn_get(s, OT_LONG);
5951 tval = (int16_t)insn_get(s, OT_WORD);
5954 next_eip = s->pc - s->cs_base;
5958 gen_jcc(s, b, tval, next_eip);
5961 case 0x190 ... 0x19f: /* setcc Gv */
5962 modrm = ldub_code(s->pc++);
5964 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
5966 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5971 ot = dflag + OT_WORD;
5972 modrm = ldub_code(s->pc++);
5973 reg = ((modrm >> 3) & 7) | rex_r;
5974 mod = (modrm >> 6) & 3;
5975 t0 = tcg_temp_local_new(TCG_TYPE_TL);
5977 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
5978 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
5980 rm = (modrm & 7) | REX_B(s);
5981 gen_op_mov_v_reg(ot, t0, rm);
5983 #ifdef TARGET_X86_64
5984 if (ot == OT_LONG) {
5985 /* XXX: specific Intel behaviour ? */
5986 l1 = gen_new_label();
5987 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5988 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
5990 tcg_gen_movi_tl(cpu_tmp0, 0);
5991 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
5995 l1 = gen_new_label();
5996 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5997 gen_op_mov_reg_v(ot, reg, t0);
6004 /************************/
6006 case 0x9c: /* pushf */
6007 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6008 if (s->vm86 && s->iopl != 3) {
6009 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6011 if (s->cc_op != CC_OP_DYNAMIC)
6012 gen_op_set_cc_op(s->cc_op);
6013 tcg_gen_helper_1_0(helper_read_eflags, cpu_T[0]);
6017 case 0x9d: /* popf */
6018 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6019 if (s->vm86 && s->iopl != 3) {
6020 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6025 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6026 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
6028 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6029 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
6032 if (s->cpl <= s->iopl) {
6034 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6035 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
6037 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6038 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
6042 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6043 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
6045 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
6046 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
6051 s->cc_op = CC_OP_EFLAGS;
6052 /* abort translation because TF flag may change */
6053 gen_jmp_im(s->pc - s->cs_base);
6057 case 0x9e: /* sahf */
6058 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6060 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6061 if (s->cc_op != CC_OP_DYNAMIC)
6062 gen_op_set_cc_op(s->cc_op);
6063 gen_compute_eflags(cpu_cc_src);
6064 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6065 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6066 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6067 s->cc_op = CC_OP_EFLAGS;
6069 case 0x9f: /* lahf */
6070 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6072 if (s->cc_op != CC_OP_DYNAMIC)
6073 gen_op_set_cc_op(s->cc_op);
6074 gen_compute_eflags(cpu_T[0]);
6075 /* Note: gen_compute_eflags() only gives the condition codes */
6076 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6077 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6079 case 0xf5: /* cmc */
6080 if (s->cc_op != CC_OP_DYNAMIC)
6081 gen_op_set_cc_op(s->cc_op);
6082 gen_compute_eflags(cpu_cc_src);
6083 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6084 s->cc_op = CC_OP_EFLAGS;
6086 case 0xf8: /* clc */
6087 if (s->cc_op != CC_OP_DYNAMIC)
6088 gen_op_set_cc_op(s->cc_op);
6089 gen_compute_eflags(cpu_cc_src);
6090 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6091 s->cc_op = CC_OP_EFLAGS;
6093 case 0xf9: /* stc */
6094 if (s->cc_op != CC_OP_DYNAMIC)
6095 gen_op_set_cc_op(s->cc_op);
6096 gen_compute_eflags(cpu_cc_src);
6097 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6098 s->cc_op = CC_OP_EFLAGS;
6100 case 0xfc: /* cld */
6101 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6102 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6104 case 0xfd: /* std */
6105 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6106 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
6109 /************************/
6110 /* bit operations */
6111 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6112 ot = dflag + OT_WORD;
6113 modrm = ldub_code(s->pc++);
6114 op = (modrm >> 3) & 7;
6115 mod = (modrm >> 6) & 3;
6116 rm = (modrm & 7) | REX_B(s);
6119 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6120 gen_op_ld_T0_A0(ot + s->mem_index);
6122 gen_op_mov_TN_reg(ot, 0, rm);
6125 val = ldub_code(s->pc++);
6126 gen_op_movl_T1_im(val);
6131 case 0x1a3: /* bt Gv, Ev */
6134 case 0x1ab: /* bts */
6137 case 0x1b3: /* btr */
6140 case 0x1bb: /* btc */
6143 ot = dflag + OT_WORD;
6144 modrm = ldub_code(s->pc++);
6145 reg = ((modrm >> 3) & 7) | rex_r;
6146 mod = (modrm >> 6) & 3;
6147 rm = (modrm & 7) | REX_B(s);
6148 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6150 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6151 /* specific case: we need to add a displacement */
6152 gen_exts(ot, cpu_T[1]);
6153 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6154 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6155 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6156 gen_op_ld_T0_A0(ot + s->mem_index);
6158 gen_op_mov_TN_reg(ot, 0, rm);
6161 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6164 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6165 tcg_gen_movi_tl(cpu_cc_dst, 0);
6168 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6169 tcg_gen_movi_tl(cpu_tmp0, 1);
6170 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6171 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6174 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6175 tcg_gen_movi_tl(cpu_tmp0, 1);
6176 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6177 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6178 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6182 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6183 tcg_gen_movi_tl(cpu_tmp0, 1);
6184 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6185 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6188 s->cc_op = CC_OP_SARB + ot;
6191 gen_op_st_T0_A0(ot + s->mem_index);
6193 gen_op_mov_reg_T0(ot, rm);
6194 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6195 tcg_gen_movi_tl(cpu_cc_dst, 0);
6198 case 0x1bc: /* bsf */
6199 case 0x1bd: /* bsr */
6204 ot = dflag + OT_WORD;
6205 modrm = ldub_code(s->pc++);
6206 reg = ((modrm >> 3) & 7) | rex_r;
6207 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6208 gen_extu(ot, cpu_T[0]);
6209 label1 = gen_new_label();
6210 tcg_gen_movi_tl(cpu_cc_dst, 0);
6211 t0 = tcg_temp_local_new(TCG_TYPE_TL);
6212 tcg_gen_mov_tl(t0, cpu_T[0]);
6213 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6215 tcg_gen_helper_1_1(helper_bsr, cpu_T[0], t0);
6217 tcg_gen_helper_1_1(helper_bsf, cpu_T[0], t0);
6219 gen_op_mov_reg_T0(ot, reg);
6220 tcg_gen_movi_tl(cpu_cc_dst, 1);
6221 gen_set_label(label1);
6222 tcg_gen_discard_tl(cpu_cc_src);
6223 s->cc_op = CC_OP_LOGICB + ot;
6227 /************************/
6229 case 0x27: /* daa */
6232 if (s->cc_op != CC_OP_DYNAMIC)
6233 gen_op_set_cc_op(s->cc_op);
6234 tcg_gen_helper_0_0(helper_daa);
6235 s->cc_op = CC_OP_EFLAGS;
6237 case 0x2f: /* das */
6240 if (s->cc_op != CC_OP_DYNAMIC)
6241 gen_op_set_cc_op(s->cc_op);
6242 tcg_gen_helper_0_0(helper_das);
6243 s->cc_op = CC_OP_EFLAGS;
6245 case 0x37: /* aaa */
6248 if (s->cc_op != CC_OP_DYNAMIC)
6249 gen_op_set_cc_op(s->cc_op);
6250 tcg_gen_helper_0_0(helper_aaa);
6251 s->cc_op = CC_OP_EFLAGS;
6253 case 0x3f: /* aas */
6256 if (s->cc_op != CC_OP_DYNAMIC)
6257 gen_op_set_cc_op(s->cc_op);
6258 tcg_gen_helper_0_0(helper_aas);
6259 s->cc_op = CC_OP_EFLAGS;
6261 case 0xd4: /* aam */
6264 val = ldub_code(s->pc++);
6266 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6268 tcg_gen_helper_0_1(helper_aam, tcg_const_i32(val));
6269 s->cc_op = CC_OP_LOGICB;
6272 case 0xd5: /* aad */
6275 val = ldub_code(s->pc++);
6276 tcg_gen_helper_0_1(helper_aad, tcg_const_i32(val));
6277 s->cc_op = CC_OP_LOGICB;
6279 /************************/
6281 case 0x90: /* nop */
6282 /* XXX: xchg + rex handling */
6283 /* XXX: correct lock test for all insn */
6284 if (prefixes & PREFIX_LOCK)
6286 if (prefixes & PREFIX_REPZ) {
6287 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6290 case 0x9b: /* fwait */
6291 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6292 (HF_MP_MASK | HF_TS_MASK)) {
6293 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6295 if (s->cc_op != CC_OP_DYNAMIC)
6296 gen_op_set_cc_op(s->cc_op);
6297 gen_jmp_im(pc_start - s->cs_base);
6298 tcg_gen_helper_0_0(helper_fwait);
6301 case 0xcc: /* int3 */
6302 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6304 case 0xcd: /* int N */
6305 val = ldub_code(s->pc++);
6306 if (s->vm86 && s->iopl != 3) {
6307 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6309 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6312 case 0xce: /* into */
6315 if (s->cc_op != CC_OP_DYNAMIC)
6316 gen_op_set_cc_op(s->cc_op);
6317 gen_jmp_im(pc_start - s->cs_base);
6318 tcg_gen_helper_0_1(helper_into, tcg_const_i32(s->pc - pc_start));
6320 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6321 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6323 gen_debug(s, pc_start - s->cs_base);
6326 tb_flush(cpu_single_env);
6327 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6330 case 0xfa: /* cli */
6332 if (s->cpl <= s->iopl) {
6333 tcg_gen_helper_0_0(helper_cli);
6335 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6339 tcg_gen_helper_0_0(helper_cli);
6341 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6345 case 0xfb: /* sti */
6347 if (s->cpl <= s->iopl) {
6349 tcg_gen_helper_0_0(helper_sti);
6350 /* interruptions are enabled only the first insn after sti */
6351 /* If several instructions disable interrupts, only the
6353 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6354 tcg_gen_helper_0_0(helper_set_inhibit_irq);
6355 /* give a chance to handle pending irqs */
6356 gen_jmp_im(s->pc - s->cs_base);
6359 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6365 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6369 case 0x62: /* bound */
6372 ot = dflag ? OT_LONG : OT_WORD;
6373 modrm = ldub_code(s->pc++);
6374 reg = (modrm >> 3) & 7;
6375 mod = (modrm >> 6) & 3;
6378 gen_op_mov_TN_reg(ot, 0, reg);
6379 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6380 gen_jmp_im(pc_start - s->cs_base);
6381 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6383 tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
6385 tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
6387 case 0x1c8 ... 0x1cf: /* bswap reg */
6388 reg = (b & 7) | REX_B(s);
6389 #ifdef TARGET_X86_64
6391 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6392 tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
6393 gen_op_mov_reg_T0(OT_QUAD, reg);
6397 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6399 tmp0 = tcg_temp_new(TCG_TYPE_I32);
6400 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6401 tcg_gen_bswap_i32(tmp0, tmp0);
6402 tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6403 gen_op_mov_reg_T0(OT_LONG, reg);
6407 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6408 tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
6409 gen_op_mov_reg_T0(OT_LONG, reg);
6413 case 0xd6: /* salc */
6416 if (s->cc_op != CC_OP_DYNAMIC)
6417 gen_op_set_cc_op(s->cc_op);
6418 gen_compute_eflags_c(cpu_T[0]);
6419 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6420 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6422 case 0xe0: /* loopnz */
6423 case 0xe1: /* loopz */
6424 case 0xe2: /* loop */
6425 case 0xe3: /* jecxz */
6429 tval = (int8_t)insn_get(s, OT_BYTE);
6430 next_eip = s->pc - s->cs_base;
6435 l1 = gen_new_label();
6436 l2 = gen_new_label();
6437 l3 = gen_new_label();
6440 case 0: /* loopnz */
6442 if (s->cc_op != CC_OP_DYNAMIC)
6443 gen_op_set_cc_op(s->cc_op);
6444 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6445 gen_op_jz_ecx(s->aflag, l3);
6446 gen_compute_eflags(cpu_tmp0);
6447 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6449 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6451 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6455 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6456 gen_op_jnz_ecx(s->aflag, l1);
6460 gen_op_jz_ecx(s->aflag, l1);
6465 gen_jmp_im(next_eip);
6474 case 0x130: /* wrmsr */
6475 case 0x132: /* rdmsr */
6477 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6479 if (s->cc_op != CC_OP_DYNAMIC)
6480 gen_op_set_cc_op(s->cc_op);
6481 gen_jmp_im(pc_start - s->cs_base);
6483 tcg_gen_helper_0_0(helper_rdmsr);
6485 tcg_gen_helper_0_0(helper_wrmsr);
6489 case 0x131: /* rdtsc */
6490 if (s->cc_op != CC_OP_DYNAMIC)
6491 gen_op_set_cc_op(s->cc_op);
6492 gen_jmp_im(pc_start - s->cs_base);
6495 tcg_gen_helper_0_0(helper_rdtsc);
6498 gen_jmp(s, s->pc - s->cs_base);
6501 case 0x133: /* rdpmc */
6502 if (s->cc_op != CC_OP_DYNAMIC)
6503 gen_op_set_cc_op(s->cc_op);
6504 gen_jmp_im(pc_start - s->cs_base);
6505 tcg_gen_helper_0_0(helper_rdpmc);
6507 case 0x134: /* sysenter */
6508 /* For Intel SYSENTER is valid on 64-bit */
6509 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6512 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6514 if (s->cc_op != CC_OP_DYNAMIC) {
6515 gen_op_set_cc_op(s->cc_op);
6516 s->cc_op = CC_OP_DYNAMIC;
6518 gen_jmp_im(pc_start - s->cs_base);
6519 tcg_gen_helper_0_0(helper_sysenter);
6523 case 0x135: /* sysexit */
6524 /* For Intel SYSEXIT is valid on 64-bit */
6525 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6528 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6530 if (s->cc_op != CC_OP_DYNAMIC) {
6531 gen_op_set_cc_op(s->cc_op);
6532 s->cc_op = CC_OP_DYNAMIC;
6534 gen_jmp_im(pc_start - s->cs_base);
6535 tcg_gen_helper_0_1(helper_sysexit, tcg_const_i32(dflag));
6539 #ifdef TARGET_X86_64
6540 case 0x105: /* syscall */
6541 /* XXX: is it usable in real mode ? */
6542 if (s->cc_op != CC_OP_DYNAMIC) {
6543 gen_op_set_cc_op(s->cc_op);
6544 s->cc_op = CC_OP_DYNAMIC;
6546 gen_jmp_im(pc_start - s->cs_base);
6547 tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
6550 case 0x107: /* sysret */
6552 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6554 if (s->cc_op != CC_OP_DYNAMIC) {
6555 gen_op_set_cc_op(s->cc_op);
6556 s->cc_op = CC_OP_DYNAMIC;
6558 gen_jmp_im(pc_start - s->cs_base);
6559 tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
6560 /* condition codes are modified only in long mode */
6562 s->cc_op = CC_OP_EFLAGS;
6567 case 0x1a2: /* cpuid */
6568 if (s->cc_op != CC_OP_DYNAMIC)
6569 gen_op_set_cc_op(s->cc_op);
6570 gen_jmp_im(pc_start - s->cs_base);
6571 tcg_gen_helper_0_0(helper_cpuid);
6573 case 0xf4: /* hlt */
6575 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6577 if (s->cc_op != CC_OP_DYNAMIC)
6578 gen_op_set_cc_op(s->cc_op);
6579 gen_jmp_im(pc_start - s->cs_base);
6580 tcg_gen_helper_0_1(helper_hlt, tcg_const_i32(s->pc - pc_start));
6585 modrm = ldub_code(s->pc++);
6586 mod = (modrm >> 6) & 3;
6587 op = (modrm >> 3) & 7;
6590 if (!s->pe || s->vm86)
6592 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
6593 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6597 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6600 if (!s->pe || s->vm86)
6603 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6605 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
6606 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6607 gen_jmp_im(pc_start - s->cs_base);
6608 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6609 tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
6613 if (!s->pe || s->vm86)
6615 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
6616 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6620 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6623 if (!s->pe || s->vm86)
6626 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6628 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
6629 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6630 gen_jmp_im(pc_start - s->cs_base);
6631 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6632 tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
6637 if (!s->pe || s->vm86)
6639 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6640 if (s->cc_op != CC_OP_DYNAMIC)
6641 gen_op_set_cc_op(s->cc_op);
6643 tcg_gen_helper_0_1(helper_verr, cpu_T[0]);
6645 tcg_gen_helper_0_1(helper_verw, cpu_T[0]);
6646 s->cc_op = CC_OP_EFLAGS;
6653 modrm = ldub_code(s->pc++);
6654 mod = (modrm >> 6) & 3;
6655 op = (modrm >> 3) & 7;
6661 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
6662 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6663 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6664 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6665 gen_add_A0_im(s, 2);
6666 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
6668 gen_op_andl_T0_im(0xffffff);
6669 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6674 case 0: /* monitor */
6675 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6678 if (s->cc_op != CC_OP_DYNAMIC)
6679 gen_op_set_cc_op(s->cc_op);
6680 gen_jmp_im(pc_start - s->cs_base);
6681 #ifdef TARGET_X86_64
6682 if (s->aflag == 2) {
6683 gen_op_movq_A0_reg(R_EAX);
6687 gen_op_movl_A0_reg(R_EAX);
6689 gen_op_andl_A0_ffff();
6691 gen_add_A0_ds_seg(s);
6692 tcg_gen_helper_0_1(helper_monitor, cpu_A0);
6695 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6698 if (s->cc_op != CC_OP_DYNAMIC) {
6699 gen_op_set_cc_op(s->cc_op);
6700 s->cc_op = CC_OP_DYNAMIC;
6702 gen_jmp_im(pc_start - s->cs_base);
6703 tcg_gen_helper_0_1(helper_mwait, tcg_const_i32(s->pc - pc_start));
6710 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
6711 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6712 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
6713 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6714 gen_add_A0_im(s, 2);
6715 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
6717 gen_op_andl_T0_im(0xffffff);
6718 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6724 if (s->cc_op != CC_OP_DYNAMIC)
6725 gen_op_set_cc_op(s->cc_op);
6726 gen_jmp_im(pc_start - s->cs_base);
6729 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6732 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6735 tcg_gen_helper_0_2(helper_vmrun,
6736 tcg_const_i32(s->aflag),
6737 tcg_const_i32(s->pc - pc_start));
6742 case 1: /* VMMCALL */
6743 if (!(s->flags & HF_SVME_MASK))
6745 tcg_gen_helper_0_0(helper_vmmcall);
6747 case 2: /* VMLOAD */
6748 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6751 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6754 tcg_gen_helper_0_1(helper_vmload,
6755 tcg_const_i32(s->aflag));
6758 case 3: /* VMSAVE */
6759 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6762 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6765 tcg_gen_helper_0_1(helper_vmsave,
6766 tcg_const_i32(s->aflag));
6770 if ((!(s->flags & HF_SVME_MASK) &&
6771 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
6775 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6778 tcg_gen_helper_0_0(helper_stgi);
6782 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6785 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6788 tcg_gen_helper_0_0(helper_clgi);
6791 case 6: /* SKINIT */
6792 if ((!(s->flags & HF_SVME_MASK) &&
6793 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
6796 tcg_gen_helper_0_0(helper_skinit);
6798 case 7: /* INVLPGA */
6799 if (!(s->flags & HF_SVME_MASK) || !s->pe)
6802 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6805 tcg_gen_helper_0_1(helper_invlpga,
6806 tcg_const_i32(s->aflag));
6812 } else if (s->cpl != 0) {
6813 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6815 gen_svm_check_intercept(s, pc_start,
6816 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
6817 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6818 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
6819 gen_add_A0_im(s, 2);
6820 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6822 gen_op_andl_T0_im(0xffffff);
6824 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
6825 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
6827 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
6828 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
6833 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
6834 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
6835 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
6839 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6841 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
6842 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6843 tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
6844 gen_jmp_im(s->pc - s->cs_base);
6848 case 7: /* invlpg */
6850 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6853 #ifdef TARGET_X86_64
6854 if (CODE64(s) && rm == 0) {
6856 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6857 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
6858 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6859 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
6866 if (s->cc_op != CC_OP_DYNAMIC)
6867 gen_op_set_cc_op(s->cc_op);
6868 gen_jmp_im(pc_start - s->cs_base);
6869 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6870 tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
6871 gen_jmp_im(s->pc - s->cs_base);
6880 case 0x108: /* invd */
6881 case 0x109: /* wbinvd */
6883 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6885 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
6889 case 0x63: /* arpl or movslS (x86_64) */
6890 #ifdef TARGET_X86_64
6893 /* d_ot is the size of destination */
6894 d_ot = dflag + OT_WORD;
6896 modrm = ldub_code(s->pc++);
6897 reg = ((modrm >> 3) & 7) | rex_r;
6898 mod = (modrm >> 6) & 3;
6899 rm = (modrm & 7) | REX_B(s);
6902 gen_op_mov_TN_reg(OT_LONG, 0, rm);
6904 if (d_ot == OT_QUAD)
6905 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
6906 gen_op_mov_reg_T0(d_ot, reg);
6908 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6909 if (d_ot == OT_QUAD) {
6910 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
6912 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6914 gen_op_mov_reg_T0(d_ot, reg);
6922 if (!s->pe || s->vm86)
6924 t0 = tcg_temp_local_new(TCG_TYPE_TL);
6925 t1 = tcg_temp_local_new(TCG_TYPE_TL);
6926 t2 = tcg_temp_local_new(TCG_TYPE_TL);
6928 modrm = ldub_code(s->pc++);
6929 reg = (modrm >> 3) & 7;
6930 mod = (modrm >> 6) & 3;
6933 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
6934 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6936 gen_op_mov_v_reg(ot, t0, rm);
6938 gen_op_mov_v_reg(ot, t1, reg);
6939 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
6940 tcg_gen_andi_tl(t1, t1, 3);
6941 tcg_gen_movi_tl(t2, 0);
6942 label1 = gen_new_label();
6943 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
6944 tcg_gen_andi_tl(t0, t0, ~3);
6945 tcg_gen_or_tl(t0, t0, t1);
6946 tcg_gen_movi_tl(t2, CC_Z);
6947 gen_set_label(label1);
6949 gen_op_st_v(ot + s->mem_index, t0, cpu_A0);
6951 gen_op_mov_reg_v(ot, rm, t0);
6953 if (s->cc_op != CC_OP_DYNAMIC)
6954 gen_op_set_cc_op(s->cc_op);
6955 gen_compute_eflags(cpu_cc_src);
6956 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
6957 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
6958 s->cc_op = CC_OP_EFLAGS;
6964 case 0x102: /* lar */
6965 case 0x103: /* lsl */
6969 if (!s->pe || s->vm86)
6971 ot = dflag ? OT_LONG : OT_WORD;
6972 modrm = ldub_code(s->pc++);
6973 reg = ((modrm >> 3) & 7) | rex_r;
6974 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6975 t0 = tcg_temp_local_new(TCG_TYPE_TL);
6976 if (s->cc_op != CC_OP_DYNAMIC)
6977 gen_op_set_cc_op(s->cc_op);
6979 tcg_gen_helper_1_1(helper_lar, t0, cpu_T[0]);
6981 tcg_gen_helper_1_1(helper_lsl, t0, cpu_T[0]);
6982 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
6983 label1 = gen_new_label();
6984 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
6985 gen_op_mov_reg_v(ot, reg, t0);
6986 gen_set_label(label1);
6987 s->cc_op = CC_OP_EFLAGS;
6992 modrm = ldub_code(s->pc++);
6993 mod = (modrm >> 6) & 3;
6994 op = (modrm >> 3) & 7;
6996 case 0: /* prefetchnta */
6997 case 1: /* prefetchnt0 */
6998 case 2: /* prefetchnt0 */
6999 case 3: /* prefetchnt0 */
7002 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7003 /* nothing more to do */
7005 default: /* nop (multi byte) */
7006 gen_nop_modrm(s, modrm);
7010 case 0x119 ... 0x11f: /* nop (multi byte) */
7011 modrm = ldub_code(s->pc++);
7012 gen_nop_modrm(s, modrm);
7014 case 0x120: /* mov reg, crN */
7015 case 0x122: /* mov crN, reg */
7017 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7019 modrm = ldub_code(s->pc++);
7020 if ((modrm & 0xc0) != 0xc0)
7022 rm = (modrm & 7) | REX_B(s);
7023 reg = ((modrm >> 3) & 7) | rex_r;
7034 if (s->cc_op != CC_OP_DYNAMIC)
7035 gen_op_set_cc_op(s->cc_op);
7036 gen_jmp_im(pc_start - s->cs_base);
7038 gen_op_mov_TN_reg(ot, 0, rm);
7039 tcg_gen_helper_0_2(helper_write_crN,
7040 tcg_const_i32(reg), cpu_T[0]);
7041 gen_jmp_im(s->pc - s->cs_base);
7044 tcg_gen_helper_1_1(helper_read_crN,
7045 cpu_T[0], tcg_const_i32(reg));
7046 gen_op_mov_reg_T0(ot, rm);
7054 case 0x121: /* mov reg, drN */
7055 case 0x123: /* mov drN, reg */
7057 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7059 modrm = ldub_code(s->pc++);
7060 if ((modrm & 0xc0) != 0xc0)
7062 rm = (modrm & 7) | REX_B(s);
7063 reg = ((modrm >> 3) & 7) | rex_r;
7068 /* XXX: do it dynamically with CR4.DE bit */
7069 if (reg == 4 || reg == 5 || reg >= 8)
7072 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7073 gen_op_mov_TN_reg(ot, 0, rm);
7074 tcg_gen_helper_0_2(helper_movl_drN_T0,
7075 tcg_const_i32(reg), cpu_T[0]);
7076 gen_jmp_im(s->pc - s->cs_base);
7079 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7080 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7081 gen_op_mov_reg_T0(ot, rm);
7085 case 0x106: /* clts */
7087 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7089 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7090 tcg_gen_helper_0_0(helper_clts);
7091 /* abort block because static cpu state changed */
7092 gen_jmp_im(s->pc - s->cs_base);
7096 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3 support */
7097 case 0x1c3: /* MOVNTI reg, mem */
7098 if (!(s->cpuid_features & CPUID_SSE2))
7100 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7101 modrm = ldub_code(s->pc++);
7102 mod = (modrm >> 6) & 3;
7105 reg = ((modrm >> 3) & 7) | rex_r;
7106 /* generate a generic store */
7107 gen_ldst_modrm(s, modrm, ot, reg, 1);
7110 modrm = ldub_code(s->pc++);
7111 mod = (modrm >> 6) & 3;
7112 op = (modrm >> 3) & 7;
7114 case 0: /* fxsave */
7115 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7116 (s->flags & HF_EM_MASK))
7118 if (s->flags & HF_TS_MASK) {
7119 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7122 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7123 if (s->cc_op != CC_OP_DYNAMIC)
7124 gen_op_set_cc_op(s->cc_op);
7125 gen_jmp_im(pc_start - s->cs_base);
7126 tcg_gen_helper_0_2(helper_fxsave,
7127 cpu_A0, tcg_const_i32((s->dflag == 2)));
7129 case 1: /* fxrstor */
7130 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7131 (s->flags & HF_EM_MASK))
7133 if (s->flags & HF_TS_MASK) {
7134 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7137 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7138 if (s->cc_op != CC_OP_DYNAMIC)
7139 gen_op_set_cc_op(s->cc_op);
7140 gen_jmp_im(pc_start - s->cs_base);
7141 tcg_gen_helper_0_2(helper_fxrstor,
7142 cpu_A0, tcg_const_i32((s->dflag == 2)));
7144 case 2: /* ldmxcsr */
7145 case 3: /* stmxcsr */
7146 if (s->flags & HF_TS_MASK) {
7147 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7150 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7153 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7155 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7156 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7158 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7159 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7162 case 5: /* lfence */
7163 case 6: /* mfence */
7164 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
7167 case 7: /* sfence / clflush */
7168 if ((modrm & 0xc7) == 0xc0) {
7170 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7171 if (!(s->cpuid_features & CPUID_SSE))
7175 if (!(s->cpuid_features & CPUID_CLFLUSH))
7177 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7184 case 0x10d: /* 3DNow! prefetch(w) */
7185 modrm = ldub_code(s->pc++);
7186 mod = (modrm >> 6) & 3;
7189 gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
7190 /* ignore for now */
7192 case 0x1aa: /* rsm */
7193 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7194 if (!(s->flags & HF_SMM_MASK))
7196 if (s->cc_op != CC_OP_DYNAMIC) {
7197 gen_op_set_cc_op(s->cc_op);
7198 s->cc_op = CC_OP_DYNAMIC;
7200 gen_jmp_im(s->pc - s->cs_base);
7201 tcg_gen_helper_0_0(helper_rsm);
7204 case 0x10e ... 0x10f:
7205 /* 3DNow! instructions, ignore prefixes */
7206 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7207 case 0x110 ... 0x117:
7208 case 0x128 ... 0x12f:
7209 case 0x138 ... 0x13a:
7210 case 0x150 ... 0x177:
7211 case 0x17c ... 0x17f:
7213 case 0x1c4 ... 0x1c6:
7214 case 0x1d0 ... 0x1fe:
7215 gen_sse(s, b, pc_start, rex_r);
7220 /* lock generation */
7221 if (s->prefix & PREFIX_LOCK)
7222 tcg_gen_helper_0_0(helper_unlock);
7225 if (s->prefix & PREFIX_LOCK)
7226 tcg_gen_helper_0_0(helper_unlock);
7227 /* XXX: ensure that no lock was generated */
7228 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7232 void optimize_flags_init(void)
7234 #if TCG_TARGET_REG_BITS == 32
7235 assert(sizeof(CCTable) == (1 << 3));
7237 assert(sizeof(CCTable) == (1 << 4));
7239 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
7240 cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,
7241 TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
7242 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
7243 TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
7244 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
7245 TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
7246 cpu_cc_tmp = tcg_global_mem_new(TCG_TYPE_TL,
7247 TCG_AREG0, offsetof(CPUState, cc_tmp), "cc_tmp");
7249 /* register helpers */
7251 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
7255 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7256 basic block 'tb'. If search_pc is TRUE, also generate PC
7257 information for each intermediate instruction. */
7258 static inline void gen_intermediate_code_internal(CPUState *env,
7259 TranslationBlock *tb,
7262 DisasContext dc1, *dc = &dc1;
7263 target_ulong pc_ptr;
7264 uint16_t *gen_opc_end;
7267 target_ulong pc_start;
7268 target_ulong cs_base;
7272 /* generate intermediate code */
7274 cs_base = tb->cs_base;
7276 cflags = tb->cflags;
7278 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7279 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7280 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7281 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7283 dc->vm86 = (flags >> VM_SHIFT) & 1;
7284 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7285 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7286 dc->tf = (flags >> TF_SHIFT) & 1;
7287 dc->singlestep_enabled = env->singlestep_enabled;
7288 dc->cc_op = CC_OP_DYNAMIC;
7289 dc->cs_base = cs_base;
7291 dc->popl_esp_hack = 0;
7292 /* select memory access functions */
7294 if (flags & HF_SOFTMMU_MASK) {
7296 dc->mem_index = 2 * 4;
7298 dc->mem_index = 1 * 4;
7300 dc->cpuid_features = env->cpuid_features;
7301 dc->cpuid_ext_features = env->cpuid_ext_features;
7302 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7303 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7304 #ifdef TARGET_X86_64
7305 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7306 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7309 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7310 (flags & HF_INHIBIT_IRQ_MASK)
7311 #ifndef CONFIG_SOFTMMU
7312 || (flags & HF_SOFTMMU_MASK)
7316 /* check addseg logic */
7317 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7318 printf("ERROR addseg\n");
7321 cpu_T[0] = tcg_temp_new(TCG_TYPE_TL);
7322 cpu_T[1] = tcg_temp_new(TCG_TYPE_TL);
7323 cpu_A0 = tcg_temp_new(TCG_TYPE_TL);
7324 cpu_T3 = tcg_temp_new(TCG_TYPE_TL);
7326 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
7327 cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);
7328 cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);
7329 cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);
7330 cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);
7331 cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL);
7332 cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL);
7333 cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR);
7334 cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR);
7336 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7338 dc->is_jmp = DISAS_NEXT;
7342 max_insns = tb->cflags & CF_COUNT_MASK;
7344 max_insns = CF_COUNT_MASK;
7348 if (env->nb_breakpoints > 0) {
7349 for(j = 0; j < env->nb_breakpoints; j++) {
7350 if (env->breakpoints[j] == pc_ptr) {
7351 gen_debug(dc, pc_ptr - dc->cs_base);
7357 j = gen_opc_ptr - gen_opc_buf;
7361 gen_opc_instr_start[lj++] = 0;
7363 gen_opc_pc[lj] = pc_ptr;
7364 gen_opc_cc_op[lj] = dc->cc_op;
7365 gen_opc_instr_start[lj] = 1;
7366 gen_opc_icount[lj] = num_insns;
7368 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7371 pc_ptr = disas_insn(dc, pc_ptr);
7373 /* stop translation if indicated */
7376 /* if single step mode, we generate only one instruction and
7377 generate an exception */
7378 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7379 the flag and abort the translation to give the irqs a
7380 change to be happen */
7381 if (dc->tf || dc->singlestep_enabled ||
7382 (flags & HF_INHIBIT_IRQ_MASK)) {
7383 gen_jmp_im(pc_ptr - dc->cs_base);
7387 /* if too long translation, stop generation too */
7388 if (gen_opc_ptr >= gen_opc_end ||
7389 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7390 num_insns >= max_insns) {
7391 gen_jmp_im(pc_ptr - dc->cs_base);
7396 if (tb->cflags & CF_LAST_IO)
7398 gen_icount_end(tb, num_insns);
7399 *gen_opc_ptr = INDEX_op_end;
7400 /* we don't forget to fill the last values */
7402 j = gen_opc_ptr - gen_opc_buf;
7405 gen_opc_instr_start[lj++] = 0;
7409 if (loglevel & CPU_LOG_TB_CPU) {
7410 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
7412 if (loglevel & CPU_LOG_TB_IN_ASM) {
7414 fprintf(logfile, "----------------\n");
7415 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7416 #ifdef TARGET_X86_64
7421 disas_flags = !dc->code32;
7422 target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
7423 fprintf(logfile, "\n");
7428 tb->size = pc_ptr - pc_start;
7429 tb->icount = num_insns;
7433 void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7435 gen_intermediate_code_internal(env, tb, 0);
7438 void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7440 gen_intermediate_code_internal(env, tb, 1);
7443 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7444 unsigned long searched_pc, int pc_pos, void *puc)
7448 if (loglevel & CPU_LOG_TB_OP) {
7450 fprintf(logfile, "RESTORE:\n");
7451 for(i = 0;i <= pc_pos; i++) {
7452 if (gen_opc_instr_start[i]) {
7453 fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7456 fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7457 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7458 (uint32_t)tb->cs_base);
7461 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7462 cc_op = gen_opc_cc_op[pc_pos];
7463 if (cc_op != CC_OP_DYNAMIC)