2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35 #include <linux/unistd.h>
36 #include <linux/version.h>
38 _syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount)
40 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
41 #define modify_ldt_ldt_s user_desc
43 #endif /* USE_CODE_COPY */
45 CPUX86State *cpu_x86_init(void)
52 env = malloc(sizeof(CPUX86State));
55 memset(env, 0, sizeof(CPUX86State));
56 /* init various static tables */
59 optimize_flags_init();
62 /* testing code for code copy case */
64 struct modify_ldt_ldt_s ldt;
67 ldt.base_addr = (unsigned long)env;
68 ldt.limit = (sizeof(CPUState) + 0xfff) >> 12;
70 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
71 ldt.read_exec_only = 0;
72 ldt.limit_in_pages = 1;
73 ldt.seg_not_present = 0;
75 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
77 asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
85 /* NOTE: must be called outside the CPU execute loop */
86 void cpu_reset(CPUX86State *env)
90 memset(env, 0, offsetof(CPUX86State, breakpoints));
94 /* init to reset state */
97 env->hflags |= HF_SOFTMMU_MASK;
100 cpu_x86_update_cr0(env, 0x60000010);
101 env->a20_mask = 0xffffffff;
103 env->idt.limit = 0xffff;
104 env->gdt.limit = 0xffff;
105 env->ldt.limit = 0xffff;
106 env->ldt.flags = DESC_P_MASK;
107 env->tr.limit = 0xffff;
108 env->tr.flags = DESC_P_MASK;
110 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0xffff0000, 0xffff, 0);
111 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
112 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
113 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
114 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
115 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
118 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
123 for(i = 0;i < 8; i++)
128 void cpu_x86_close(CPUX86State *env)
133 /***********************************************************/
136 static const char *cc_op_str[] = {
171 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
175 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
177 eflags = env->eflags;
178 fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
179 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
180 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d\n",
181 env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
182 env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
184 eflags & DF_MASK ? 'D' : '-',
185 eflags & CC_O ? 'O' : '-',
186 eflags & CC_S ? 'S' : '-',
187 eflags & CC_Z ? 'Z' : '-',
188 eflags & CC_A ? 'A' : '-',
189 eflags & CC_P ? 'P' : '-',
190 eflags & CC_C ? 'C' : '-',
191 env->hflags & HF_CPL_MASK,
192 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
193 (env->a20_mask >> 20) & 1);
194 for(i = 0; i < 6; i++) {
195 SegmentCache *sc = &env->segs[i];
196 fprintf(f, "%s =%04x %08x %08x %08x\n",
203 fprintf(f, "LDT=%04x %08x %08x %08x\n",
208 fprintf(f, "TR =%04x %08x %08x %08x\n",
213 fprintf(f, "GDT= %08x %08x\n",
214 (int)env->gdt.base, env->gdt.limit);
215 fprintf(f, "IDT= %08x %08x\n",
216 (int)env->idt.base, env->idt.limit);
217 fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
218 env->cr[0], env->cr[2], env->cr[3], env->cr[4]);
220 if (flags & X86_DUMP_CCOP) {
221 if ((unsigned)env->cc_op < CC_OP_NB)
222 snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
224 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
225 fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
226 env->cc_src, env->cc_dst, cc_op_name);
228 if (flags & X86_DUMP_FPU) {
229 fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
230 (double)env->fpregs[0],
231 (double)env->fpregs[1],
232 (double)env->fpregs[2],
233 (double)env->fpregs[3]);
234 fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
235 (double)env->fpregs[4],
236 (double)env->fpregs[5],
237 (double)env->fpregs[7],
238 (double)env->fpregs[8]);
242 /***********************************************************/
244 /* XXX: add PGE support */
246 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
248 a20_state = (a20_state != 0);
249 if (a20_state != ((env->a20_mask >> 20) & 1)) {
250 #if defined(DEBUG_MMU)
251 printf("A20 update: a20=%d\n", a20_state);
253 /* if the cpu is currently executing code, we must unlink it and
254 all the potentially executing TB */
255 cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
257 /* when a20 is changed, all the MMU mappings are invalid, so
258 we must flush everything */
260 env->a20_mask = 0xffefffff | (a20_state << 20);
264 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
268 #if defined(DEBUG_MMU)
269 printf("CR0 update: CR0=0x%08x\n", new_cr0);
271 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
272 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
275 env->cr[0] = new_cr0 | CR0_ET_MASK;
277 /* update PE flag in hidden flags */
278 pe_state = (env->cr[0] & CR0_PE_MASK);
279 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
280 /* ensure that ADDSEG is always set in real mode */
281 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
282 /* update FPU flags */
283 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
284 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
287 void cpu_x86_update_cr3(CPUX86State *env, uint32_t new_cr3)
289 env->cr[3] = new_cr3;
290 if (env->cr[0] & CR0_PG_MASK) {
291 #if defined(DEBUG_MMU)
292 printf("CR3 update: CR3=%08x\n", new_cr3);
298 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
300 #if defined(DEBUG_MMU)
301 printf("CR4 update: CR4=%08x\n", env->cr[4]);
303 if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
304 (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
307 env->cr[4] = new_cr4;
310 /* XXX: also flush 4MB pages */
311 void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
313 tlb_flush_page(env, addr);
317 -1 = cannot handle fault
318 0 = nothing more to do
319 1 = generate PF fault
320 2 = soft MMU activation required for this block
322 int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
323 int is_write, int is_user, int is_softmmu)
325 uint8_t *pde_ptr, *pte_ptr;
326 uint32_t pde, pte, virt_addr, ptep;
327 int error_code, is_dirty, prot, page_size, ret;
328 unsigned long paddr, vaddr, page_offset;
330 #if defined(DEBUG_MMU)
331 printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
332 addr, is_write, is_user, env->eip);
336 if (env->user_mode_only) {
337 /* user mode only emulation */
342 if (!(env->cr[0] & CR0_PG_MASK)) {
344 virt_addr = addr & TARGET_PAGE_MASK;
345 prot = PAGE_READ | PAGE_WRITE;
350 /* page directory entry */
351 pde_ptr = phys_ram_base +
352 (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask);
353 pde = ldl_raw(pde_ptr);
354 if (!(pde & PG_PRESENT_MASK)) {
358 /* if PSE bit is set, then we use a 4MB page */
359 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
361 if (!(pde & PG_USER_MASK))
362 goto do_fault_protect;
363 if (is_write && !(pde & PG_RW_MASK))
364 goto do_fault_protect;
366 if ((env->cr[0] & CR0_WP_MASK) &&
367 is_write && !(pde & PG_RW_MASK))
368 goto do_fault_protect;
370 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
371 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
372 pde |= PG_ACCESSED_MASK;
374 pde |= PG_DIRTY_MASK;
375 stl_raw(pde_ptr, pde);
378 pte = pde & ~0x003ff000; /* align to 4MB */
380 page_size = 4096 * 1024;
381 virt_addr = addr & ~0x003fffff;
383 if (!(pde & PG_ACCESSED_MASK)) {
384 pde |= PG_ACCESSED_MASK;
385 stl_raw(pde_ptr, pde);
388 /* page directory entry */
389 pte_ptr = phys_ram_base +
390 (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask);
391 pte = ldl_raw(pte_ptr);
392 if (!(pte & PG_PRESENT_MASK)) {
396 /* combine pde and pte user and rw protections */
399 if (!(ptep & PG_USER_MASK))
400 goto do_fault_protect;
401 if (is_write && !(ptep & PG_RW_MASK))
402 goto do_fault_protect;
404 if ((env->cr[0] & CR0_WP_MASK) &&
405 is_write && !(ptep & PG_RW_MASK))
406 goto do_fault_protect;
408 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
409 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
410 pte |= PG_ACCESSED_MASK;
412 pte |= PG_DIRTY_MASK;
413 stl_raw(pte_ptr, pte);
416 virt_addr = addr & ~0xfff;
419 /* the page can be put in the TLB */
421 if (pte & PG_DIRTY_MASK) {
422 /* only set write access if already dirty... otherwise wait
425 if (ptep & PG_RW_MASK)
428 if (!(env->cr[0] & CR0_WP_MASK) ||
435 pte = pte & env->a20_mask;
437 /* Even if 4MB pages, we map only one 4KB page in the cache to
438 avoid filling it too fast */
439 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
440 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
441 vaddr = virt_addr + page_offset;
443 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
446 error_code = PG_ERROR_P_MASK;
449 env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
451 env->error_code |= PG_ERROR_U_MASK;
455 #if defined(CONFIG_USER_ONLY)
456 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
461 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
463 uint8_t *pde_ptr, *pte_ptr;
464 uint32_t pde, pte, paddr, page_offset, page_size;
466 if (!(env->cr[0] & CR0_PG_MASK)) {
470 /* page directory entry */
471 pde_ptr = phys_ram_base +
472 (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask);
473 pde = ldl_raw(pde_ptr);
474 if (!(pde & PG_PRESENT_MASK))
476 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
477 pte = pde & ~0x003ff000; /* align to 4MB */
478 page_size = 4096 * 1024;
480 /* page directory entry */
481 pte_ptr = phys_ram_base +
482 (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask);
483 pte = ldl_raw(pte_ptr);
484 if (!(pte & PG_PRESENT_MASK))
489 pte = pte & env->a20_mask;
490 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
491 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
496 #if defined(USE_CODE_COPY)
509 uint8_t fpregs1[8 * 10];
512 void restore_native_fp_state(CPUState *env)
515 struct fpstate fp1, *fp = &fp1;
517 fp->fpuc = env->fpuc;
518 fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
520 for (i=7; i>=0; i--) {
522 if (env->fptags[i]) {
525 /* the FPU automatically computes it */
530 for(i = 0;i < 8; i++) {
531 memcpy(&fp->fpregs1[i * 10], &env->fpregs[j], 10);
534 asm volatile ("frstor %0" : "=m" (*fp));
535 env->native_fp_regs = 1;
538 void save_native_fp_state(CPUState *env)
542 struct fpstate fp1, *fp = &fp1;
544 asm volatile ("fsave %0" : : "m" (*fp));
545 env->fpuc = fp->fpuc;
546 env->fpstt = (fp->fpus >> 11) & 7;
547 env->fpus = fp->fpus & ~0x3800;
549 for(i = 0;i < 8; i++) {
550 env->fptags[i] = ((fptag & 3) == 3);
554 for(i = 0;i < 8; i++) {
555 memcpy(&env->fpregs[j], &fp->fpregs1[i * 10], 10);
558 /* we must restore the default rounding state */
559 /* XXX: we do not restore the exception state */
560 fpuc = 0x037f | (env->fpuc & (3 << 10));
561 asm volatile("fldcw %0" : : "m" (fpuc));
562 env->native_fp_regs = 0;