2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 CPUX86State *cpu_x86_init(void)
42 env = malloc(sizeof(CPUX86State));
45 memset(env, 0, sizeof(CPUX86State));
50 /* flags setup : we activate the IRQs by default as in user mode */
51 env->eflags = 0x2 | IF_MASK;
55 env->hflags |= HF_SOFTMMU_MASK;
57 /* init various static tables */
60 optimize_flags_init();
65 void cpu_x86_close(CPUX86State *env)
70 /***********************************************************/
73 static const char *cc_op_str[] = {
106 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
110 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
112 eflags = env->eflags;
113 fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
114 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
115 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d\n",
116 env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
117 env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
119 eflags & DF_MASK ? 'D' : '-',
120 eflags & CC_O ? 'O' : '-',
121 eflags & CC_S ? 'S' : '-',
122 eflags & CC_Z ? 'Z' : '-',
123 eflags & CC_A ? 'A' : '-',
124 eflags & CC_P ? 'P' : '-',
125 eflags & CC_C ? 'C' : '-',
126 env->hflags & HF_CPL_MASK);
127 for(i = 0; i < 6; i++) {
128 SegmentCache *sc = &env->segs[i];
129 fprintf(f, "%s =%04x %08x %08x %08x\n",
136 fprintf(f, "LDT=%04x %08x %08x %08x\n",
141 fprintf(f, "TR =%04x %08x %08x %08x\n",
146 fprintf(f, "GDT= %08x %08x\n",
147 (int)env->gdt.base, env->gdt.limit);
148 fprintf(f, "IDT= %08x %08x\n",
149 (int)env->idt.base, env->idt.limit);
150 fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
151 env->cr[0], env->cr[2], env->cr[3], env->cr[4]);
153 if (flags & X86_DUMP_CCOP) {
154 if ((unsigned)env->cc_op < CC_OP_NB)
155 strcpy(cc_op_name, cc_op_str[env->cc_op]);
157 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
158 fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
159 env->cc_src, env->cc_dst, cc_op_name);
161 if (flags & X86_DUMP_FPU) {
162 fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
163 (double)env->fpregs[0],
164 (double)env->fpregs[1],
165 (double)env->fpregs[2],
166 (double)env->fpregs[3]);
167 fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
168 (double)env->fpregs[4],
169 (double)env->fpregs[5],
170 (double)env->fpregs[7],
171 (double)env->fpregs[8]);
175 /***********************************************************/
177 /* XXX: add PGE support */
179 /* called when cr3 or PG bit are modified */
180 static int last_pg_state = -1;
181 static int last_pe_state = 0;
182 static uint32_t a20_mask;
187 uint8_t *phys_ram_base;
189 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
191 a20_state = (a20_state != 0);
192 if (a20_state != a20_enabled) {
193 /* if the cpu is currently executing code, we must unlink it and
194 all the potentially executing TB */
195 cpu_interrupt(env, 0);
197 /* when a20 is changed, all the MMU mappings are invalid, so
198 we must flush everything */
201 a20_enabled = a20_state;
203 a20_mask = 0xffffffff;
205 a20_mask = 0xffefffff;
209 void cpu_x86_update_cr0(CPUX86State *env)
211 int pg_state, pe_state;
214 printf("CR0 update: CR0=0x%08x\n", env->cr[0]);
216 pg_state = env->cr[0] & CR0_PG_MASK;
217 if (pg_state != last_pg_state) {
220 last_pg_state = pg_state;
222 pe_state = env->cr[0] & CR0_PE_MASK;
223 if (last_pe_state != pe_state) {
225 last_pe_state = pe_state;
229 void cpu_x86_update_cr3(CPUX86State *env)
231 if (env->cr[0] & CR0_PG_MASK) {
232 #if defined(DEBUG_MMU)
233 printf("CR3 update: CR3=%08x\n", env->cr[3]);
240 void cpu_x86_init_mmu(CPUX86State *env)
243 a20_mask = 0xffffffff;
246 cpu_x86_update_cr0(env);
249 /* XXX: also flush 4MB pages */
250 void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
253 unsigned long virt_addr;
255 tlb_flush_page(env, addr);
257 flags = page_get_flags(addr);
258 if (flags & PAGE_VALID) {
259 virt_addr = addr & ~0xfff;
260 #if !defined(CONFIG_SOFTMMU)
261 munmap((void *)virt_addr, 4096);
263 page_set_flags(virt_addr, virt_addr + 4096, 0);
268 -1 = cannot handle fault
269 0 = nothing more to do
270 1 = generate PF fault
271 2 = soft MMU activation required for this block
273 int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
274 int is_write, int is_user, int is_softmmu)
276 uint8_t *pde_ptr, *pte_ptr;
277 uint32_t pde, pte, virt_addr;
278 int error_code, is_dirty, prot, page_size, ret;
282 printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
283 addr, is_write, is_user, env->eip);
286 if (env->user_mode_only) {
287 /* user mode only emulation */
292 if (!(env->cr[0] & CR0_PG_MASK)) {
294 virt_addr = addr & TARGET_PAGE_MASK;
295 prot = PROT_READ | PROT_WRITE;
300 /* page directory entry */
301 pde_ptr = phys_ram_base +
302 (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & a20_mask);
303 pde = ldl_raw(pde_ptr);
304 if (!(pde & PG_PRESENT_MASK)) {
309 if (!(pde & PG_USER_MASK))
310 goto do_fault_protect;
311 if (is_write && !(pde & PG_RW_MASK))
312 goto do_fault_protect;
314 if ((env->cr[0] & CR0_WP_MASK) && (pde & PG_USER_MASK) &&
315 is_write && !(pde & PG_RW_MASK))
316 goto do_fault_protect;
318 /* if PSE bit is set, then we use a 4MB page */
319 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
320 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
321 if (!(pde & PG_ACCESSED_MASK)) {
322 pde |= PG_ACCESSED_MASK;
324 pde |= PG_DIRTY_MASK;
325 stl_raw(pde_ptr, pde);
328 pte = pde & ~0x003ff000; /* align to 4MB */
329 page_size = 4096 * 1024;
330 virt_addr = addr & ~0x003fffff;
332 if (!(pde & PG_ACCESSED_MASK)) {
333 pde |= PG_ACCESSED_MASK;
334 stl_raw(pde_ptr, pde);
337 /* page directory entry */
338 pte_ptr = phys_ram_base +
339 (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask);
340 pte = ldl_raw(pte_ptr);
341 if (!(pte & PG_PRESENT_MASK)) {
346 if (!(pte & PG_USER_MASK))
347 goto do_fault_protect;
348 if (is_write && !(pte & PG_RW_MASK))
349 goto do_fault_protect;
351 if ((env->cr[0] & CR0_WP_MASK) && (pte & PG_USER_MASK) &&
352 is_write && !(pte & PG_RW_MASK))
353 goto do_fault_protect;
355 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
356 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
357 pte |= PG_ACCESSED_MASK;
359 pte |= PG_DIRTY_MASK;
360 stl_raw(pte_ptr, pte);
363 virt_addr = addr & ~0xfff;
365 /* the page can be put in the TLB */
368 if (pte & PG_RW_MASK)
371 if (!(env->cr[0] & CR0_WP_MASK) || !(pte & PG_USER_MASK) ||
377 pte = pte & a20_mask;
378 #if !defined(CONFIG_SOFTMMU)
382 unsigned long paddr, vaddr, address, addend, page_offset;
385 /* software MMU case. Even if 4MB pages, we map only one 4KB
386 page in the cache to avoid filling it too fast */
387 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
388 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
389 vaddr = virt_addr + page_offset;
390 index = (addr >> 12) & (CPU_TLB_SIZE - 1);
391 pd = physpage_find(paddr);
394 address = vaddr | pd;
397 /* standard memory */
399 addend = (unsigned long)phys_ram_base + pd;
402 env->tlb_read[is_user][index].address = address;
403 env->tlb_read[is_user][index].addend = addend;
404 if (prot & PROT_WRITE) {
405 env->tlb_write[is_user][index].address = address;
406 env->tlb_write[is_user][index].addend = addend;
408 env->tlb_write[is_user][index].address = -1;
409 env->tlb_write[is_user][index].addend = -1;
411 page_set_flags(vaddr, vaddr + TARGET_PAGE_SIZE,
412 PAGE_VALID | PAGE_EXEC | prot);
415 #if !defined(CONFIG_SOFTMMU)
418 /* XXX: incorrect for 4MB pages */
419 pd = physpage_find(pte & ~0xfff);
420 if ((pd & 0xfff) != 0) {
421 /* IO access: no mapping is done as it will be handled by the
423 if (!(env->hflags & HF_SOFTMMU_MASK))
427 map_addr = mmap((void *)virt_addr, page_size, prot,
428 MAP_SHARED | MAP_FIXED, phys_ram_fd, pd);
429 if (map_addr == MAP_FAILED) {
431 "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x\n",
432 pte & ~0xfff, virt_addr);
436 printf("mmaping 0x%08x to virt 0x%08x pse=%d\n",
437 pte & ~0xfff, virt_addr, (page_size != 4096));
439 page_set_flags(virt_addr, virt_addr + page_size,
440 PAGE_VALID | PAGE_EXEC | prot);
446 error_code = PG_ERROR_P_MASK;
449 env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
451 env->error_code |= PG_ERROR_U_MASK;