2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
35 #include <linux/unistd.h>
36 #include <linux/version.h>
38 _syscall3(int, modify_ldt, int, func, void *, ptr, unsigned long, bytecount)
40 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 66)
41 #define modify_ldt_ldt_s user_desc
43 #endif /* USE_CODE_COPY */
45 CPUX86State *cpu_x86_init(void)
53 env = malloc(sizeof(CPUX86State));
56 memset(env, 0, sizeof(CPUX86State));
58 /* init to reset state */
62 env->hflags |= HF_SOFTMMU_MASK;
65 cpu_x86_update_cr0(env, 0x60000010);
66 env->a20_mask = 0xffffffff;
68 env->idt.limit = 0xffff;
69 env->gdt.limit = 0xffff;
70 env->ldt.limit = 0xffff;
71 env->ldt.flags = DESC_P_MASK;
72 env->tr.limit = 0xffff;
73 env->tr.flags = DESC_P_MASK;
75 /* not correct (CS base=0xffff0000) */
76 cpu_x86_load_seg_cache(env, R_CS, 0xf000, (uint8_t *)0x000f0000, 0xffff, 0);
77 cpu_x86_load_seg_cache(env, R_DS, 0, NULL, 0xffff, 0);
78 cpu_x86_load_seg_cache(env, R_ES, 0, NULL, 0xffff, 0);
79 cpu_x86_load_seg_cache(env, R_SS, 0, NULL, 0xffff, 0);
80 cpu_x86_load_seg_cache(env, R_FS, 0, NULL, 0xffff, 0);
81 cpu_x86_load_seg_cache(env, R_GS, 0, NULL, 0xffff, 0);
84 env->regs[R_EDX] = 0x600; /* indicate P6 processor */
93 /* init various static tables */
96 optimize_flags_init();
99 /* testing code for code copy case */
101 struct modify_ldt_ldt_s ldt;
103 ldt.entry_number = 1;
104 ldt.base_addr = (unsigned long)env;
105 ldt.limit = (sizeof(CPUState) + 0xfff) >> 12;
107 ldt.contents = MODIFY_LDT_CONTENTS_DATA;
108 ldt.read_exec_only = 0;
109 ldt.limit_in_pages = 1;
110 ldt.seg_not_present = 0;
112 modify_ldt(1, &ldt, sizeof(ldt)); /* write ldt entry */
114 asm volatile ("movl %0, %%fs" : : "r" ((1 << 3) | 7));
115 cpu_single_env = env;
121 void cpu_x86_close(CPUX86State *env)
126 /***********************************************************/
129 static const char *cc_op_str[] = {
164 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
168 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
170 eflags = env->eflags;
171 fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
172 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
173 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d\n",
174 env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
175 env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
177 eflags & DF_MASK ? 'D' : '-',
178 eflags & CC_O ? 'O' : '-',
179 eflags & CC_S ? 'S' : '-',
180 eflags & CC_Z ? 'Z' : '-',
181 eflags & CC_A ? 'A' : '-',
182 eflags & CC_P ? 'P' : '-',
183 eflags & CC_C ? 'C' : '-',
184 env->hflags & HF_CPL_MASK,
185 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1);
186 for(i = 0; i < 6; i++) {
187 SegmentCache *sc = &env->segs[i];
188 fprintf(f, "%s =%04x %08x %08x %08x\n",
195 fprintf(f, "LDT=%04x %08x %08x %08x\n",
200 fprintf(f, "TR =%04x %08x %08x %08x\n",
205 fprintf(f, "GDT= %08x %08x\n",
206 (int)env->gdt.base, env->gdt.limit);
207 fprintf(f, "IDT= %08x %08x\n",
208 (int)env->idt.base, env->idt.limit);
209 fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
210 env->cr[0], env->cr[2], env->cr[3], env->cr[4]);
212 if (flags & X86_DUMP_CCOP) {
213 if ((unsigned)env->cc_op < CC_OP_NB)
214 strcpy(cc_op_name, cc_op_str[env->cc_op]);
216 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
217 fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
218 env->cc_src, env->cc_dst, cc_op_name);
220 if (flags & X86_DUMP_FPU) {
221 fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
222 (double)env->fpregs[0],
223 (double)env->fpregs[1],
224 (double)env->fpregs[2],
225 (double)env->fpregs[3]);
226 fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
227 (double)env->fpregs[4],
228 (double)env->fpregs[5],
229 (double)env->fpregs[7],
230 (double)env->fpregs[8]);
234 /***********************************************************/
236 /* XXX: add PGE support */
238 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
240 a20_state = (a20_state != 0);
241 if (a20_state != ((env->a20_mask >> 20) & 1)) {
242 #if defined(DEBUG_MMU)
243 printf("A20 update: a20=%d\n", a20_state);
245 /* if the cpu is currently executing code, we must unlink it and
246 all the potentially executing TB */
247 cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
249 /* when a20 is changed, all the MMU mappings are invalid, so
250 we must flush everything */
252 env->a20_mask = 0xffefffff | (a20_state << 20);
256 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
260 #if defined(DEBUG_MMU)
261 printf("CR0 update: CR0=0x%08x\n", new_cr0);
263 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
264 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
267 env->cr[0] = new_cr0;
269 /* update PE flag in hidden flags */
270 pe_state = (env->cr[0] & CR0_PE_MASK);
271 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
272 /* ensure that ADDSEG is always set in real mode */
273 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
274 /* update FPU flags */
275 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
276 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
279 void cpu_x86_update_cr3(CPUX86State *env, uint32_t new_cr3)
281 env->cr[3] = new_cr3;
282 if (env->cr[0] & CR0_PG_MASK) {
283 #if defined(DEBUG_MMU)
284 printf("CR3 update: CR3=%08x\n", new_cr3);
290 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
292 #if defined(DEBUG_MMU)
293 printf("CR4 update: CR4=%08x\n", env->cr[4]);
295 if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
296 (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
299 env->cr[4] = new_cr4;
302 /* XXX: also flush 4MB pages */
303 void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
305 tlb_flush_page(env, addr);
309 -1 = cannot handle fault
310 0 = nothing more to do
311 1 = generate PF fault
312 2 = soft MMU activation required for this block
314 int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
315 int is_write, int is_user, int is_softmmu)
317 uint8_t *pde_ptr, *pte_ptr;
318 uint32_t pde, pte, virt_addr, ptep;
319 int error_code, is_dirty, prot, page_size, ret;
320 unsigned long paddr, vaddr, page_offset;
322 #if defined(DEBUG_MMU)
323 printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
324 addr, is_write, is_user, env->eip);
327 if (env->user_mode_only) {
328 /* user mode only emulation */
333 if (!(env->cr[0] & CR0_PG_MASK)) {
335 virt_addr = addr & TARGET_PAGE_MASK;
336 prot = PAGE_READ | PAGE_WRITE;
341 /* page directory entry */
342 pde_ptr = phys_ram_base +
343 (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask);
344 pde = ldl_raw(pde_ptr);
345 if (!(pde & PG_PRESENT_MASK)) {
349 /* if PSE bit is set, then we use a 4MB page */
350 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
352 if (!(pde & PG_USER_MASK))
353 goto do_fault_protect;
354 if (is_write && !(pde & PG_RW_MASK))
355 goto do_fault_protect;
357 if ((env->cr[0] & CR0_WP_MASK) &&
358 is_write && !(pde & PG_RW_MASK))
359 goto do_fault_protect;
361 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
362 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
363 pde |= PG_ACCESSED_MASK;
365 pde |= PG_DIRTY_MASK;
366 stl_raw(pde_ptr, pde);
369 pte = pde & ~0x003ff000; /* align to 4MB */
371 page_size = 4096 * 1024;
372 virt_addr = addr & ~0x003fffff;
374 if (!(pde & PG_ACCESSED_MASK)) {
375 pde |= PG_ACCESSED_MASK;
376 stl_raw(pde_ptr, pde);
379 /* page directory entry */
380 pte_ptr = phys_ram_base +
381 (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask);
382 pte = ldl_raw(pte_ptr);
383 if (!(pte & PG_PRESENT_MASK)) {
387 /* combine pde and pte user and rw protections */
390 if (!(ptep & PG_USER_MASK))
391 goto do_fault_protect;
392 if (is_write && !(ptep & PG_RW_MASK))
393 goto do_fault_protect;
395 if ((env->cr[0] & CR0_WP_MASK) &&
396 is_write && !(ptep & PG_RW_MASK))
397 goto do_fault_protect;
399 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
400 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
401 pte |= PG_ACCESSED_MASK;
403 pte |= PG_DIRTY_MASK;
404 stl_raw(pte_ptr, pte);
407 virt_addr = addr & ~0xfff;
410 /* the page can be put in the TLB */
412 if (pte & PG_DIRTY_MASK) {
413 /* only set write access if already dirty... otherwise wait
416 if (ptep & PG_RW_MASK)
419 if (!(env->cr[0] & CR0_WP_MASK) ||
426 pte = pte & env->a20_mask;
428 /* Even if 4MB pages, we map only one 4KB page in the cache to
429 avoid filling it too fast */
430 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
431 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
432 vaddr = virt_addr + page_offset;
434 ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
437 error_code = PG_ERROR_P_MASK;
440 env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
442 env->error_code |= PG_ERROR_U_MASK;
446 #if defined(CONFIG_USER_ONLY)
447 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
452 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
454 uint8_t *pde_ptr, *pte_ptr;
455 uint32_t pde, pte, paddr, page_offset, page_size;
457 if (!(env->cr[0] & CR0_PG_MASK)) {
461 /* page directory entry */
462 pde_ptr = phys_ram_base +
463 (((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & env->a20_mask);
464 pde = ldl_raw(pde_ptr);
465 if (!(pde & PG_PRESENT_MASK))
467 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
468 pte = pde & ~0x003ff000; /* align to 4MB */
469 page_size = 4096 * 1024;
471 /* page directory entry */
472 pte_ptr = phys_ram_base +
473 (((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask);
474 pte = ldl_raw(pte_ptr);
475 if (!(pte & PG_PRESENT_MASK))
480 pte = pte & env->a20_mask;
481 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
482 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
487 #if defined(USE_CODE_COPY)
500 uint8_t fpregs1[8 * 10];
503 void restore_native_fp_state(CPUState *env)
506 struct fpstate fp1, *fp = &fp1;
508 fp->fpuc = env->fpuc;
509 fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
511 for (i=7; i>=0; i--) {
513 if (env->fptags[i]) {
516 /* the FPU automatically computes it */
521 for(i = 0;i < 8; i++) {
522 memcpy(&fp->fpregs1[i * 10], &env->fpregs[j], 10);
525 asm volatile ("frstor %0" : "=m" (*fp));
526 env->native_fp_regs = 1;
529 void save_native_fp_state(CPUState *env)
533 struct fpstate fp1, *fp = &fp1;
535 asm volatile ("fsave %0" : : "m" (*fp));
536 env->fpuc = fp->fpuc;
537 env->fpstt = (fp->fpus >> 11) & 7;
538 env->fpus = fp->fpus & ~0x3800;
540 for(i = 0;i < 8; i++) {
541 env->fptags[i] = ((fptag & 3) == 3);
545 for(i = 0;i < 8; i++) {
546 memcpy(&env->fpregs[j], &fp->fpregs1[i * 10], 10);
549 /* we must restore the default rounding state */
550 /* XXX: we do not restore the exception state */
551 fpuc = 0x037f | (env->fpuc & (3 << 10));
552 asm volatile("fldcw %0" : : "m" (fpuc));
553 env->native_fp_regs = 0;