2 * i386 helpers (without register variable usage)
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include "qemu-common.h"
37 static int cpu_x86_register (CPUX86State *env, const char *cpu_model);
39 static void add_flagname_to_bitmaps(char *flagname, uint32_t *features,
40 uint32_t *ext_features,
41 uint32_t *ext2_features,
42 uint32_t *ext3_features)
45 /* feature flags taken from "Intel Processor Identification and the CPUID
46 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
47 * about feature names, the Linux name is used. */
48 static const char *feature_name[] = {
49 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
50 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
51 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, NULL, "ds" /* Intel dts */, "acpi", "mmx",
52 "fxsr", "sse", "sse2", "ss", "ht" /* Intel htt */, "tm", "ia64", "pbe",
54 static const char *ext_feature_name[] = {
55 "pni" /* Intel,AMD sse3 */, NULL, NULL, "monitor", "ds_cpl", "vmx", NULL /* Linux smx */, "est",
56 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
57 NULL, NULL, "dca", NULL, NULL, NULL, NULL, "popcnt",
58 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
60 static const char *ext2_feature_name[] = {
61 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
62 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", "mttr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL, NULL /* Linux mp */, "nx" /* Intel xd */, NULL, "mmxext", "mmx",
64 "fxsr", "fxsr_opt" /* AMD ffxsr */, "pdpe1gb" /* AMD Page1GB */, "rdtscp", NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow",
66 static const char *ext3_feature_name[] = {
67 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
68 "3dnowprefetch", "osvw", NULL /* Linux ibs */, NULL, "skinit", "wdt", NULL, NULL,
69 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
70 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
73 for ( i = 0 ; i < 32 ; i++ )
74 if (feature_name[i] && !strcmp (flagname, feature_name[i])) {
78 for ( i = 0 ; i < 32 ; i++ )
79 if (ext_feature_name[i] && !strcmp (flagname, ext_feature_name[i])) {
80 *ext_features |= 1 << i;
83 for ( i = 0 ; i < 32 ; i++ )
84 if (ext2_feature_name[i] && !strcmp (flagname, ext2_feature_name[i])) {
85 *ext2_features |= 1 << i;
88 for ( i = 0 ; i < 32 ; i++ )
89 if (ext3_feature_name[i] && !strcmp (flagname, ext3_feature_name[i])) {
90 *ext3_features |= 1 << i;
93 fprintf(stderr, "CPU feature %s not found\n", flagname);
96 CPUX86State *cpu_x86_init(const char *cpu_model)
101 env = qemu_mallocz(sizeof(CPUX86State));
105 env->cpu_model_str = cpu_model;
107 /* init various static tables */
110 optimize_flags_init();
112 if (cpu_x86_register(env, cpu_model) < 0) {
125 typedef struct x86_def_t {
128 uint32_t vendor1, vendor2, vendor3;
132 uint32_t features, ext_features, ext2_features, ext3_features;
137 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
138 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
139 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX)
140 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
141 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
142 CPUID_PSE36 | CPUID_FXSR)
143 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
144 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
145 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
146 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
147 CPUID_PAE | CPUID_SEP | CPUID_APIC)
148 static x86_def_t x86_defs[] = {
153 .vendor1 = CPUID_VENDOR_AMD_1,
154 .vendor2 = CPUID_VENDOR_AMD_2,
155 .vendor3 = CPUID_VENDOR_AMD_3,
159 .features = PPRO_FEATURES |
160 /* these features are needed for Win64 and aren't fully implemented */
161 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
162 /* this feature is needed for Solaris and isn't fully implemented */
164 .ext_features = CPUID_EXT_SSE3,
165 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) |
166 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
167 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
168 .ext3_features = CPUID_EXT3_SVM,
169 .xlevel = 0x8000000A,
170 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
178 /* The original CPU also implements these features:
179 CPUID_VME, CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
180 CPUID_TM, CPUID_PBE */
181 .features = PPRO_FEATURES |
182 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
184 /* The original CPU also implements these ext features:
185 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
186 CPUID_EXT_TM2, CPUID_EXT_CX16, CPUID_EXT_XTPR, CPUID_EXT_PDCM */
187 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3,
188 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
189 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
190 .xlevel = 0x80000008,
191 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
200 .features = PPRO_FEATURES,
201 .ext_features = CPUID_EXT_SSE3,
203 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
211 /* The original CPU also implements these features:
212 CPUID_DTS, CPUID_ACPI, CPUID_SS, CPUID_HT,
213 CPUID_TM, CPUID_PBE */
214 .features = PPRO_FEATURES | CPUID_VME |
215 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA,
216 /* The original CPU also implements these ext features:
217 CPUID_EXT_VMX, CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_XTPR,
219 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
220 .ext2_features = CPUID_EXT2_NX,
221 .xlevel = 0x80000008,
222 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
230 .features = I486_FEATURES,
239 .features = PENTIUM_FEATURES,
248 .features = PENTIUM2_FEATURES,
257 .features = PENTIUM3_FEATURES,
263 .vendor1 = 0x68747541, /* "Auth" */
264 .vendor2 = 0x69746e65, /* "enti" */
265 .vendor3 = 0x444d4163, /* "cAMD" */
269 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
270 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
271 .xlevel = 0x80000008,
272 /* XXX: put another string ? */
273 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
277 /* original is on level 10 */
282 .features = PPRO_FEATURES |
283 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME,
284 /* Missing: CPUID_DTS | CPUID_ACPI | CPUID_SS |
285 * CPUID_HT | CPUID_TM | CPUID_PBE */
286 /* Some CPUs got no CPUID_SEP */
287 .ext_features = CPUID_EXT_MONITOR |
288 CPUID_EXT_SSE3 /* PNI */ | CPUID_EXT_SSSE3,
289 /* Missing: CPUID_EXT_DSCPL | CPUID_EXT_EST |
290 * CPUID_EXT_TM2 | CPUID_EXT_XTPR */
291 .ext2_features = (PPRO_FEATURES & 0x0183F3FF) | CPUID_EXT2_NX,
292 /* Missing: .ext3_features = CPUID_EXT3_LAHF_LM */
293 .xlevel = 0x8000000A,
294 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
298 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
303 char *s = strdup(cpu_model);
304 char *featurestr, *name = strtok(s, ",");
305 uint32_t plus_features = 0, plus_ext_features = 0, plus_ext2_features = 0, plus_ext3_features = 0;
306 uint32_t minus_features = 0, minus_ext_features = 0, minus_ext2_features = 0, minus_ext3_features = 0;
307 int family = -1, model = -1, stepping = -1;
310 for (i = 0; i < sizeof(x86_defs) / sizeof(x86_def_t); i++) {
311 if (strcmp(name, x86_defs[i].name) == 0) {
318 memcpy(x86_cpu_def, def, sizeof(*def));
320 featurestr = strtok(NULL, ",");
324 if (featurestr[0] == '+') {
325 add_flagname_to_bitmaps(featurestr + 1, &plus_features, &plus_ext_features, &plus_ext2_features, &plus_ext3_features);
326 } else if (featurestr[0] == '-') {
327 add_flagname_to_bitmaps(featurestr + 1, &minus_features, &minus_ext_features, &minus_ext2_features, &minus_ext3_features);
328 } else if ((val = strchr(featurestr, '='))) {
330 if (!strcmp(featurestr, "family")) {
332 family = strtol(val, &err, 10);
333 if (!*val || *err || family < 0) {
334 fprintf(stderr, "bad numerical value %s\n", val);
337 x86_cpu_def->family = family;
338 } else if (!strcmp(featurestr, "model")) {
340 model = strtol(val, &err, 10);
341 if (!*val || *err || model < 0 || model > 0xff) {
342 fprintf(stderr, "bad numerical value %s\n", val);
345 x86_cpu_def->model = model;
346 } else if (!strcmp(featurestr, "stepping")) {
348 stepping = strtol(val, &err, 10);
349 if (!*val || *err || stepping < 0 || stepping > 0xf) {
350 fprintf(stderr, "bad numerical value %s\n", val);
353 x86_cpu_def->stepping = stepping;
354 } else if (!strcmp(featurestr, "vendor")) {
355 if (strlen(val) != 12) {
356 fprintf(stderr, "vendor string must be 12 chars long\n");
359 x86_cpu_def->vendor1 = 0;
360 x86_cpu_def->vendor2 = 0;
361 x86_cpu_def->vendor3 = 0;
362 for(i = 0; i < 4; i++) {
363 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
364 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
365 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
367 } else if (!strcmp(featurestr, "model_id")) {
368 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
371 fprintf(stderr, "unrecognized feature %s\n", featurestr);
375 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
378 featurestr = strtok(NULL, ",");
380 x86_cpu_def->features |= plus_features;
381 x86_cpu_def->ext_features |= plus_ext_features;
382 x86_cpu_def->ext2_features |= plus_ext2_features;
383 x86_cpu_def->ext3_features |= plus_ext3_features;
384 x86_cpu_def->features &= ~minus_features;
385 x86_cpu_def->ext_features &= ~minus_ext_features;
386 x86_cpu_def->ext2_features &= ~minus_ext2_features;
387 x86_cpu_def->ext3_features &= ~minus_ext3_features;
396 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
400 for (i = 0; i < sizeof(x86_defs) / sizeof(x86_def_t); i++)
401 (*cpu_fprintf)(f, "x86 %16s\n", x86_defs[i].name);
404 static int cpu_x86_register (CPUX86State *env, const char *cpu_model)
406 x86_def_t def1, *def = &def1;
408 if (cpu_x86_find_by_name(def, cpu_model) < 0)
411 env->cpuid_vendor1 = def->vendor1;
412 env->cpuid_vendor2 = def->vendor2;
413 env->cpuid_vendor3 = def->vendor3;
415 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
416 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
417 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
419 env->cpuid_level = def->level;
420 if (def->family > 0x0f)
421 env->cpuid_version = 0xf00 | ((def->family - 0x0f) << 20);
423 env->cpuid_version = def->family << 8;
424 env->cpuid_version |= ((def->model & 0xf) << 4) | ((def->model >> 4) << 16);
425 env->cpuid_version |= def->stepping;
426 env->cpuid_features = def->features;
427 env->pat = 0x0007040600070406ULL;
428 env->cpuid_ext_features = def->ext_features;
429 env->cpuid_ext2_features = def->ext2_features;
430 env->cpuid_xlevel = def->xlevel;
431 env->cpuid_ext3_features = def->ext3_features;
433 const char *model_id = def->model_id;
437 len = strlen(model_id);
438 for(i = 0; i < 48; i++) {
442 c = (uint8_t)model_id[i];
443 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
449 /* NOTE: must be called outside the CPU execute loop */
450 void cpu_reset(CPUX86State *env)
454 memset(env, 0, offsetof(CPUX86State, breakpoints));
458 env->old_exception = -1;
460 /* init to reset state */
462 #ifdef CONFIG_SOFTMMU
463 env->hflags |= HF_SOFTMMU_MASK;
465 env->hflags2 |= HF2_GIF_MASK;
467 cpu_x86_update_cr0(env, 0x60000010);
468 env->a20_mask = ~0x0;
469 env->smbase = 0x30000;
471 env->idt.limit = 0xffff;
472 env->gdt.limit = 0xffff;
473 env->ldt.limit = 0xffff;
474 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
475 env->tr.limit = 0xffff;
476 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
478 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
479 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | DESC_R_MASK);
480 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
481 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
482 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
483 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
484 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
485 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
486 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
487 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
488 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
489 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK);
492 env->regs[R_EDX] = env->cpuid_version;
497 for(i = 0;i < 8; i++)
504 void cpu_x86_close(CPUX86State *env)
509 /***********************************************************/
512 static const char *cc_op_str[] = {
567 void cpu_dump_state(CPUState *env, FILE *f,
568 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
573 static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
575 eflags = env->eflags;
577 if (env->hflags & HF_CS64_MASK) {
579 "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
580 "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
581 "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
582 "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
583 "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
601 eflags & DF_MASK ? 'D' : '-',
602 eflags & CC_O ? 'O' : '-',
603 eflags & CC_S ? 'S' : '-',
604 eflags & CC_Z ? 'Z' : '-',
605 eflags & CC_A ? 'A' : '-',
606 eflags & CC_P ? 'P' : '-',
607 eflags & CC_C ? 'C' : '-',
608 env->hflags & HF_CPL_MASK,
609 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
610 (int)(env->a20_mask >> 20) & 1,
611 (env->hflags >> HF_SMM_SHIFT) & 1,
616 cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
617 "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
618 "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
619 (uint32_t)env->regs[R_EAX],
620 (uint32_t)env->regs[R_EBX],
621 (uint32_t)env->regs[R_ECX],
622 (uint32_t)env->regs[R_EDX],
623 (uint32_t)env->regs[R_ESI],
624 (uint32_t)env->regs[R_EDI],
625 (uint32_t)env->regs[R_EBP],
626 (uint32_t)env->regs[R_ESP],
627 (uint32_t)env->eip, eflags,
628 eflags & DF_MASK ? 'D' : '-',
629 eflags & CC_O ? 'O' : '-',
630 eflags & CC_S ? 'S' : '-',
631 eflags & CC_Z ? 'Z' : '-',
632 eflags & CC_A ? 'A' : '-',
633 eflags & CC_P ? 'P' : '-',
634 eflags & CC_C ? 'C' : '-',
635 env->hflags & HF_CPL_MASK,
636 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
637 (int)(env->a20_mask >> 20) & 1,
638 (env->hflags >> HF_SMM_SHIFT) & 1,
643 if (env->hflags & HF_LMA_MASK) {
644 for(i = 0; i < 6; i++) {
645 SegmentCache *sc = &env->segs[i];
646 cpu_fprintf(f, "%s =%04x %016" PRIx64 " %08x %08x\n",
653 cpu_fprintf(f, "LDT=%04x %016" PRIx64 " %08x %08x\n",
658 cpu_fprintf(f, "TR =%04x %016" PRIx64 " %08x %08x\n",
663 cpu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
664 env->gdt.base, env->gdt.limit);
665 cpu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
666 env->idt.base, env->idt.limit);
667 cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
668 (uint32_t)env->cr[0],
671 (uint32_t)env->cr[4]);
675 for(i = 0; i < 6; i++) {
676 SegmentCache *sc = &env->segs[i];
677 cpu_fprintf(f, "%s =%04x %08x %08x %08x\n",
684 cpu_fprintf(f, "LDT=%04x %08x %08x %08x\n",
686 (uint32_t)env->ldt.base,
689 cpu_fprintf(f, "TR =%04x %08x %08x %08x\n",
691 (uint32_t)env->tr.base,
694 cpu_fprintf(f, "GDT= %08x %08x\n",
695 (uint32_t)env->gdt.base, env->gdt.limit);
696 cpu_fprintf(f, "IDT= %08x %08x\n",
697 (uint32_t)env->idt.base, env->idt.limit);
698 cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
699 (uint32_t)env->cr[0],
700 (uint32_t)env->cr[2],
701 (uint32_t)env->cr[3],
702 (uint32_t)env->cr[4]);
704 if (flags & X86_DUMP_CCOP) {
705 if ((unsigned)env->cc_op < CC_OP_NB)
706 snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);
708 snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
710 if (env->hflags & HF_CS64_MASK) {
711 cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
712 env->cc_src, env->cc_dst,
717 cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
718 (uint32_t)env->cc_src, (uint32_t)env->cc_dst,
722 if (flags & X86_DUMP_FPU) {
725 for(i = 0; i < 8; i++) {
726 fptag |= ((!env->fptags[i]) << i);
728 cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
730 (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
735 #if defined(USE_X86LDOUBLE)
743 tmp.d = env->fpregs[i].d;
744 cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
745 i, tmp.l.lower, tmp.l.upper);
747 cpu_fprintf(f, "FPR%d=%016" PRIx64,
748 i, env->fpregs[i].mmx.q);
751 cpu_fprintf(f, "\n");
755 if (env->hflags & HF_CS64_MASK)
760 cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",
762 env->xmm_regs[i].XMM_L(3),
763 env->xmm_regs[i].XMM_L(2),
764 env->xmm_regs[i].XMM_L(1),
765 env->xmm_regs[i].XMM_L(0));
767 cpu_fprintf(f, "\n");
774 /***********************************************************/
776 /* XXX: add PGE support */
778 void cpu_x86_set_a20(CPUX86State *env, int a20_state)
780 a20_state = (a20_state != 0);
781 if (a20_state != ((env->a20_mask >> 20) & 1)) {
782 #if defined(DEBUG_MMU)
783 printf("A20 update: a20=%d\n", a20_state);
785 /* if the cpu is currently executing code, we must unlink it and
786 all the potentially executing TB */
787 cpu_interrupt(env, CPU_INTERRUPT_EXITTB);
789 /* when a20 is changed, all the MMU mappings are invalid, so
790 we must flush everything */
792 env->a20_mask = (~0x100000) | (a20_state << 20);
796 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
800 #if defined(DEBUG_MMU)
801 printf("CR0 update: CR0=0x%08x\n", new_cr0);
803 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
804 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
809 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
810 (env->efer & MSR_EFER_LME)) {
811 /* enter in long mode */
812 /* XXX: generate an exception */
813 if (!(env->cr[4] & CR4_PAE_MASK))
815 env->efer |= MSR_EFER_LMA;
816 env->hflags |= HF_LMA_MASK;
817 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
818 (env->efer & MSR_EFER_LMA)) {
820 env->efer &= ~MSR_EFER_LMA;
821 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
822 env->eip &= 0xffffffff;
825 env->cr[0] = new_cr0 | CR0_ET_MASK;
827 /* update PE flag in hidden flags */
828 pe_state = (env->cr[0] & CR0_PE_MASK);
829 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
830 /* ensure that ADDSEG is always set in real mode */
831 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
832 /* update FPU flags */
833 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
834 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
837 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
839 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
841 env->cr[3] = new_cr3;
842 if (env->cr[0] & CR0_PG_MASK) {
843 #if defined(DEBUG_MMU)
844 printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
850 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
852 #if defined(DEBUG_MMU)
853 printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
855 if ((new_cr4 & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK)) !=
856 (env->cr[4] & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK))) {
860 if (!(env->cpuid_features & CPUID_SSE))
861 new_cr4 &= ~CR4_OSFXSR_MASK;
862 if (new_cr4 & CR4_OSFXSR_MASK)
863 env->hflags |= HF_OSFXSR_MASK;
865 env->hflags &= ~HF_OSFXSR_MASK;
867 env->cr[4] = new_cr4;
870 /* XXX: also flush 4MB pages */
871 void cpu_x86_flush_tlb(CPUX86State *env, target_ulong addr)
873 tlb_flush_page(env, addr);
876 #if defined(CONFIG_USER_ONLY)
878 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
879 int is_write, int mmu_idx, int is_softmmu)
881 /* user mode only emulation */
884 env->error_code = (is_write << PG_ERROR_W_BIT);
885 env->error_code |= PG_ERROR_U_MASK;
886 env->exception_index = EXCP0E_PAGE;
890 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
897 /* XXX: This value should match the one returned by CPUID
899 #if defined(USE_KQEMU)
900 #define PHYS_ADDR_MASK 0xfffff000LL
902 # if defined(TARGET_X86_64)
903 # define PHYS_ADDR_MASK 0xfffffff000LL
905 # define PHYS_ADDR_MASK 0xffffff000LL
910 -1 = cannot handle fault
911 0 = nothing more to do
912 1 = generate PF fault
913 2 = soft MMU activation required for this block
915 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
916 int is_write1, int mmu_idx, int is_softmmu)
919 target_ulong pde_addr, pte_addr;
920 int error_code, is_dirty, prot, page_size, ret, is_write, is_user;
921 target_phys_addr_t paddr;
922 uint32_t page_offset;
923 target_ulong vaddr, virt_addr;
925 is_user = mmu_idx == MMU_USER_IDX;
926 #if defined(DEBUG_MMU)
927 printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
928 addr, is_write1, is_user, env->eip);
930 is_write = is_write1 & 1;
932 if (!(env->cr[0] & CR0_PG_MASK)) {
934 virt_addr = addr & TARGET_PAGE_MASK;
935 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
940 if (env->cr[4] & CR4_PAE_MASK) {
942 target_ulong pdpe_addr;
945 if (env->hflags & HF_LMA_MASK) {
946 uint64_t pml4e_addr, pml4e;
949 /* test virtual address sign extension */
950 sext = (int64_t)addr >> 47;
951 if (sext != 0 && sext != -1) {
953 env->exception_index = EXCP0D_GPF;
957 pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
959 pml4e = ldq_phys(pml4e_addr);
960 if (!(pml4e & PG_PRESENT_MASK)) {
964 if (!(env->efer & MSR_EFER_NXE) && (pml4e & PG_NX_MASK)) {
965 error_code = PG_ERROR_RSVD_MASK;
968 if (!(pml4e & PG_ACCESSED_MASK)) {
969 pml4e |= PG_ACCESSED_MASK;
970 stl_phys_notdirty(pml4e_addr, pml4e);
972 ptep = pml4e ^ PG_NX_MASK;
973 pdpe_addr = ((pml4e & PHYS_ADDR_MASK) + (((addr >> 30) & 0x1ff) << 3)) &
975 pdpe = ldq_phys(pdpe_addr);
976 if (!(pdpe & PG_PRESENT_MASK)) {
980 if (!(env->efer & MSR_EFER_NXE) && (pdpe & PG_NX_MASK)) {
981 error_code = PG_ERROR_RSVD_MASK;
984 ptep &= pdpe ^ PG_NX_MASK;
985 if (!(pdpe & PG_ACCESSED_MASK)) {
986 pdpe |= PG_ACCESSED_MASK;
987 stl_phys_notdirty(pdpe_addr, pdpe);
992 /* XXX: load them when cr3 is loaded ? */
993 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
995 pdpe = ldq_phys(pdpe_addr);
996 if (!(pdpe & PG_PRESENT_MASK)) {
1000 ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
1003 pde_addr = ((pdpe & PHYS_ADDR_MASK) + (((addr >> 21) & 0x1ff) << 3)) &
1005 pde = ldq_phys(pde_addr);
1006 if (!(pde & PG_PRESENT_MASK)) {
1010 if (!(env->efer & MSR_EFER_NXE) && (pde & PG_NX_MASK)) {
1011 error_code = PG_ERROR_RSVD_MASK;
1014 ptep &= pde ^ PG_NX_MASK;
1015 if (pde & PG_PSE_MASK) {
1017 page_size = 2048 * 1024;
1019 if ((ptep & PG_NX_MASK) && is_write1 == 2)
1020 goto do_fault_protect;
1022 if (!(ptep & PG_USER_MASK))
1023 goto do_fault_protect;
1024 if (is_write && !(ptep & PG_RW_MASK))
1025 goto do_fault_protect;
1027 if ((env->cr[0] & CR0_WP_MASK) &&
1028 is_write && !(ptep & PG_RW_MASK))
1029 goto do_fault_protect;
1031 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
1032 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
1033 pde |= PG_ACCESSED_MASK;
1035 pde |= PG_DIRTY_MASK;
1036 stl_phys_notdirty(pde_addr, pde);
1038 /* align to page_size */
1039 pte = pde & ((PHYS_ADDR_MASK & ~(page_size - 1)) | 0xfff);
1040 virt_addr = addr & ~(page_size - 1);
1043 if (!(pde & PG_ACCESSED_MASK)) {
1044 pde |= PG_ACCESSED_MASK;
1045 stl_phys_notdirty(pde_addr, pde);
1047 pte_addr = ((pde & PHYS_ADDR_MASK) + (((addr >> 12) & 0x1ff) << 3)) &
1049 pte = ldq_phys(pte_addr);
1050 if (!(pte & PG_PRESENT_MASK)) {
1054 if (!(env->efer & MSR_EFER_NXE) && (pte & PG_NX_MASK)) {
1055 error_code = PG_ERROR_RSVD_MASK;
1058 /* combine pde and pte nx, user and rw protections */
1059 ptep &= pte ^ PG_NX_MASK;
1061 if ((ptep & PG_NX_MASK) && is_write1 == 2)
1062 goto do_fault_protect;
1064 if (!(ptep & PG_USER_MASK))
1065 goto do_fault_protect;
1066 if (is_write && !(ptep & PG_RW_MASK))
1067 goto do_fault_protect;
1069 if ((env->cr[0] & CR0_WP_MASK) &&
1070 is_write && !(ptep & PG_RW_MASK))
1071 goto do_fault_protect;
1073 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
1074 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
1075 pte |= PG_ACCESSED_MASK;
1077 pte |= PG_DIRTY_MASK;
1078 stl_phys_notdirty(pte_addr, pte);
1081 virt_addr = addr & ~0xfff;
1082 pte = pte & (PHYS_ADDR_MASK | 0xfff);
1087 /* page directory entry */
1088 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
1090 pde = ldl_phys(pde_addr);
1091 if (!(pde & PG_PRESENT_MASK)) {
1095 /* if PSE bit is set, then we use a 4MB page */
1096 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
1097 page_size = 4096 * 1024;
1099 if (!(pde & PG_USER_MASK))
1100 goto do_fault_protect;
1101 if (is_write && !(pde & PG_RW_MASK))
1102 goto do_fault_protect;
1104 if ((env->cr[0] & CR0_WP_MASK) &&
1105 is_write && !(pde & PG_RW_MASK))
1106 goto do_fault_protect;
1108 is_dirty = is_write && !(pde & PG_DIRTY_MASK);
1109 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
1110 pde |= PG_ACCESSED_MASK;
1112 pde |= PG_DIRTY_MASK;
1113 stl_phys_notdirty(pde_addr, pde);
1116 pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
1118 virt_addr = addr & ~(page_size - 1);
1120 if (!(pde & PG_ACCESSED_MASK)) {
1121 pde |= PG_ACCESSED_MASK;
1122 stl_phys_notdirty(pde_addr, pde);
1125 /* page directory entry */
1126 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) &
1128 pte = ldl_phys(pte_addr);
1129 if (!(pte & PG_PRESENT_MASK)) {
1133 /* combine pde and pte user and rw protections */
1136 if (!(ptep & PG_USER_MASK))
1137 goto do_fault_protect;
1138 if (is_write && !(ptep & PG_RW_MASK))
1139 goto do_fault_protect;
1141 if ((env->cr[0] & CR0_WP_MASK) &&
1142 is_write && !(ptep & PG_RW_MASK))
1143 goto do_fault_protect;
1145 is_dirty = is_write && !(pte & PG_DIRTY_MASK);
1146 if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
1147 pte |= PG_ACCESSED_MASK;
1149 pte |= PG_DIRTY_MASK;
1150 stl_phys_notdirty(pte_addr, pte);
1153 virt_addr = addr & ~0xfff;
1156 /* the page can be put in the TLB */
1158 if (!(ptep & PG_NX_MASK))
1160 if (pte & PG_DIRTY_MASK) {
1161 /* only set write access if already dirty... otherwise wait
1164 if (ptep & PG_RW_MASK)
1167 if (!(env->cr[0] & CR0_WP_MASK) ||
1168 (ptep & PG_RW_MASK))
1173 pte = pte & env->a20_mask;
1175 /* Even if 4MB pages, we map only one 4KB page in the cache to
1176 avoid filling it too fast */
1177 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1178 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1179 vaddr = virt_addr + page_offset;
1181 ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
1184 error_code = PG_ERROR_P_MASK;
1186 error_code |= (is_write << PG_ERROR_W_BIT);
1188 error_code |= PG_ERROR_U_MASK;
1189 if (is_write1 == 2 &&
1190 (env->efer & MSR_EFER_NXE) &&
1191 (env->cr[4] & CR4_PAE_MASK))
1192 error_code |= PG_ERROR_I_D_MASK;
1193 if (env->intercept_exceptions & (1 << EXCP0E_PAGE)) {
1194 /* cr2 is not modified in case of exceptions */
1195 stq_phys(env->vm_vmcb + offsetof(struct vmcb, control.exit_info_2),
1200 env->error_code = error_code;
1201 env->exception_index = EXCP0E_PAGE;
1205 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
1207 target_ulong pde_addr, pte_addr;
1209 target_phys_addr_t paddr;
1210 uint32_t page_offset;
1213 if (env->cr[4] & CR4_PAE_MASK) {
1214 target_ulong pdpe_addr;
1217 #ifdef TARGET_X86_64
1218 if (env->hflags & HF_LMA_MASK) {
1219 uint64_t pml4e_addr, pml4e;
1222 /* test virtual address sign extension */
1223 sext = (int64_t)addr >> 47;
1224 if (sext != 0 && sext != -1)
1227 pml4e_addr = ((env->cr[3] & ~0xfff) + (((addr >> 39) & 0x1ff) << 3)) &
1229 pml4e = ldq_phys(pml4e_addr);
1230 if (!(pml4e & PG_PRESENT_MASK))
1233 pdpe_addr = ((pml4e & ~0xfff) + (((addr >> 30) & 0x1ff) << 3)) &
1235 pdpe = ldq_phys(pdpe_addr);
1236 if (!(pdpe & PG_PRESENT_MASK))
1241 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
1243 pdpe = ldq_phys(pdpe_addr);
1244 if (!(pdpe & PG_PRESENT_MASK))
1248 pde_addr = ((pdpe & ~0xfff) + (((addr >> 21) & 0x1ff) << 3)) &
1250 pde = ldq_phys(pde_addr);
1251 if (!(pde & PG_PRESENT_MASK)) {
1254 if (pde & PG_PSE_MASK) {
1256 page_size = 2048 * 1024;
1257 pte = pde & ~( (page_size - 1) & ~0xfff); /* align to page_size */
1260 pte_addr = ((pde & ~0xfff) + (((addr >> 12) & 0x1ff) << 3)) &
1263 pte = ldq_phys(pte_addr);
1265 if (!(pte & PG_PRESENT_MASK))
1270 if (!(env->cr[0] & CR0_PG_MASK)) {
1274 /* page directory entry */
1275 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask;
1276 pde = ldl_phys(pde_addr);
1277 if (!(pde & PG_PRESENT_MASK))
1279 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
1280 pte = pde & ~0x003ff000; /* align to 4MB */
1281 page_size = 4096 * 1024;
1283 /* page directory entry */
1284 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask;
1285 pte = ldl_phys(pte_addr);
1286 if (!(pte & PG_PRESENT_MASK))
1291 pte = pte & env->a20_mask;
1294 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
1295 paddr = (pte & TARGET_PAGE_MASK) + page_offset;
1298 #endif /* !CONFIG_USER_ONLY */
1300 static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
1301 uint32_t *ecx, uint32_t *edx)
1303 #if defined(CONFIG_KVM)
1307 asm volatile("cpuid"
1308 : "=a"(vec[0]), "=b"(vec[1]),
1309 "=c"(vec[2]), "=d"(vec[3])
1310 : "0"(function) : "cc");
1312 asm volatile("pusha \n\t"
1314 "mov %%eax, 0(%1) \n\t"
1315 "mov %%ebx, 4(%1) \n\t"
1316 "mov %%ecx, 8(%1) \n\t"
1317 "mov %%edx, 12(%1) \n\t"
1319 : : "a"(function), "S"(vec)
1334 void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
1335 uint32_t *eax, uint32_t *ebx,
1336 uint32_t *ecx, uint32_t *edx)
1338 /* test if maximum index reached */
1339 if (index & 0x80000000) {
1340 if (index > env->cpuid_xlevel)
1341 index = env->cpuid_level;
1343 if (index > env->cpuid_level)
1344 index = env->cpuid_level;
1349 *eax = env->cpuid_level;
1350 *ebx = env->cpuid_vendor1;
1351 *edx = env->cpuid_vendor2;
1352 *ecx = env->cpuid_vendor3;
1354 /* sysenter isn't supported on compatibility mode on AMD. and syscall
1355 * isn't supported in compatibility mode on Intel. so advertise the
1356 * actuall cpu, and say goodbye to migration between different vendors
1357 * is you use compatibility mode. */
1359 host_cpuid(0, NULL, ebx, ecx, edx);
1362 *eax = env->cpuid_version;
1363 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1364 *ecx = env->cpuid_ext_features;
1365 *edx = env->cpuid_features;
1367 /* "Hypervisor present" bit required for Microsoft SVVP */
1372 /* cache info: needed for Pentium Pro compatibility */
1379 /* cache info: needed for Core compatibility */
1381 case 0: /* L1 dcache info */
1387 case 1: /* L1 icache info */
1393 case 2: /* L2 cache info */
1399 default: /* end of info */
1409 /* mwait info: needed for Core compatibility */
1410 *eax = 0; /* Smallest monitor-line size in bytes */
1411 *ebx = 0; /* Largest monitor-line size in bytes */
1412 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1416 /* Thermal and Power Leaf */
1423 /* Direct Cache Access Information Leaf */
1424 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1430 /* Architectural Performance Monitoring Leaf */
1437 *eax = env->cpuid_xlevel;
1438 *ebx = env->cpuid_vendor1;
1439 *edx = env->cpuid_vendor2;
1440 *ecx = env->cpuid_vendor3;
1443 *eax = env->cpuid_features;
1445 *ecx = env->cpuid_ext3_features;
1446 *edx = env->cpuid_ext2_features;
1448 if (kvm_enabled()) {
1449 uint32_t h_eax, h_edx;
1451 host_cpuid(0x80000001, &h_eax, NULL, NULL, &h_edx);
1453 /* disable CPU features that the host does not support */
1456 if ((h_edx & 0x20000000) == 0 /* || !lm_capable_kernel */)
1457 *edx &= ~0x20000000;
1459 if ((h_edx & 0x00000800) == 0)
1460 *edx &= ~0x00000800;
1462 if ((h_edx & 0x00100000) == 0)
1463 *edx &= ~0x00100000;
1465 /* disable CPU features that KVM cannot support */
1470 *edx &= ~0xc0000000;
1476 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1477 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1478 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1479 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1482 /* cache info (L1 cache) */
1489 /* cache info (L2 cache) */
1496 /* virtual & phys address size in low 2 bytes. */
1497 /* XXX: This value must match the one used in the MMU code. */
1498 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1499 /* 64 bit processor */
1500 #if defined(USE_KQEMU)
1501 *eax = 0x00003020; /* 48 bits virtual, 32 bits physical */
1503 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1504 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1507 #if defined(USE_KQEMU)
1508 *eax = 0x00000020; /* 32 bits physical */
1510 if (env->cpuid_features & CPUID_PSE36)
1511 *eax = 0x00000024; /* 36 bits physical */
1513 *eax = 0x00000020; /* 32 bits physical */
1521 *eax = 0x00000001; /* SVM Revision */
1522 *ebx = 0x00000010; /* nr of ASIDs */
1524 *edx = 0; /* optional features */
1527 /* reserved values: zero */