2 * i386 virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define TARGET_LONG_BITS 32
52 /* segment descriptor fields */
53 #define DESC_G_MASK (1 << 23)
54 #define DESC_B_SHIFT 22
55 #define DESC_B_MASK (1 << DESC_B_SHIFT)
56 #define DESC_AVL_MASK (1 << 20)
57 #define DESC_P_MASK (1 << 15)
58 #define DESC_DPL_SHIFT 13
59 #define DESC_S_MASK (1 << 12)
60 #define DESC_TYPE_SHIFT 8
61 #define DESC_A_MASK (1 << 8)
63 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
64 #define DESC_C_MASK (1 << 10) /* code: conforming */
65 #define DESC_R_MASK (1 << 9) /* code: readable */
67 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
68 #define DESC_W_MASK (1 << 9) /* data: writable */
70 #define DESC_TSS_BUSY_MASK (1 << 9)
84 #define TF_MASK 0x00000100
85 #define IF_MASK 0x00000200
86 #define DF_MASK 0x00000400
87 #define IOPL_MASK 0x00003000
88 #define NT_MASK 0x00004000
89 #define RF_MASK 0x00010000
90 #define VM_MASK 0x00020000
91 #define AC_MASK 0x00040000
92 #define VIF_MASK 0x00080000
93 #define VIP_MASK 0x00100000
94 #define ID_MASK 0x00200000
96 /* hidden flags - used internally by qemu to represent additionnal cpu
97 states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
98 using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
101 #define HF_CPL_SHIFT 0
102 /* true if soft mmu is being used */
103 #define HF_SOFTMMU_SHIFT 2
104 /* true if hardware interrupts must be disabled for next instruction */
105 #define HF_INHIBIT_IRQ_SHIFT 3
106 /* 16 or 32 segments */
107 #define HF_CS32_SHIFT 4
108 #define HF_SS32_SHIFT 5
109 /* zero base for DS, ES and SS */
110 #define HF_ADDSEG_SHIFT 6
111 /* copy of CR0.PE (protected mode) */
112 #define HF_PE_SHIFT 7
113 #define HF_TF_SHIFT 8 /* must be same as eflags */
114 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
115 #define HF_VM_SHIFT 17 /* must be same as eflags */
117 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
118 #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
119 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
120 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
121 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
122 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
123 #define HF_PE_MASK (1 << HF_PE_SHIFT)
125 #define CR0_PE_MASK (1 << 0)
126 #define CR0_TS_MASK (1 << 3)
127 #define CR0_WP_MASK (1 << 16)
128 #define CR0_AM_MASK (1 << 18)
129 #define CR0_PG_MASK (1 << 31)
131 #define CR4_VME_MASK (1 << 0)
132 #define CR4_PVI_MASK (1 << 1)
133 #define CR4_TSD_MASK (1 << 2)
134 #define CR4_DE_MASK (1 << 3)
135 #define CR4_PSE_MASK (1 << 4)
137 #define PG_PRESENT_BIT 0
139 #define PG_USER_BIT 2
142 #define PG_ACCESSED_BIT 5
143 #define PG_DIRTY_BIT 6
145 #define PG_GLOBAL_BIT 8
147 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
148 #define PG_RW_MASK (1 << PG_RW_BIT)
149 #define PG_USER_MASK (1 << PG_USER_BIT)
150 #define PG_PWT_MASK (1 << PG_PWT_BIT)
151 #define PG_PCD_MASK (1 << PG_PCD_BIT)
152 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
153 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
154 #define PG_PSE_MASK (1 << PG_PSE_BIT)
155 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
157 #define PG_ERROR_W_BIT 1
159 #define PG_ERROR_P_MASK 0x01
160 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
161 #define PG_ERROR_U_MASK 0x04
162 #define PG_ERROR_RSVD_MASK 0x08
164 #define MSR_IA32_APICBASE 0x1b
165 #define MSR_IA32_APICBASE_BSP (1<<8)
166 #define MSR_IA32_APICBASE_ENABLE (1<<11)
167 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
169 #define MSR_IA32_SYSENTER_CS 0x174
170 #define MSR_IA32_SYSENTER_ESP 0x175
171 #define MSR_IA32_SYSENTER_EIP 0x176
173 #define EXCP00_DIVZ 0
174 #define EXCP01_SSTP 1
176 #define EXCP03_INT3 3
177 #define EXCP04_INTO 4
178 #define EXCP05_BOUND 5
179 #define EXCP06_ILLOP 6
180 #define EXCP07_PREX 7
181 #define EXCP08_DBLE 8
182 #define EXCP09_XERR 9
183 #define EXCP0A_TSS 10
184 #define EXCP0B_NOSEG 11
185 #define EXCP0C_STACK 12
186 #define EXCP0D_GPF 13
187 #define EXCP0E_PAGE 14
188 #define EXCP10_COPR 16
189 #define EXCP11_ALGN 17
190 #define EXCP12_MCHK 18
193 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
194 CC_OP_EFLAGS, /* all cc are explicitely computed, CC_SRC = flags */
196 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
200 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
204 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
208 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
212 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
216 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
220 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
224 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
228 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
232 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
240 #define USE_X86LDOUBLE
243 #ifdef USE_X86LDOUBLE
244 typedef long double CPU86_LDouble;
246 typedef double CPU86_LDouble;
249 typedef struct SegmentCache {
256 typedef struct CPUX86State {
257 /* standard registers */
260 uint32_t eflags; /* eflags register. During CPU emulation, CC
261 flags and DF are set to zero because they are
264 /* emulator internal eflags handling */
268 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
269 uint32_t hflags; /* hidden flags, see HF_xxx constants */
272 unsigned int fpstt; /* top of stack index */
275 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
276 CPU86_LDouble fpregs[8];
278 /* emulator internal variables */
288 SegmentCache segs[6]; /* selector values */
291 SegmentCache gdt; /* only base and limit are used */
292 SegmentCache idt; /* only base and limit are used */
294 /* sysenter registers */
295 uint32_t sysenter_cs;
296 uint32_t sysenter_esp;
297 uint32_t sysenter_eip;
299 /* exception/interrupt handling */
303 int exception_is_int;
304 int exception_next_eip;
305 struct TranslationBlock *current_tb; /* currently executing TB */
306 uint32_t cr[5]; /* NOTE: cr1 is unused */
307 uint32_t dr[8]; /* debug registers */
308 int interrupt_request;
309 int user_mode_only; /* user mode only simulation */
311 /* soft mmu support */
312 /* 0 = kernel, 1 = user */
313 CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
314 CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
316 /* ice debug support */
317 uint32_t breakpoints[MAX_BREAKPOINTS];
319 int singlestep_enabled;
326 void cpu_x86_outb(CPUX86State *env, int addr, int val);
327 void cpu_x86_outw(CPUX86State *env, int addr, int val);
328 void cpu_x86_outl(CPUX86State *env, int addr, int val);
329 int cpu_x86_inb(CPUX86State *env, int addr);
330 int cpu_x86_inw(CPUX86State *env, int addr);
331 int cpu_x86_inl(CPUX86State *env, int addr);
334 CPUX86State *cpu_x86_init(void);
335 int cpu_x86_exec(CPUX86State *s);
336 void cpu_x86_close(CPUX86State *s);
337 int cpu_x86_get_pic_interrupt(CPUX86State *s);
339 /* this function must always be used to load data in the segment
340 cache: it synchronizes the hflags with the segment cache values */
341 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
342 int seg_reg, unsigned int selector,
343 uint8_t *base, unsigned int limit,
347 unsigned int new_hflags;
349 sc = &env->segs[seg_reg];
350 sc->selector = selector;
355 /* update the hidden flags */
356 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
357 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
358 new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
359 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
360 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
361 /* XXX: try to avoid this test. The problem comes from the
362 fact that is real mode or vm86 mode we only modify the
363 'base' and 'selector' fields of the segment cache to go
364 faster. A solution may be to force addseg to one in
366 new_hflags |= HF_ADDSEG_MASK;
368 new_hflags |= (((unsigned long)env->segs[R_DS].base |
369 (unsigned long)env->segs[R_ES].base |
370 (unsigned long)env->segs[R_SS].base) != 0) <<
373 env->hflags = (env->hflags &
374 ~(HF_CS32_MASK | HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
377 /* wrapper, just in case memory mappings must be changed */
378 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
381 s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
383 #error HF_CPL_MASK is hardcoded
387 /* the following helpers are only usable in user mode simulation as
388 they can trigger unexpected exceptions */
389 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
390 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
391 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
393 /* you can call this signal handler from your SIGBUS and SIGSEGV
394 signal handlers to inform the virtual CPU of exceptions. non zero
395 is returned if the signal was handled by the virtual CPU. */
397 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
401 void cpu_x86_init_mmu(CPUX86State *env);
402 extern int a20_enabled;
404 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
407 #define X86_DUMP_FPU 0x0001 /* dump FPU state too */
408 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
409 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
411 #define TARGET_PAGE_BITS 12
414 #endif /* CPU_I386_H */