2 * CRIS emulation for qemu: main translation routines.
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
40 #include "crisv32-decode.h"
41 #include "qemu-common.h"
58 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59 #define BUG_ON(x) ({if (x) BUG();})
63 /* Used by the decoder. */
64 #define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
67 #define CC_MASK_NZ 0xc
68 #define CC_MASK_NZV 0xe
69 #define CC_MASK_NZVC 0xf
70 #define CC_MASK_RNZV 0x10e
86 /* This is the state at translation time. */
87 typedef struct DisasContext {
96 unsigned int zsize, zzsize;
104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
108 int clear_x; /* Clear x after this insn? */
110 int user; /* user or kernel mode. */
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
123 void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124 static void gen_BUG(DisasContext *dc, char *file, int line)
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
130 cris_prepare_jmp (dc, 0x70000000 + line);
133 const char *regnames[] =
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
140 const char *pregnames[] =
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
148 /* We need this table to handle preg-moves with implicit width. */
160 #define t_gen_mov_TN_env(tn, member) \
161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
162 #define t_gen_mov_env_TN(member, tn) \
163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
165 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
171 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
178 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
182 tcg_gen_ld_tl(tn, cpu_env, offset);
184 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
188 tcg_gen_st_tl(tn, cpu_env, offset);
191 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
194 fprintf(stderr, "wrong register read $p%d\n", r);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
208 tcg_gen_mov_tl(tn, cpu_PR[r]);
210 static inline void t_gen_mov_preg_TN(int r, TCGv tn)
213 fprintf(stderr, "wrong register write $p%d\n", r);
214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
220 tcg_gen_helper_0_0(helper_tlb_flush);
222 tcg_gen_mov_tl(cpu_PR[r], tn);
226 static inline void t_gen_raise_exception(uint32_t index)
228 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
231 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
238 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
244 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
251 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
257 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
264 tcg_gen_brcond_tl(TCG_COND_LEU, b, tcg_const_tl(31), l1);
265 /* Clear dst if shift operands were to large. */
266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
270 /* 64-bit signed mul, lower result in d and upper in d2. */
271 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
290 /* 64-bit unsigned muls, lower result in d and upper in d2. */
291 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
310 /* 32bit branch-free binary search for counting leading zeros. */
311 static void t_gen_lz_i32(TCGv d, TCGv x)
315 y = tcg_temp_new(TCG_TYPE_I32);
316 m = tcg_temp_new(TCG_TYPE_I32);
317 n = tcg_temp_new(TCG_TYPE_I32);
320 tcg_gen_shri_i32(y, x, 16);
321 tcg_gen_neg_i32(y, y);
323 /* m = (y >> 16) & 16 */
324 tcg_gen_sari_i32(m, y, 16);
325 tcg_gen_andi_i32(m, m, 16);
328 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
330 tcg_gen_shr_i32(x, x, m);
333 tcg_gen_subi_i32(y, x, 0x100);
334 /* m = (y >> 16) & 8 */
335 tcg_gen_sari_i32(m, y, 16);
336 tcg_gen_andi_i32(m, m, 8);
338 tcg_gen_add_i32(n, n, m);
340 tcg_gen_shl_i32(x, x, m);
343 tcg_gen_subi_i32(y, x, 0x1000);
344 /* m = (y >> 16) & 4 */
345 tcg_gen_sari_i32(m, y, 16);
346 tcg_gen_andi_i32(m, m, 4);
348 tcg_gen_add_i32(n, n, m);
350 tcg_gen_shl_i32(x, x, m);
353 tcg_gen_subi_i32(y, x, 0x4000);
354 /* m = (y >> 16) & 2 */
355 tcg_gen_sari_i32(m, y, 16);
356 tcg_gen_andi_i32(m, m, 2);
358 tcg_gen_add_i32(n, n, m);
360 tcg_gen_shl_i32(x, x, m);
363 tcg_gen_shri_i32(y, x, 14);
364 /* m = y & ~(y >> 1) */
365 tcg_gen_sari_i32(m, y, 1);
366 tcg_gen_xori_i32(m, m, 0xffffffff);
367 tcg_gen_and_i32(m, m, y);
370 tcg_gen_addi_i32(d, n, 2);
371 tcg_gen_sub_i32(d, d, m);
373 tcg_gen_discard_i32(y);
374 tcg_gen_discard_i32(m);
375 tcg_gen_discard_i32(n);
378 static void t_gen_btst(TCGv d, TCGv s)
385 The N flag is set according to the selected bit in the dest reg.
386 The Z flag is set if the selected bit and all bits to the right are
388 The X flag is cleared.
389 Other flags are left untouched.
390 The destination reg is not affected.
392 unsigned int fz, sbit, bset, mask, masked_t0;
395 bset = !!(T0 & (1 << sbit));
396 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
397 masked_t0 = T0 & mask;
398 fz = !(masked_t0 | bset);
400 // Clear the X, N and Z flags.
401 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
402 // Set the N and Z flags accordingly.
403 T0 |= (bset << 3) | (fz << 2);
406 l1 = gen_new_label();
407 sbit = tcg_temp_new(TCG_TYPE_TL);
408 bset = tcg_temp_new(TCG_TYPE_TL);
410 /* Compute bset and sbit. */
411 tcg_gen_andi_tl(sbit, s, 31);
412 tcg_gen_shl_tl(s, tcg_const_tl(1), sbit);
413 tcg_gen_and_tl(bset, d, s);
414 tcg_gen_shr_tl(bset, bset, sbit);
415 /* Displace to N_FLAG. */
416 tcg_gen_shli_tl(bset, bset, 3);
418 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
419 tcg_gen_subi_tl(sbit, sbit, 1);
420 tcg_gen_and_tl(sbit, d, sbit);
422 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
423 /* or in the N_FLAG. */
424 tcg_gen_or_tl(d, d, bset);
425 tcg_gen_brcond_tl(TCG_COND_NE, sbit, tcg_const_tl(0), l1);
426 /* or in the Z_FLAG. */
427 tcg_gen_ori_tl(d, d, Z_FLAG);
430 tcg_gen_discard_tl(sbit);
431 tcg_gen_discard_tl(bset);
434 static void t_gen_cris_dstep(TCGv d, TCGv s)
438 l1 = gen_new_label();
445 tcg_gen_shli_tl(d, d, 1);
446 tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
447 tcg_gen_sub_tl(d, d, s);
451 /* Extended arithmetics on CRIS. */
452 static inline void t_gen_add_flag(TCGv d, int flag)
456 c = tcg_temp_new(TCG_TYPE_TL);
457 t_gen_mov_TN_preg(c, PR_CCS);
458 /* Propagate carry into d. */
459 tcg_gen_andi_tl(c, c, 1 << flag);
461 tcg_gen_shri_tl(c, c, flag);
462 tcg_gen_add_tl(d, d, c);
463 tcg_gen_discard_tl(c);
466 static inline void t_gen_addx_carry(TCGv d)
470 x = tcg_temp_new(TCG_TYPE_TL);
471 c = tcg_temp_new(TCG_TYPE_TL);
472 t_gen_mov_TN_preg(x, PR_CCS);
473 tcg_gen_mov_tl(c, x);
475 /* Propagate carry into d if X is set. Branch free. */
476 tcg_gen_andi_tl(c, c, C_FLAG);
477 tcg_gen_andi_tl(x, x, X_FLAG);
478 tcg_gen_shri_tl(x, x, 4);
480 tcg_gen_and_tl(x, x, c);
481 tcg_gen_add_tl(d, d, x);
482 tcg_gen_discard_tl(x);
483 tcg_gen_discard_tl(c);
486 static inline void t_gen_subx_carry(TCGv d)
490 x = tcg_temp_new(TCG_TYPE_TL);
491 c = tcg_temp_new(TCG_TYPE_TL);
492 t_gen_mov_TN_preg(x, PR_CCS);
493 tcg_gen_mov_tl(c, x);
495 /* Propagate carry into d if X is set. Branch free. */
496 tcg_gen_andi_tl(c, c, C_FLAG);
497 tcg_gen_andi_tl(x, x, X_FLAG);
498 tcg_gen_shri_tl(x, x, 4);
500 tcg_gen_and_tl(x, x, c);
501 tcg_gen_sub_tl(d, d, x);
502 tcg_gen_discard_tl(x);
503 tcg_gen_discard_tl(c);
506 /* Swap the two bytes within each half word of the s operand.
507 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
508 static inline void t_gen_swapb(TCGv d, TCGv s)
512 t = tcg_temp_new(TCG_TYPE_TL);
513 org_s = tcg_temp_new(TCG_TYPE_TL);
515 /* d and s may refer to the same object. */
516 tcg_gen_mov_tl(org_s, s);
517 tcg_gen_shli_tl(t, org_s, 8);
518 tcg_gen_andi_tl(d, t, 0xff00ff00);
519 tcg_gen_shri_tl(t, org_s, 8);
520 tcg_gen_andi_tl(t, t, 0x00ff00ff);
521 tcg_gen_or_tl(d, d, t);
522 tcg_gen_discard_tl(t);
523 tcg_gen_discard_tl(org_s);
526 /* Swap the halfwords of the s operand. */
527 static inline void t_gen_swapw(TCGv d, TCGv s)
530 /* d and s refer the same object. */
531 t = tcg_temp_new(TCG_TYPE_TL);
532 tcg_gen_mov_tl(t, s);
533 tcg_gen_shli_tl(d, t, 16);
534 tcg_gen_shri_tl(t, t, 16);
535 tcg_gen_or_tl(d, d, t);
536 tcg_gen_discard_tl(t);
539 /* Reverse the within each byte.
540 T0 = (((T0 << 7) & 0x80808080) |
541 ((T0 << 5) & 0x40404040) |
542 ((T0 << 3) & 0x20202020) |
543 ((T0 << 1) & 0x10101010) |
544 ((T0 >> 1) & 0x08080808) |
545 ((T0 >> 3) & 0x04040404) |
546 ((T0 >> 5) & 0x02020202) |
547 ((T0 >> 7) & 0x01010101));
549 static inline void t_gen_swapr(TCGv d, TCGv s)
552 int shift; /* LSL when positive, LSR when negative. */
567 /* d and s refer the same object. */
568 t = tcg_temp_new(TCG_TYPE_TL);
569 org_s = tcg_temp_new(TCG_TYPE_TL);
570 tcg_gen_mov_tl(org_s, s);
572 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
573 tcg_gen_andi_tl(d, t, bitrev[0].mask);
574 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
575 if (bitrev[i].shift >= 0) {
576 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
578 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
580 tcg_gen_andi_tl(t, t, bitrev[i].mask);
581 tcg_gen_or_tl(d, d, t);
583 tcg_gen_discard_tl(t);
584 tcg_gen_discard_tl(org_s);
587 static void t_gen_cc_jmp(target_ulong pc_true, target_ulong pc_false)
592 l1 = gen_new_label();
593 btaken = tcg_temp_new(TCG_TYPE_TL);
595 /* Conditional jmp. */
596 t_gen_mov_TN_env(btaken, btaken);
597 tcg_gen_movi_tl(env_pc, pc_false);
598 tcg_gen_brcond_tl(TCG_COND_EQ, btaken, tcg_const_tl(0), l1);
599 tcg_gen_movi_tl(env_pc, pc_true);
602 tcg_gen_discard_tl(btaken);
605 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
607 TranslationBlock *tb;
609 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
611 tcg_gen_movi_tl(env_pc, dest);
612 tcg_gen_exit_tb((long)tb + n);
614 tcg_gen_mov_tl(env_pc, cpu_T[0]);
619 /* Sign extend at translation time. */
620 static int sign_extend(unsigned int val, unsigned int width)
632 static inline void cris_clear_x_flag(DisasContext *dc)
635 || (dc->flagx_live && dc->flags_x)
636 || dc->cc_op != CC_OP_FLAGS)
637 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
642 static void cris_evaluate_flags(DisasContext *dc)
644 if (!dc->flags_live) {
645 tcg_gen_movi_tl(cc_op, dc->cc_op);
646 tcg_gen_movi_tl(cc_size, dc->cc_size);
647 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
652 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
655 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
658 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
664 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
667 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
670 tcg_gen_helper_0_0(helper_evaluate_flags);
682 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
685 tcg_gen_helper_0_0(helper_evaluate_flags);
695 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
699 /* Check if we need to evaluate the condition codes due to
701 ovl = (dc->cc_mask ^ mask) & ~mask;
703 /* TODO: optimize this case. It trigs all the time. */
704 cris_evaluate_flags (dc);
715 static void cris_update_cc_op(DisasContext *dc, int op, int size)
722 /* op is the operation.
723 T0, T1 are the operands.
724 dst is the destination reg.
726 static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
730 cris_update_cc_op(dc, op, size);
731 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
733 /* FIXME: This shouldn't be needed. But we don't pass the
734 tests without it. Investigate. */
735 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
736 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
739 /* Emit the ALU insns. */
743 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
744 /* Extended arithmetics. */
745 t_gen_addx_carry(cpu_T[0]);
748 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
749 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
752 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
753 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
756 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
757 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
758 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
759 /* CRIS flag evaluation needs ~src. */
760 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
762 /* Extended arithmetics. */
763 t_gen_subx_carry(cpu_T[0]);
766 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
769 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
772 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
775 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
778 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
781 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
784 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
787 tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
788 /* Extended arithmetics. */
789 t_gen_subx_carry(cpu_T[0]);
792 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
795 t_gen_btst(cpu_T[0], cpu_T[1]);
801 mof = tcg_temp_new(TCG_TYPE_TL);
802 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
803 t_gen_mov_preg_TN(PR_MOF, mof);
804 tcg_gen_discard_tl(mof);
810 mof = tcg_temp_new(TCG_TYPE_TL);
811 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
812 t_gen_mov_preg_TN(PR_MOF, mof);
813 tcg_gen_discard_tl(mof);
817 t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
822 l1 = gen_new_label();
823 tcg_gen_brcond_tl(TCG_COND_LEU,
824 cpu_T[0], cpu_T[1], l1);
825 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
830 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
831 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
832 /* CRIS flag evaluation needs ~src. */
833 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
834 /* CRIS flag evaluation needs ~src. */
835 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
837 /* Extended arithmetics. */
838 t_gen_subx_carry(cpu_T[0]);
842 fprintf (logfile, "illegal ALU op.\n");
848 tcg_gen_mov_tl(cc_src, cpu_T[1]);
851 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
853 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
858 t_gen_mov_reg_TN(rd, cpu_T[0]);
860 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
861 t_gen_mov_TN_reg(cpu_T[0], rd);
863 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
865 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
866 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
867 t_gen_mov_reg_TN(rd, cpu_T[0]);
868 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
872 tcg_gen_mov_tl(cc_result, cpu_T[0]);
875 /* TODO: Optimize this. */
877 cris_evaluate_flags(dc);
881 static int arith_cc(DisasContext *dc)
885 case CC_OP_ADD: return 1;
886 case CC_OP_SUB: return 1;
887 case CC_OP_LSL: return 1;
888 case CC_OP_LSR: return 1;
889 case CC_OP_ASR: return 1;
890 case CC_OP_CMP: return 1;
898 static void gen_tst_cc (DisasContext *dc, int cond)
902 /* TODO: optimize more condition codes. */
905 * If the flags are live, we've gotta look into the bits of CCS.
906 * Otherwise, if we just did an arithmetic operation we try to
907 * evaluate the condition code faster.
909 * When this function is done, T0 should be non-zero if the condition
912 arith_opt = arith_cc(dc) && !dc->flags_live;
916 /* If cc_result is zero, T0 should be
917 non-zero otherwise T0 should be zero. */
919 l1 = gen_new_label();
920 tcg_gen_movi_tl(cpu_T[0], 0);
921 tcg_gen_brcond_tl(TCG_COND_NE, cc_result,
922 tcg_const_tl(0), l1);
923 tcg_gen_movi_tl(cpu_T[0], 1);
927 cris_evaluate_flags(dc);
928 tcg_gen_andi_tl(cpu_T[0],
929 cpu_PR[PR_CCS], Z_FLAG);
934 tcg_gen_mov_tl(cpu_T[0], cc_result);
936 cris_evaluate_flags(dc);
937 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
939 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
943 cris_evaluate_flags(dc);
944 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
947 cris_evaluate_flags(dc);
948 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
950 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
953 cris_evaluate_flags(dc);
954 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
957 cris_evaluate_flags(dc);
958 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
960 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
964 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
966 cris_evaluate_flags(dc);
967 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
969 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
974 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
975 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
978 cris_evaluate_flags(dc);
979 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
984 cris_evaluate_flags(dc);
985 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
989 cris_evaluate_flags(dc);
993 tmp = tcg_temp_new(TCG_TYPE_TL);
994 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
996 /* Overlay the C flag on top of the Z. */
997 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
998 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
999 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
1001 tcg_gen_discard_tl(tmp);
1005 cris_evaluate_flags(dc);
1006 /* Overlay the V flag on top of the N. */
1007 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1008 tcg_gen_xor_tl(cpu_T[0],
1009 cpu_PR[PR_CCS], cpu_T[0]);
1010 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1011 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
1014 cris_evaluate_flags(dc);
1015 /* Overlay the V flag on top of the N. */
1016 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1017 tcg_gen_xor_tl(cpu_T[0],
1018 cpu_PR[PR_CCS], cpu_T[0]);
1019 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
1022 cris_evaluate_flags(dc);
1026 n = tcg_temp_new(TCG_TYPE_TL);
1027 z = tcg_temp_new(TCG_TYPE_TL);
1029 /* To avoid a shift we overlay everything on
1031 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1032 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1034 tcg_gen_xori_tl(z, z, 2);
1036 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1037 tcg_gen_xori_tl(n, n, 2);
1038 tcg_gen_and_tl(cpu_T[0], z, n);
1039 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1041 tcg_gen_discard_tl(n);
1042 tcg_gen_discard_tl(z);
1046 cris_evaluate_flags(dc);
1050 n = tcg_temp_new(TCG_TYPE_TL);
1051 z = tcg_temp_new(TCG_TYPE_TL);
1053 /* To avoid a shift we overlay everything on
1055 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1056 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1058 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1059 tcg_gen_or_tl(cpu_T[0], z, n);
1060 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1062 tcg_gen_discard_tl(n);
1063 tcg_gen_discard_tl(z);
1067 cris_evaluate_flags(dc);
1068 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
1071 cris_evaluate_flags(dc);
1072 tcg_gen_movi_tl(cpu_T[0], 1);
1080 static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
1082 /* This helps us re-schedule the micro-code to insns in delay-slots
1083 before the actual jump. */
1084 dc->delayed_branch = 2;
1085 dc->delayed_pc = dc->pc + offset;
1089 gen_tst_cc (dc, cond);
1090 t_gen_mov_env_TN(btaken, cpu_T[0]);
1092 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
1096 /* Dynamic jumps, when the dest is in a live reg for example. */
1097 void cris_prepare_dyn_jmp (DisasContext *dc)
1099 /* This helps us re-schedule the micro-code to insns in delay-slots
1100 before the actual jump. */
1101 dc->delayed_branch = 2;
1106 void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
1108 /* This helps us re-schedule the micro-code to insns in delay-slots
1109 before the actual jump. */
1110 dc->delayed_branch = 2;
1111 dc->delayed_pc = dst;
1116 void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1117 unsigned int size, int sign)
1119 int mem_index = cpu_mmu_index(dc->env);
1123 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1125 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1127 else if (size == 2) {
1129 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1131 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1134 tcg_gen_qemu_ld32s(dst, addr, mem_index);
1138 void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1141 int mem_index = cpu_mmu_index(dc->env);
1143 cris_evaluate_flags(dc);
1145 /* Remember, operands are flipped. CRIS has reversed order. */
1147 tcg_gen_qemu_st8(val, addr, mem_index);
1149 tcg_gen_qemu_st16(val, addr, mem_index);
1151 tcg_gen_qemu_st32(val, addr, mem_index);
1154 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1157 tcg_gen_ext8s_i32(d, s);
1159 tcg_gen_ext16s_i32(d, s);
1161 tcg_gen_mov_tl(d, s);
1164 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1167 tcg_gen_ext8u_i32(d, s);
1169 tcg_gen_ext16u_i32(d, s);
1171 tcg_gen_mov_tl(d, s);
1175 static char memsize_char(int size)
1179 case 1: return 'b'; break;
1180 case 2: return 'w'; break;
1181 case 4: return 'd'; break;
1189 static unsigned int memsize_z(DisasContext *dc)
1191 return dc->zsize + 1;
1194 static unsigned int memsize_zz(DisasContext *dc)
1205 static inline void do_postinc (DisasContext *dc, int size)
1208 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1212 static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1213 int size, int s_ext)
1216 t_gen_sext(cpu_T[1], cpu_R[rs], size);
1218 t_gen_zext(cpu_T[1], cpu_R[rs], size);
1221 /* Prepare T0 and T1 for a register alu operation.
1222 s_ext decides if the operand1 should be sign-extended or zero-extended when
1224 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1225 int size, int s_ext)
1227 dec_prep_move_r(dc, rs, rd, size, s_ext);
1230 t_gen_sext(cpu_T[0], cpu_R[rd], size);
1232 t_gen_zext(cpu_T[0], cpu_R[rd], size);
1235 /* Prepare T0 and T1 for a memory + alu operation.
1236 s_ext decides if the operand1 should be sign-extended or zero-extended when
1238 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1240 unsigned int rs, rd;
1247 is_imm = rs == 15 && dc->postinc;
1249 /* Load [$rs] onto T1. */
1251 insn_len = 2 + memsize;
1258 imm = ldsb_code(dc->pc + 2);
1260 imm = ldsw_code(dc->pc + 2);
1263 imm = ldub_code(dc->pc + 2);
1265 imm = lduw_code(dc->pc + 2);
1268 imm = ldl_code(dc->pc + 2);
1270 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1271 imm, rd, s_ext, memsize));
1272 tcg_gen_movi_tl(cpu_T[1], imm);
1275 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
1277 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
1279 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
1282 /* put dest in T0. */
1283 t_gen_mov_TN_reg(cpu_T[0], rd);
1288 static const char *cc_name(int cc)
1290 static char *cc_names[16] = {
1291 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1292 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1295 return cc_names[cc];
1299 /* Start of insn decoders. */
1301 static unsigned int dec_bccq(DisasContext *dc)
1305 uint32_t cond = dc->op2;
1308 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1309 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1312 offset |= sign << 8;
1314 offset = sign_extend(offset, 8);
1316 /* op2 holds the condition-code. */
1317 cris_cc_mask(dc, 0);
1318 cris_prepare_cc_branch (dc, offset, cond);
1321 static unsigned int dec_addoq(DisasContext *dc)
1325 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1326 imm = sign_extend(dc->op1, 7);
1328 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1329 cris_cc_mask(dc, 0);
1330 /* Fetch register operand, */
1331 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1334 static unsigned int dec_addq(DisasContext *dc)
1336 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1338 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1340 cris_cc_mask(dc, CC_MASK_NZVC);
1341 /* Fetch register operand, */
1342 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1343 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1344 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1347 static unsigned int dec_moveq(DisasContext *dc)
1351 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1352 imm = sign_extend(dc->op1, 5);
1353 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1355 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
1358 static unsigned int dec_subq(DisasContext *dc)
1360 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1362 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1364 cris_cc_mask(dc, CC_MASK_NZVC);
1365 /* Fetch register operand, */
1366 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1367 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1368 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1371 static unsigned int dec_cmpq(DisasContext *dc)
1374 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1375 imm = sign_extend(dc->op1, 5);
1377 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1378 cris_cc_mask(dc, CC_MASK_NZVC);
1379 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1380 tcg_gen_movi_tl(cpu_T[1], imm);
1381 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1384 static unsigned int dec_andq(DisasContext *dc)
1387 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1388 imm = sign_extend(dc->op1, 5);
1390 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1391 cris_cc_mask(dc, CC_MASK_NZ);
1392 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1393 tcg_gen_movi_tl(cpu_T[1], imm);
1394 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1397 static unsigned int dec_orq(DisasContext *dc)
1400 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1401 imm = sign_extend(dc->op1, 5);
1402 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1403 cris_cc_mask(dc, CC_MASK_NZ);
1404 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1405 tcg_gen_movi_tl(cpu_T[1], imm);
1406 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1409 static unsigned int dec_btstq(DisasContext *dc)
1411 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1412 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
1414 cris_cc_mask(dc, CC_MASK_NZ);
1415 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1416 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1417 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1419 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1420 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1424 static unsigned int dec_asrq(DisasContext *dc)
1426 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1427 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1428 cris_cc_mask(dc, CC_MASK_NZ);
1429 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1430 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1431 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1434 static unsigned int dec_lslq(DisasContext *dc)
1436 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1437 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1439 cris_cc_mask(dc, CC_MASK_NZ);
1440 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1441 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1442 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1445 static unsigned int dec_lsrq(DisasContext *dc)
1447 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1448 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1450 cris_cc_mask(dc, CC_MASK_NZ);
1451 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1452 tcg_gen_movi_tl(cpu_T[1], dc->op1);
1453 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1457 static unsigned int dec_move_r(DisasContext *dc)
1459 int size = memsize_zz(dc);
1461 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1462 memsize_char(size), dc->op1, dc->op2));
1464 cris_cc_mask(dc, CC_MASK_NZ);
1465 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1466 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1470 static unsigned int dec_scc_r(DisasContext *dc)
1474 DIS(fprintf (logfile, "s%s $r%u\n",
1475 cc_name(cond), dc->op1));
1481 gen_tst_cc (dc, cond);
1483 l1 = gen_new_label();
1484 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1485 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
1486 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1490 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1492 cris_cc_mask(dc, 0);
1496 static unsigned int dec_and_r(DisasContext *dc)
1498 int size = memsize_zz(dc);
1500 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1501 memsize_char(size), dc->op1, dc->op2));
1502 cris_cc_mask(dc, CC_MASK_NZ);
1503 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1504 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1508 static unsigned int dec_lz_r(DisasContext *dc)
1510 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1512 cris_cc_mask(dc, CC_MASK_NZ);
1513 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1514 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1518 static unsigned int dec_lsl_r(DisasContext *dc)
1520 int size = memsize_zz(dc);
1522 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1523 memsize_char(size), dc->op1, dc->op2));
1524 cris_cc_mask(dc, CC_MASK_NZ);
1525 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1526 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1527 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1531 static unsigned int dec_lsr_r(DisasContext *dc)
1533 int size = memsize_zz(dc);
1535 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1536 memsize_char(size), dc->op1, dc->op2));
1537 cris_cc_mask(dc, CC_MASK_NZ);
1538 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1539 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1540 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1544 static unsigned int dec_asr_r(DisasContext *dc)
1546 int size = memsize_zz(dc);
1548 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1549 memsize_char(size), dc->op1, dc->op2));
1550 cris_cc_mask(dc, CC_MASK_NZ);
1551 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1552 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
1553 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1557 static unsigned int dec_muls_r(DisasContext *dc)
1559 int size = memsize_zz(dc);
1561 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1562 memsize_char(size), dc->op1, dc->op2));
1563 cris_cc_mask(dc, CC_MASK_NZV);
1564 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
1565 t_gen_sext(cpu_T[0], cpu_T[0], size);
1566 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1570 static unsigned int dec_mulu_r(DisasContext *dc)
1572 int size = memsize_zz(dc);
1574 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1575 memsize_char(size), dc->op1, dc->op2));
1576 cris_cc_mask(dc, CC_MASK_NZV);
1577 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1578 t_gen_zext(cpu_T[0], cpu_T[0], size);
1579 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1584 static unsigned int dec_dstep_r(DisasContext *dc)
1586 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1587 cris_cc_mask(dc, CC_MASK_NZ);
1588 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1589 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1590 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1594 static unsigned int dec_xor_r(DisasContext *dc)
1596 int size = memsize_zz(dc);
1597 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1598 memsize_char(size), dc->op1, dc->op2));
1599 BUG_ON(size != 4); /* xor is dword. */
1600 cris_cc_mask(dc, CC_MASK_NZ);
1601 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1602 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1606 static unsigned int dec_bound_r(DisasContext *dc)
1608 int size = memsize_zz(dc);
1609 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1610 memsize_char(size), dc->op1, dc->op2));
1611 cris_cc_mask(dc, CC_MASK_NZ);
1612 /* TODO: needs optmimization. */
1613 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1614 /* rd should be 4. */
1615 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1616 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1620 static unsigned int dec_cmp_r(DisasContext *dc)
1622 int size = memsize_zz(dc);
1623 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1624 memsize_char(size), dc->op1, dc->op2));
1625 cris_cc_mask(dc, CC_MASK_NZVC);
1626 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1627 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1631 static unsigned int dec_abs_r(DisasContext *dc)
1635 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1637 cris_cc_mask(dc, CC_MASK_NZ);
1638 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
1640 /* TODO: consider a branch free approach. */
1641 l1 = gen_new_label();
1642 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1643 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
1645 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1649 static unsigned int dec_add_r(DisasContext *dc)
1651 int size = memsize_zz(dc);
1652 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1653 memsize_char(size), dc->op1, dc->op2));
1654 cris_cc_mask(dc, CC_MASK_NZVC);
1655 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1656 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1660 static unsigned int dec_addc_r(DisasContext *dc)
1662 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1664 cris_evaluate_flags(dc);
1665 cris_cc_mask(dc, CC_MASK_NZVC);
1666 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1667 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1671 static unsigned int dec_mcp_r(DisasContext *dc)
1673 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1675 cris_evaluate_flags(dc);
1676 cris_cc_mask(dc, CC_MASK_RNZV);
1677 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1678 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1679 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1684 static char * swapmode_name(int mode, char *modename) {
1687 modename[i++] = 'n';
1689 modename[i++] = 'w';
1691 modename[i++] = 'b';
1693 modename[i++] = 'r';
1699 static unsigned int dec_swap_r(DisasContext *dc)
1701 DIS(char modename[4]);
1702 DIS(fprintf (logfile, "swap%s $r%u\n",
1703 swapmode_name(dc->op2, modename), dc->op1));
1705 cris_cc_mask(dc, CC_MASK_NZ);
1706 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1708 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
1710 t_gen_swapw(cpu_T[0], cpu_T[0]);
1712 t_gen_swapb(cpu_T[0], cpu_T[0]);
1714 t_gen_swapr(cpu_T[0], cpu_T[0]);
1715 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1716 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1720 static unsigned int dec_or_r(DisasContext *dc)
1722 int size = memsize_zz(dc);
1723 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1724 memsize_char(size), dc->op1, dc->op2));
1725 cris_cc_mask(dc, CC_MASK_NZ);
1726 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1727 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1731 static unsigned int dec_addi_r(DisasContext *dc)
1733 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1734 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1735 cris_cc_mask(dc, 0);
1736 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1737 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1738 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1739 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
1743 static unsigned int dec_addi_acr(DisasContext *dc)
1745 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
1746 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1747 cris_cc_mask(dc, 0);
1748 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1749 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
1751 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1752 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
1756 static unsigned int dec_neg_r(DisasContext *dc)
1758 int size = memsize_zz(dc);
1759 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1760 memsize_char(size), dc->op1, dc->op2));
1761 cris_cc_mask(dc, CC_MASK_NZVC);
1762 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1763 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1767 static unsigned int dec_btst_r(DisasContext *dc)
1769 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1771 cris_cc_mask(dc, CC_MASK_NZ);
1772 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1773 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1775 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1776 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
1781 static unsigned int dec_sub_r(DisasContext *dc)
1783 int size = memsize_zz(dc);
1784 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1785 memsize_char(size), dc->op1, dc->op2));
1786 cris_cc_mask(dc, CC_MASK_NZVC);
1787 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1788 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1792 /* Zero extension. From size to dword. */
1793 static unsigned int dec_movu_r(DisasContext *dc)
1795 int size = memsize_z(dc);
1796 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1800 cris_cc_mask(dc, CC_MASK_NZ);
1801 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1802 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1806 /* Sign extension. From size to dword. */
1807 static unsigned int dec_movs_r(DisasContext *dc)
1809 int size = memsize_z(dc);
1810 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1814 cris_cc_mask(dc, CC_MASK_NZ);
1815 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1816 /* Size can only be qi or hi. */
1817 t_gen_sext(cpu_T[1], cpu_T[0], size);
1818 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1822 /* zero extension. From size to dword. */
1823 static unsigned int dec_addu_r(DisasContext *dc)
1825 int size = memsize_z(dc);
1826 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1830 cris_cc_mask(dc, CC_MASK_NZVC);
1831 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1832 /* Size can only be qi or hi. */
1833 t_gen_zext(cpu_T[1], cpu_T[1], size);
1834 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1835 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1839 /* Sign extension. From size to dword. */
1840 static unsigned int dec_adds_r(DisasContext *dc)
1842 int size = memsize_z(dc);
1843 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1847 cris_cc_mask(dc, CC_MASK_NZVC);
1848 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1849 /* Size can only be qi or hi. */
1850 t_gen_sext(cpu_T[1], cpu_T[1], size);
1851 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1853 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1857 /* Zero extension. From size to dword. */
1858 static unsigned int dec_subu_r(DisasContext *dc)
1860 int size = memsize_z(dc);
1861 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1865 cris_cc_mask(dc, CC_MASK_NZVC);
1866 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1867 /* Size can only be qi or hi. */
1868 t_gen_zext(cpu_T[1], cpu_T[1], size);
1869 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1870 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1874 /* Sign extension. From size to dword. */
1875 static unsigned int dec_subs_r(DisasContext *dc)
1877 int size = memsize_z(dc);
1878 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1882 cris_cc_mask(dc, CC_MASK_NZVC);
1883 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1884 /* Size can only be qi or hi. */
1885 t_gen_sext(cpu_T[1], cpu_T[1], size);
1886 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1887 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1891 static unsigned int dec_setclrf(DisasContext *dc)
1894 int set = (~dc->opcode >> 2) & 1;
1896 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1897 | EXTRACT_FIELD(dc->ir, 0, 3);
1898 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1899 if (set && flags == 0)
1900 DIS(fprintf (logfile, "nop\n"));
1901 else if (!set && (flags & 0x20))
1902 DIS(fprintf (logfile, "di\n"));
1904 DIS(fprintf (logfile, "%sf %x\n",
1905 set ? "set" : "clr",
1908 if (set && (flags & X_FLAG)) {
1913 /* Simply decode the flags. */
1914 cris_evaluate_flags (dc);
1915 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1916 tcg_gen_movi_tl(cc_op, dc->cc_op);
1919 if (!dc->user && (flags & U_FLAG)) {
1920 /* Enter user mode. */
1921 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
1922 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
1923 dc->is_jmp = DISAS_UPDATE;
1925 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
1928 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
1935 static unsigned int dec_move_rs(DisasContext *dc)
1937 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1938 cris_cc_mask(dc, 0);
1939 tcg_gen_helper_0_2(helper_movl_sreg_reg,
1940 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
1943 static unsigned int dec_move_sr(DisasContext *dc)
1945 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
1946 cris_cc_mask(dc, 0);
1947 tcg_gen_helper_0_2(helper_movl_reg_sreg,
1948 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
1952 static unsigned int dec_move_rp(DisasContext *dc)
1954 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1955 cris_cc_mask(dc, 0);
1957 if (dc->op2 == PR_CCS) {
1958 cris_evaluate_flags(dc);
1959 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1961 /* User space is not allowed to touch all flags. */
1962 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1963 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1964 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1968 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1970 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
1971 if (dc->op2 == PR_CCS) {
1972 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1977 static unsigned int dec_move_pr(DisasContext *dc)
1979 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1980 cris_cc_mask(dc, 0);
1981 /* Support register 0 is hardwired to zero.
1982 Treat it specially. */
1984 tcg_gen_movi_tl(cpu_T[1], 0);
1985 else if (dc->op2 == PR_CCS) {
1986 cris_evaluate_flags(dc);
1987 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1989 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1990 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1994 static unsigned int dec_move_mr(DisasContext *dc)
1996 int memsize = memsize_zz(dc);
1998 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1999 memsize_char(memsize),
2000 dc->op1, dc->postinc ? "+]" : "]",
2003 insn_len = dec_prep_alu_m(dc, 0, memsize);
2004 cris_cc_mask(dc, CC_MASK_NZ);
2005 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
2006 do_postinc(dc, memsize);
2010 static unsigned int dec_movs_m(DisasContext *dc)
2012 int memsize = memsize_z(dc);
2014 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
2015 memsize_char(memsize),
2016 dc->op1, dc->postinc ? "+]" : "]",
2020 insn_len = dec_prep_alu_m(dc, 1, memsize);
2021 cris_cc_mask(dc, CC_MASK_NZ);
2022 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2023 do_postinc(dc, memsize);
2027 static unsigned int dec_addu_m(DisasContext *dc)
2029 int memsize = memsize_z(dc);
2031 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2032 memsize_char(memsize),
2033 dc->op1, dc->postinc ? "+]" : "]",
2037 insn_len = dec_prep_alu_m(dc, 0, memsize);
2038 cris_cc_mask(dc, CC_MASK_NZVC);
2039 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2040 do_postinc(dc, memsize);
2044 static unsigned int dec_adds_m(DisasContext *dc)
2046 int memsize = memsize_z(dc);
2048 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2049 memsize_char(memsize),
2050 dc->op1, dc->postinc ? "+]" : "]",
2054 insn_len = dec_prep_alu_m(dc, 1, memsize);
2055 cris_cc_mask(dc, CC_MASK_NZVC);
2056 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2057 do_postinc(dc, memsize);
2061 static unsigned int dec_subu_m(DisasContext *dc)
2063 int memsize = memsize_z(dc);
2065 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2066 memsize_char(memsize),
2067 dc->op1, dc->postinc ? "+]" : "]",
2071 insn_len = dec_prep_alu_m(dc, 0, memsize);
2072 cris_cc_mask(dc, CC_MASK_NZVC);
2073 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2074 do_postinc(dc, memsize);
2078 static unsigned int dec_subs_m(DisasContext *dc)
2080 int memsize = memsize_z(dc);
2082 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2083 memsize_char(memsize),
2084 dc->op1, dc->postinc ? "+]" : "]",
2088 insn_len = dec_prep_alu_m(dc, 1, memsize);
2089 cris_cc_mask(dc, CC_MASK_NZVC);
2090 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2091 do_postinc(dc, memsize);
2095 static unsigned int dec_movu_m(DisasContext *dc)
2097 int memsize = memsize_z(dc);
2100 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2101 memsize_char(memsize),
2102 dc->op1, dc->postinc ? "+]" : "]",
2105 insn_len = dec_prep_alu_m(dc, 0, memsize);
2106 cris_cc_mask(dc, CC_MASK_NZ);
2107 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2108 do_postinc(dc, memsize);
2112 static unsigned int dec_cmpu_m(DisasContext *dc)
2114 int memsize = memsize_z(dc);
2116 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2117 memsize_char(memsize),
2118 dc->op1, dc->postinc ? "+]" : "]",
2121 insn_len = dec_prep_alu_m(dc, 0, memsize);
2122 cris_cc_mask(dc, CC_MASK_NZVC);
2123 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
2124 do_postinc(dc, memsize);
2128 static unsigned int dec_cmps_m(DisasContext *dc)
2130 int memsize = memsize_z(dc);
2132 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2133 memsize_char(memsize),
2134 dc->op1, dc->postinc ? "+]" : "]",
2137 insn_len = dec_prep_alu_m(dc, 1, memsize);
2138 cris_cc_mask(dc, CC_MASK_NZVC);
2139 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2140 do_postinc(dc, memsize);
2144 static unsigned int dec_cmp_m(DisasContext *dc)
2146 int memsize = memsize_zz(dc);
2148 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2149 memsize_char(memsize),
2150 dc->op1, dc->postinc ? "+]" : "]",
2153 insn_len = dec_prep_alu_m(dc, 0, memsize);
2154 cris_cc_mask(dc, CC_MASK_NZVC);
2155 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2156 do_postinc(dc, memsize);
2160 static unsigned int dec_test_m(DisasContext *dc)
2162 int memsize = memsize_zz(dc);
2164 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2165 memsize_char(memsize),
2166 dc->op1, dc->postinc ? "+]" : "]",
2169 cris_evaluate_flags(dc);
2171 insn_len = dec_prep_alu_m(dc, 0, memsize);
2172 cris_cc_mask(dc, CC_MASK_NZ);
2173 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2175 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2176 tcg_gen_movi_tl(cpu_T[1], 0);
2177 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2178 do_postinc(dc, memsize);
2182 static unsigned int dec_and_m(DisasContext *dc)
2184 int memsize = memsize_zz(dc);
2186 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2187 memsize_char(memsize),
2188 dc->op1, dc->postinc ? "+]" : "]",
2191 insn_len = dec_prep_alu_m(dc, 0, memsize);
2192 cris_cc_mask(dc, CC_MASK_NZ);
2193 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
2194 do_postinc(dc, memsize);
2198 static unsigned int dec_add_m(DisasContext *dc)
2200 int memsize = memsize_zz(dc);
2202 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2203 memsize_char(memsize),
2204 dc->op1, dc->postinc ? "+]" : "]",
2207 insn_len = dec_prep_alu_m(dc, 0, memsize);
2208 cris_cc_mask(dc, CC_MASK_NZVC);
2209 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
2210 do_postinc(dc, memsize);
2214 static unsigned int dec_addo_m(DisasContext *dc)
2216 int memsize = memsize_zz(dc);
2218 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2219 memsize_char(memsize),
2220 dc->op1, dc->postinc ? "+]" : "]",
2223 insn_len = dec_prep_alu_m(dc, 1, memsize);
2224 cris_cc_mask(dc, 0);
2225 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
2226 do_postinc(dc, memsize);
2230 static unsigned int dec_bound_m(DisasContext *dc)
2232 int memsize = memsize_zz(dc);
2234 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2235 memsize_char(memsize),
2236 dc->op1, dc->postinc ? "+]" : "]",
2239 insn_len = dec_prep_alu_m(dc, 0, memsize);
2240 cris_cc_mask(dc, CC_MASK_NZ);
2241 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
2242 do_postinc(dc, memsize);
2246 static unsigned int dec_addc_mr(DisasContext *dc)
2249 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2250 dc->op1, dc->postinc ? "+]" : "]",
2253 cris_evaluate_flags(dc);
2254 insn_len = dec_prep_alu_m(dc, 0, 4);
2255 cris_cc_mask(dc, CC_MASK_NZVC);
2256 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2261 static unsigned int dec_sub_m(DisasContext *dc)
2263 int memsize = memsize_zz(dc);
2265 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2266 memsize_char(memsize),
2267 dc->op1, dc->postinc ? "+]" : "]",
2268 dc->op2, dc->ir, dc->zzsize));
2270 insn_len = dec_prep_alu_m(dc, 0, memsize);
2271 cris_cc_mask(dc, CC_MASK_NZVC);
2272 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2273 do_postinc(dc, memsize);
2277 static unsigned int dec_or_m(DisasContext *dc)
2279 int memsize = memsize_zz(dc);
2281 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2282 memsize_char(memsize),
2283 dc->op1, dc->postinc ? "+]" : "]",
2286 insn_len = dec_prep_alu_m(dc, 0, memsize);
2287 cris_cc_mask(dc, CC_MASK_NZ);
2288 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2289 do_postinc(dc, memsize);
2293 static unsigned int dec_move_mp(DisasContext *dc)
2295 int memsize = memsize_zz(dc);
2298 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2299 memsize_char(memsize),
2301 dc->postinc ? "+]" : "]",
2304 insn_len = dec_prep_alu_m(dc, 0, memsize);
2305 cris_cc_mask(dc, 0);
2306 if (dc->op2 == PR_CCS) {
2307 cris_evaluate_flags(dc);
2309 /* User space is not allowed to touch all flags. */
2310 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2311 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2312 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2316 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
2318 do_postinc(dc, memsize);
2322 static unsigned int dec_move_pm(DisasContext *dc)
2326 memsize = preg_sizes[dc->op2];
2328 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2329 memsize_char(memsize),
2330 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
2332 /* prepare store. Address in T0, value in T1. */
2333 if (dc->op2 == PR_CCS)
2334 cris_evaluate_flags(dc);
2335 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2337 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2339 cris_cc_mask(dc, 0);
2341 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2345 static unsigned int dec_movem_mr(DisasContext *dc)
2350 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2351 dc->postinc ? "+]" : "]", dc->op2));
2353 /* fetch the address into T0 and T1. */
2354 for (i = 0; i <= dc->op2; i++) {
2355 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
2356 /* Perform the load onto regnum i. Always dword wide. */
2357 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2358 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
2361 for (i = 0; i <= dc->op2; i++) {
2362 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2363 tcg_gen_discard_tl(tmp[i]);
2366 /* writeback the updated pointer value. */
2368 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2370 /* gen_load might want to evaluate the previous insns flags. */
2371 cris_cc_mask(dc, 0);
2375 static unsigned int dec_movem_rm(DisasContext *dc)
2379 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2380 dc->postinc ? "+]" : "]"));
2382 for (i = 0; i <= dc->op2; i++) {
2383 /* Displace addr. */
2384 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2385 /* Perform the store. */
2386 gen_store(dc, cpu_T[0], cpu_R[i], 4);
2389 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
2390 cris_cc_mask(dc, 0);
2394 static unsigned int dec_move_rm(DisasContext *dc)
2398 memsize = memsize_zz(dc);
2400 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2401 memsize, dc->op2, dc->op1));
2403 /* prepare store. */
2404 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2407 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2408 cris_cc_mask(dc, 0);
2412 static unsigned int dec_lapcq(DisasContext *dc)
2414 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2415 dc->pc + dc->op1*2, dc->op2));
2416 cris_cc_mask(dc, 0);
2417 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
2418 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2422 static unsigned int dec_lapc_im(DisasContext *dc)
2430 cris_cc_mask(dc, 0);
2431 imm = ldl_code(dc->pc + 2);
2432 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
2436 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
2440 /* Jump to special reg. */
2441 static unsigned int dec_jump_p(DisasContext *dc)
2443 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2445 if (dc->op2 == PR_CCS)
2446 cris_evaluate_flags(dc);
2447 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
2448 /* rete will often have low bit set to indicate delayslot. */
2449 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
2450 cris_cc_mask(dc, 0);
2451 cris_prepare_dyn_jmp(dc);
2455 /* Jump and save. */
2456 static unsigned int dec_jas_r(DisasContext *dc)
2458 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2459 cris_cc_mask(dc, 0);
2460 /* Store the return address in Pd. */
2461 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2464 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
2465 tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
2467 cris_prepare_dyn_jmp(dc);
2471 static unsigned int dec_jas_im(DisasContext *dc)
2475 imm = ldl_code(dc->pc + 2);
2477 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2478 cris_cc_mask(dc, 0);
2479 /* Store the return address in Pd. */
2480 tcg_gen_movi_tl(env_btarget, imm);
2481 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
2482 cris_prepare_dyn_jmp(dc);
2486 static unsigned int dec_jasc_im(DisasContext *dc)
2490 imm = ldl_code(dc->pc + 2);
2492 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2493 cris_cc_mask(dc, 0);
2494 /* Store the return address in Pd. */
2495 tcg_gen_movi_tl(cpu_T[0], imm);
2496 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2497 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2498 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2499 cris_prepare_dyn_jmp(dc);
2503 static unsigned int dec_jasc_r(DisasContext *dc)
2505 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2506 cris_cc_mask(dc, 0);
2507 /* Store the return address in Pd. */
2508 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2509 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2510 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2511 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2512 cris_prepare_dyn_jmp(dc);
2516 static unsigned int dec_bcc_im(DisasContext *dc)
2519 uint32_t cond = dc->op2;
2521 offset = ldsw_code(dc->pc + 2);
2523 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2524 cc_name(cond), offset,
2525 dc->pc, dc->pc + offset));
2527 cris_cc_mask(dc, 0);
2528 /* op2 holds the condition-code. */
2529 cris_prepare_cc_branch (dc, offset, cond);
2533 static unsigned int dec_bas_im(DisasContext *dc)
2538 simm = ldl_code(dc->pc + 2);
2540 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2541 cris_cc_mask(dc, 0);
2542 /* Stor the return address in Pd. */
2543 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2544 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2545 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2546 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2547 cris_prepare_dyn_jmp(dc);
2551 static unsigned int dec_basc_im(DisasContext *dc)
2554 simm = ldl_code(dc->pc + 2);
2556 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2557 cris_cc_mask(dc, 0);
2558 /* Stor the return address in Pd. */
2559 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
2560 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
2561 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2562 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
2563 cris_prepare_dyn_jmp(dc);
2567 static unsigned int dec_rfe_etc(DisasContext *dc)
2569 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2570 dc->opcode, dc->pc, dc->op1, dc->op2));
2572 cris_cc_mask(dc, 0);
2574 if (dc->op2 == 15) /* ignore halt. */
2577 switch (dc->op2 & 7) {
2580 cris_evaluate_flags(dc);
2581 tcg_gen_helper_0_0(helper_rfe);
2582 dc->is_jmp = DISAS_UPDATE;
2590 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2591 t_gen_mov_env_TN(pc, cpu_T[0]);
2592 /* Breaks start at 16 in the exception vector. */
2593 t_gen_mov_env_TN(trap_vector,
2594 tcg_const_tl(dc->op1 + 16));
2595 t_gen_raise_exception(EXCP_BREAK);
2596 dc->is_jmp = DISAS_UPDATE;
2599 printf ("op2=%x\n", dc->op2);
2607 static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2609 /* Ignore D-cache flushes. */
2613 static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2615 /* Ignore I-cache flushes. */
2619 static unsigned int dec_null(DisasContext *dc)
2621 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2622 dc->pc, dc->opcode, dc->op1, dc->op2);
2628 struct decoder_info {
2633 unsigned int (*dec)(DisasContext *dc);
2635 /* Order matters here. */
2636 {DEC_MOVEQ, dec_moveq},
2637 {DEC_BTSTQ, dec_btstq},
2638 {DEC_CMPQ, dec_cmpq},
2639 {DEC_ADDOQ, dec_addoq},
2640 {DEC_ADDQ, dec_addq},
2641 {DEC_SUBQ, dec_subq},
2642 {DEC_ANDQ, dec_andq},
2644 {DEC_ASRQ, dec_asrq},
2645 {DEC_LSLQ, dec_lslq},
2646 {DEC_LSRQ, dec_lsrq},
2647 {DEC_BCCQ, dec_bccq},
2649 {DEC_BCC_IM, dec_bcc_im},
2650 {DEC_JAS_IM, dec_jas_im},
2651 {DEC_JAS_R, dec_jas_r},
2652 {DEC_JASC_IM, dec_jasc_im},
2653 {DEC_JASC_R, dec_jasc_r},
2654 {DEC_BAS_IM, dec_bas_im},
2655 {DEC_BASC_IM, dec_basc_im},
2656 {DEC_JUMP_P, dec_jump_p},
2657 {DEC_LAPC_IM, dec_lapc_im},
2658 {DEC_LAPCQ, dec_lapcq},
2660 {DEC_RFE_ETC, dec_rfe_etc},
2661 {DEC_ADDC_MR, dec_addc_mr},
2663 {DEC_MOVE_MP, dec_move_mp},
2664 {DEC_MOVE_PM, dec_move_pm},
2665 {DEC_MOVEM_MR, dec_movem_mr},
2666 {DEC_MOVEM_RM, dec_movem_rm},
2667 {DEC_MOVE_PR, dec_move_pr},
2668 {DEC_SCC_R, dec_scc_r},
2669 {DEC_SETF, dec_setclrf},
2670 {DEC_CLEARF, dec_setclrf},
2672 {DEC_MOVE_SR, dec_move_sr},
2673 {DEC_MOVE_RP, dec_move_rp},
2674 {DEC_SWAP_R, dec_swap_r},
2675 {DEC_ABS_R, dec_abs_r},
2676 {DEC_LZ_R, dec_lz_r},
2677 {DEC_MOVE_RS, dec_move_rs},
2678 {DEC_BTST_R, dec_btst_r},
2679 {DEC_ADDC_R, dec_addc_r},
2681 {DEC_DSTEP_R, dec_dstep_r},
2682 {DEC_XOR_R, dec_xor_r},
2683 {DEC_MCP_R, dec_mcp_r},
2684 {DEC_CMP_R, dec_cmp_r},
2686 {DEC_ADDI_R, dec_addi_r},
2687 {DEC_ADDI_ACR, dec_addi_acr},
2689 {DEC_ADD_R, dec_add_r},
2690 {DEC_SUB_R, dec_sub_r},
2692 {DEC_ADDU_R, dec_addu_r},
2693 {DEC_ADDS_R, dec_adds_r},
2694 {DEC_SUBU_R, dec_subu_r},
2695 {DEC_SUBS_R, dec_subs_r},
2696 {DEC_LSL_R, dec_lsl_r},
2698 {DEC_AND_R, dec_and_r},
2699 {DEC_OR_R, dec_or_r},
2700 {DEC_BOUND_R, dec_bound_r},
2701 {DEC_ASR_R, dec_asr_r},
2702 {DEC_LSR_R, dec_lsr_r},
2704 {DEC_MOVU_R, dec_movu_r},
2705 {DEC_MOVS_R, dec_movs_r},
2706 {DEC_NEG_R, dec_neg_r},
2707 {DEC_MOVE_R, dec_move_r},
2709 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2710 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2712 {DEC_MULS_R, dec_muls_r},
2713 {DEC_MULU_R, dec_mulu_r},
2715 {DEC_ADDU_M, dec_addu_m},
2716 {DEC_ADDS_M, dec_adds_m},
2717 {DEC_SUBU_M, dec_subu_m},
2718 {DEC_SUBS_M, dec_subs_m},
2720 {DEC_CMPU_M, dec_cmpu_m},
2721 {DEC_CMPS_M, dec_cmps_m},
2722 {DEC_MOVU_M, dec_movu_m},
2723 {DEC_MOVS_M, dec_movs_m},
2725 {DEC_CMP_M, dec_cmp_m},
2726 {DEC_ADDO_M, dec_addo_m},
2727 {DEC_BOUND_M, dec_bound_m},
2728 {DEC_ADD_M, dec_add_m},
2729 {DEC_SUB_M, dec_sub_m},
2730 {DEC_AND_M, dec_and_m},
2731 {DEC_OR_M, dec_or_m},
2732 {DEC_MOVE_RM, dec_move_rm},
2733 {DEC_TEST_M, dec_test_m},
2734 {DEC_MOVE_MR, dec_move_mr},
2739 static inline unsigned int
2740 cris_decoder(DisasContext *dc)
2742 unsigned int insn_len = 2;
2745 /* Load a halfword onto the instruction register. */
2746 dc->ir = lduw_code(dc->pc);
2748 /* Now decode it. */
2749 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2750 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2751 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2752 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2753 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2754 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2756 /* Large switch for all insns. */
2757 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2758 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2760 insn_len = decinfo[i].dec(dc);
2768 static void check_breakpoint(CPUState *env, DisasContext *dc)
2771 if (env->nb_breakpoints > 0) {
2772 for(j = 0; j < env->nb_breakpoints; j++) {
2773 if (env->breakpoints[j] == dc->pc) {
2774 cris_evaluate_flags (dc);
2775 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2776 t_gen_mov_env_TN(pc, cpu_T[0]);
2777 t_gen_raise_exception(EXCP_DEBUG);
2778 dc->is_jmp = DISAS_UPDATE;
2784 /* generate intermediate code for basic block 'tb'. */
2785 struct DisasContext ctx;
2787 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2790 uint16_t *gen_opc_end;
2792 unsigned int insn_len;
2794 struct DisasContext *dc = &ctx;
2795 uint32_t next_page_start;
2800 /* Odd PC indicates that branch is rexecuting due to exception in the
2801 * delayslot, like in real hw.
2802 * FIXME: we need to handle the case were the branch and the insn in
2803 * the delayslot do not share pages.
2805 pc_start = tb->pc & ~1;
2809 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2811 dc->is_jmp = DISAS_NEXT;
2814 dc->singlestep_enabled = env->singlestep_enabled;
2819 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2821 dc->user = env->pregs[PR_CCS] & U_FLAG;
2822 dc->delayed_branch = 0;
2824 if (loglevel & CPU_LOG_TB_IN_ASM) {
2826 "search=%d pc=%x ccs=%x pid=%x usp=%x dbg=%x %x %x\n"
2831 search_pc, env->pc, env->pregs[PR_CCS],
2832 env->pregs[PR_PID], env->pregs[PR_USP],
2833 env->debug1, env->debug2, env->debug3,
2834 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2835 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2836 env->regs[8], env->regs[9],
2837 env->regs[10], env->regs[11],
2838 env->regs[12], env->regs[13],
2839 env->regs[14], env->regs[15]);
2843 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2847 check_breakpoint(env, dc);
2848 if (dc->is_jmp == DISAS_JUMP
2849 || dc->is_jmp == DISAS_SWI)
2853 j = gen_opc_ptr - gen_opc_buf;
2857 gen_opc_instr_start[lj++] = 0;
2859 if (dc->delayed_branch == 1) {
2860 gen_opc_pc[lj] = dc->ppc | 1;
2861 gen_opc_instr_start[lj] = 0;
2864 gen_opc_pc[lj] = dc->pc;
2865 gen_opc_instr_start[lj] = 1;
2870 insn_len = cris_decoder(dc);
2874 cris_clear_x_flag(dc);
2876 /* Check for delayed branches here. If we do it before
2877 actually genereating any host code, the simulator will just
2878 loop doing nothing for on this program location. */
2879 if (dc->delayed_branch) {
2880 dc->delayed_branch--;
2881 if (dc->delayed_branch == 0)
2883 if (dc->bcc == CC_A) {
2884 tcg_gen_mov_tl(env_pc, env_btarget);
2885 dc->is_jmp = DISAS_JUMP;
2888 t_gen_cc_jmp(dc->delayed_pc, dc->pc);
2889 dc->is_jmp = DISAS_JUMP;
2894 /* If we are rexecuting a branch due to exceptions on
2895 delay slots dont break. */
2896 if (!(tb->pc & 1) && env->singlestep_enabled)
2898 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
2899 && ((dc->pc < next_page_start) || dc->delayed_branch));
2901 if (dc->delayed_branch == 1) {
2902 /* Reexecute the last insn. */
2903 dc->pc = dc->ppc | 1;
2907 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2908 dc->is_jmp, dc->delayed_branch));
2909 /* T0 and env_pc should hold the new pc. */
2910 tcg_gen_movi_tl(cpu_T[0], dc->pc);
2911 tcg_gen_mov_tl(env_pc, cpu_T[0]);
2914 cris_evaluate_flags (dc);
2916 if (__builtin_expect(env->singlestep_enabled, 0)) {
2917 t_gen_raise_exception(EXCP_DEBUG);
2919 switch(dc->is_jmp) {
2921 gen_goto_tb(dc, 1, dc->pc);
2926 /* indicate that the hash table must be used
2927 to find the next TB */
2932 /* nothing more to generate */
2936 *gen_opc_ptr = INDEX_op_end;
2938 j = gen_opc_ptr - gen_opc_buf;
2941 gen_opc_instr_start[lj++] = 0;
2943 tb->size = dc->pc - pc_start;
2947 if (loglevel & CPU_LOG_TB_IN_ASM) {
2948 fprintf(logfile, "--------------\n");
2949 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2950 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
2951 fprintf(logfile, "\nisize=%d osize=%d\n",
2952 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
2958 int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2960 return gen_intermediate_code_internal(env, tb, 0);
2963 int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2965 return gen_intermediate_code_internal(env, tb, 1);
2968 void cpu_dump_state (CPUState *env, FILE *f,
2969 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2978 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2979 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2981 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
2983 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2984 env->debug1, env->debug2, env->debug3);
2986 for (i = 0; i < 16; i++) {
2987 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2988 if ((i + 1) % 4 == 0)
2989 cpu_fprintf(f, "\n");
2991 cpu_fprintf(f, "\nspecial regs:\n");
2992 for (i = 0; i < 16; i++) {
2993 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2994 if ((i + 1) % 4 == 0)
2995 cpu_fprintf(f, "\n");
2997 srs = env->pregs[PR_SRS];
2998 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3000 for (i = 0; i < 16; i++) {
3001 cpu_fprintf(f, "s%2.2d=%8.8x ",
3002 i, env->sregs[srs][i]);
3003 if ((i + 1) % 4 == 0)
3004 cpu_fprintf(f, "\n");
3007 cpu_fprintf(f, "\n\n");
3011 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
3015 CPUCRISState *cpu_cris_init (const char *cpu_model)
3020 env = qemu_mallocz(sizeof(CPUCRISState));
3025 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
3026 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3027 #if TARGET_LONG_BITS > HOST_LONG_BITS
3028 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3029 TCG_AREG0, offsetof(CPUState, t0), "T0");
3030 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3031 TCG_AREG0, offsetof(CPUState, t1), "T1");
3033 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3034 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3037 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3038 offsetof(CPUState, cc_src), "cc_src");
3039 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3040 offsetof(CPUState, cc_dest),
3042 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3043 offsetof(CPUState, cc_result),
3045 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3046 offsetof(CPUState, cc_op), "cc_op");
3047 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3048 offsetof(CPUState, cc_size),
3050 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3051 offsetof(CPUState, cc_mask),
3054 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3055 offsetof(CPUState, pc),
3057 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3058 offsetof(CPUState, btarget),
3061 for (i = 0; i < 16; i++) {
3062 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3063 offsetof(CPUState, regs[i]),
3066 for (i = 0; i < 16; i++) {
3067 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3068 offsetof(CPUState, pregs[i]),
3072 TCG_HELPER(helper_raise_exception);
3073 TCG_HELPER(helper_store);
3074 TCG_HELPER(helper_dump);
3075 TCG_HELPER(helper_dummy);
3077 TCG_HELPER(helper_tlb_flush);
3078 TCG_HELPER(helper_movl_sreg_reg);
3079 TCG_HELPER(helper_movl_reg_sreg);
3080 TCG_HELPER(helper_rfe);
3082 TCG_HELPER(helper_evaluate_flags_muls);
3083 TCG_HELPER(helper_evaluate_flags_mulu);
3084 TCG_HELPER(helper_evaluate_flags_mcp);
3085 TCG_HELPER(helper_evaluate_flags_alu_4);
3086 TCG_HELPER(helper_evaluate_flags_move_4);
3087 TCG_HELPER(helper_evaluate_flags_move_2);
3088 TCG_HELPER(helper_evaluate_flags);
3094 void cpu_reset (CPUCRISState *env)
3096 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3099 #if defined(CONFIG_USER_ONLY)
3100 /* start in user mode with interrupts enabled. */
3101 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3103 env->pregs[PR_CCS] = 0;
3107 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3108 unsigned long searched_pc, int pc_pos, void *puc)
3110 env->pc = gen_opc_pc[pc_pos];