2 * CRIS helper routines.
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include "host-utils.h"
33 #if defined(CONFIG_USER_ONLY)
35 void do_interrupt (CPUState *env)
37 env->exception_index = -1;
38 env->pregs[PR_ERP] = env->pc;
41 int cpu_cris_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
42 int mmu_idx, int is_softmmu)
44 env->exception_index = 0xaa;
45 env->debug1 = address;
46 cpu_dump_state(env, stderr, fprintf, 0);
47 env->pregs[PR_ERP] = env->pc;
51 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
56 #else /* !CONFIG_USER_ONLY */
59 static void cris_shift_ccs(CPUState *env)
62 /* Apply the ccs shift. */
63 ccs = env->pregs[PR_CCS];
64 ccs = ((ccs & 0xc0000000) | ((ccs << 12) >> 2)) & ~0x3ff;
65 env->pregs[PR_CCS] = ccs;
68 int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
69 int mmu_idx, int is_softmmu)
71 struct cris_mmu_result_t res;
76 D(printf ("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
77 address &= TARGET_PAGE_MASK;
78 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
79 miss = cris_mmu_translate(&res, env, address, rw, mmu_idx);
82 if (env->exception_index == EXCP_MMU_FAULT)
84 "CRIS: Illegal recursive bus fault."
88 env->exception_index = EXCP_MMU_FAULT;
89 env->fault_vector = res.bf_vec;
96 address &= TARGET_PAGE_MASK;
97 r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
100 D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x ismmu=%d vec=%x\n",
101 __func__, r, env->interrupt_request,
102 address, is_softmmu, res.bf_vec));
106 void do_interrupt(CPUState *env)
110 D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
111 env->exception_index,
112 env->interrupt_request));
114 switch (env->exception_index)
117 /* These exceptions are genereated by the core itself.
118 ERP should point to the insn following the brk. */
119 ex_vec = env->trap_vector;
120 env->pregs[PR_ERP] = env->pc + 2;
124 ex_vec = env->fault_vector;
125 env->pregs[PR_ERP] = env->pc;
129 /* Is the core accepting interrupts? */
130 if (!(env->pregs[PR_CCS] & I_FLAG))
132 /* The interrupt controller gives us the
134 ex_vec = env->interrupt_vector;
135 /* Normal interrupts are taken between
136 TB's. env->pc is valid here. */
137 env->pregs[PR_ERP] = env->pc;
141 if ((env->pregs[PR_CCS] & U_FLAG)) {
142 D(fprintf(logfile, "excp isr=%x PC=%x SP=%x ERP=%x pid=%x ccs=%x cc=%d %x\n",
145 env->pregs[PR_ERP], env->pregs[PR_PID],
147 env->cc_op, env->cc_mask));
150 env->pc = ldl_code(env->pregs[PR_EBP] + ex_vec * 4);
152 if (env->pregs[PR_CCS] & U_FLAG) {
153 /* Swap stack pointers. */
154 env->pregs[PR_USP] = env->regs[R_SP];
155 env->regs[R_SP] = env->ksp;
158 /* Apply the CRIS CCS shift. Clears U if set. */
160 D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
161 __func__, env->pc, ex_vec,
164 env->pregs[PR_ERP]));
167 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
170 struct cris_mmu_result_t res;
172 miss = cris_mmu_translate(&res, env, addr, 0, 0);
175 D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));