2 * CRIS virtual CPU header
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #define TARGET_LONG_BITS 32
28 #define TARGET_HAS_ICE 1
30 #define ELF_MACHINE EM_CRIS
32 #define EXCP_MMU_EXEC 0
33 #define EXCP_MMU_READ 1
34 #define EXCP_MMU_WRITE 2
35 #define EXCP_MMU_FLUSH 3
36 #define EXCP_MMU_FAULT 4
37 #define EXCP_BREAK 16 /* trap. */
39 /* Register aliases. R0 - R15 */
44 /* Support regs, P0 - P15 */
74 #define ALU_FLAGS 0x1F
76 /* Condition codes. */
94 /* Internal flags for the implementation. */
97 #define NB_MMU_MODES 2
99 typedef struct CPUCRISState {
101 /* P0 - P15 are referred to as special registers in the docs. */
104 /* Pseudo register for the PC. Not directly accessable on CRIS. */
107 /* Pseudo register for the kernel stack. */
115 /* Condition flag tracking. */
121 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
123 /* Extended arithmetics. */
128 int interrupt_request;
129 int interrupt_vector;
137 /* FIXME: add a check in the translator to avoid writing to support
138 register sets beyond the 4th. The ISA allows up to 256! but in
139 practice there is no core that implements more than 4.
141 Support function registers are used to control units close to the
142 core. Accesses do not pass down the normal hierarchy.
144 uint32_t sregs[4][16];
146 /* Linear feedback shift reg in the mmu. Used to provide pseudo
147 randomness for the 'hint' the mmu gives to sw for chosing valid
148 sets on TLB refills. */
149 uint32_t mmu_rand_lfsr;
152 * We just store the stores to the tlbset here for later evaluation
153 * when the hw needs access to them.
155 * One for I and another for D.
171 CPUCRISState *cpu_cris_init(const char *cpu_model);
172 int cpu_cris_exec(CPUCRISState *s);
173 void cpu_cris_close(CPUCRISState *s);
174 void do_interrupt(CPUCRISState *env);
175 /* you can call this signal handler from your SIGBUS and SIGSEGV
176 signal handlers to inform the virtual CPU of exceptions. non zero
177 is returned if the signal was handled by the virtual CPU. */
178 int cpu_cris_signal_handler(int host_signum, void *pinfo,
180 void cpu_cris_flush_flags(CPUCRISState *, int);
183 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
187 CC_OP_DYNAMIC, /* Use env->cc_op */
225 void cris_set_irq_level(CPUCRISState *env, int level, uint8_t vector);
226 void cris_set_macsr(CPUCRISState *env, uint32_t val);
227 void cris_switch_sp(CPUCRISState *env);
229 void do_cris_semihosting(CPUCRISState *env, int nr);
232 CRIS_FEATURE_CF_ISA_MUL,
235 static inline int cris_feature(CPUCRISState *env, int feature)
237 return (env->features & (1u << feature)) != 0;
240 void register_cris_insns (CPUCRISState *env);
242 /* CRIS uses 8k pages. */
243 #define TARGET_PAGE_BITS 13
244 #define MMAP_SHIFT TARGET_PAGE_BITS
246 #define CPUState CPUCRISState
247 #define cpu_init cpu_cris_init
248 #define cpu_exec cpu_cris_exec
249 #define cpu_gen_code cpu_cris_gen_code
250 #define cpu_signal_handler cpu_cris_signal_handler
252 /* MMU modes definitions */
253 #define MMU_MODE0_SUFFIX _kernel
254 #define MMU_MODE1_SUFFIX _user
255 #define MMU_USER_IDX 1
256 static inline int cpu_mmu_index (CPUState *env)
258 return !!(env->pregs[PR_CCS] & U_FLAG);
261 /* Support function regs. */
262 #define SFR_RW_GC_CFG 0][0
263 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
264 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
265 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
266 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
267 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
268 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
269 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6