4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 /* internal defines */
31 typedef struct DisasContext {
34 struct TranslationBlock *tb;
37 #define DISAS_JUMP_NEXT 4
39 /* XXX: move that elsewhere */
40 static uint16_t *gen_opc_ptr;
41 static uint32_t *gen_opparam_ptr;
46 #define DEF(s, n, copy_size) INDEX_op_ ## s,
54 static GenOpFunc2 *gen_test_cc[14] = {
71 const uint8_t table_logic_cc[16] = {
90 static GenOpFunc1 *gen_shift_T1_im[4] = {
97 static GenOpFunc1 *gen_shift_T2_im[4] = {
104 static GenOpFunc1 *gen_shift_T1_im_cc[4] = {
105 gen_op_shll_T1_im_cc,
106 gen_op_shrl_T1_im_cc,
107 gen_op_sarl_T1_im_cc,
108 gen_op_rorl_T1_im_cc,
111 static GenOpFunc *gen_shift_T1_T0[4] = {
118 static GenOpFunc *gen_shift_T1_T0_cc[4] = {
119 gen_op_shll_T1_T0_cc,
120 gen_op_shrl_T1_T0_cc,
121 gen_op_sarl_T1_T0_cc,
122 gen_op_rorl_T1_T0_cc,
125 static GenOpFunc *gen_op_movl_TN_reg[3][16] = {
182 static GenOpFunc *gen_op_movl_reg_TN[2][16] = {
221 static GenOpFunc1 *gen_op_movl_TN_im[3] = {
227 static inline void gen_movl_TN_reg(DisasContext *s, int reg, int t)
232 /* normaly, since we updated PC, we need only to add 4 */
233 val = (long)s->pc + 4;
234 gen_op_movl_TN_im[t](val);
236 gen_op_movl_TN_reg[t][reg]();
240 static inline void gen_movl_T0_reg(DisasContext *s, int reg)
242 gen_movl_TN_reg(s, reg, 0);
245 static inline void gen_movl_T1_reg(DisasContext *s, int reg)
247 gen_movl_TN_reg(s, reg, 1);
250 static inline void gen_movl_T2_reg(DisasContext *s, int reg)
252 gen_movl_TN_reg(s, reg, 2);
255 static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)
257 gen_op_movl_reg_TN[t][reg]();
259 s->is_jmp = DISAS_JUMP;
263 static inline void gen_movl_reg_T0(DisasContext *s, int reg)
265 gen_movl_reg_TN(s, reg, 0);
268 static inline void gen_movl_reg_T1(DisasContext *s, int reg)
270 gen_movl_reg_TN(s, reg, 1);
273 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)
277 if (!(insn & (1 << 25))) {
280 if (!(insn & (1 << 23)))
283 gen_op_addl_T1_im(val);
287 shift = (insn >> 7) & 0x1f;
288 gen_movl_T2_reg(s, rm);
290 gen_shift_T2_im[(insn >> 5) & 3](shift);
292 if (!(insn & (1 << 23)))
299 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn)
303 if (insn & (1 << 22)) {
305 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
306 if (!(insn & (1 << 23)))
309 gen_op_addl_T1_im(val);
313 gen_movl_T2_reg(s, rm);
314 if (!(insn & (1 << 23)))
321 static void disas_arm_insn(DisasContext *s)
323 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
332 /* if not always execute, we generate a conditional jump to
334 gen_test_cc[cond ^ 1]((long)s->tb, (long)s->pc);
335 s->is_jmp = DISAS_JUMP_NEXT;
337 if (((insn & 0x0e000000) == 0 &&
338 (insn & 0x00000090) != 0x90) ||
339 ((insn & 0x0e000000) == (1 << 25))) {
340 int set_cc, logic_cc, shiftop;
342 op1 = (insn >> 21) & 0xf;
343 set_cc = (insn >> 20) & 1;
344 logic_cc = table_logic_cc[op1] & set_cc;
346 /* data processing instruction */
347 if (insn & (1 << 25)) {
348 /* immediate operand */
350 shift = ((insn >> 8) & 0xf) * 2;
352 val = (val >> shift) | (val << (32 - shift));
353 gen_op_movl_T1_im(val);
354 /* XXX: is CF modified ? */
358 gen_movl_T1_reg(s, rm);
359 shiftop = (insn >> 5) & 3;
360 if (!(insn & (1 << 4))) {
361 shift = (insn >> 7) & 0x1f;
364 gen_shift_T1_im_cc[shiftop](shift);
366 gen_shift_T1_im[shiftop](shift);
370 rs = (insn >> 8) & 0xf;
371 gen_movl_T0_reg(s, rs);
373 gen_shift_T1_T0_cc[shiftop]();
375 gen_shift_T1_T0[shiftop]();
379 if (op1 != 0x0f && op1 != 0x0d) {
380 rn = (insn >> 16) & 0xf;
381 gen_movl_T0_reg(s, rn);
383 rd = (insn >> 12) & 0xf;
387 gen_movl_reg_T0(s, rd);
389 gen_op_logic_T0_cc();
393 gen_movl_reg_T0(s, rd);
395 gen_op_logic_T0_cc();
399 gen_op_subl_T0_T1_cc();
402 gen_movl_reg_T0(s, rd);
406 gen_op_rsbl_T0_T1_cc();
409 gen_movl_reg_T0(s, rd);
413 gen_op_addl_T0_T1_cc();
416 gen_movl_reg_T0(s, rd);
420 gen_op_adcl_T0_T1_cc();
423 gen_movl_reg_T0(s, rd);
427 gen_op_sbcl_T0_T1_cc();
430 gen_movl_reg_T0(s, rd);
434 gen_op_rscl_T0_T1_cc();
437 gen_movl_reg_T0(s, rd);
442 gen_op_logic_T0_cc();
448 gen_op_logic_T0_cc();
453 gen_op_subl_T0_T1_cc();
458 gen_op_addl_T0_T1_cc();
463 gen_movl_reg_T0(s, rd);
465 gen_op_logic_T0_cc();
468 gen_movl_reg_T1(s, rd);
470 gen_op_logic_T1_cc();
474 gen_movl_reg_T0(s, rd);
476 gen_op_logic_T0_cc();
481 gen_movl_reg_T1(s, rd);
483 gen_op_logic_T1_cc();
487 /* other instructions */
488 op1 = (insn >> 24) & 0xf;
492 sh = (insn >> 5) & 3;
495 rd = (insn >> 16) & 0xf;
496 rn = (insn >> 12) & 0xf;
497 rs = (insn >> 8) & 0xf;
499 if (!(insn & (1 << 23))) {
501 gen_movl_T0_reg(s, rs);
502 gen_movl_T1_reg(s, rm);
504 if (insn & (1 << 21)) {
505 gen_movl_T1_reg(s, rn);
508 if (insn & (1 << 20))
509 gen_op_logic_T0_cc();
510 gen_movl_reg_T0(s, rd);
513 gen_movl_T0_reg(s, rs);
514 gen_movl_T1_reg(s, rm);
515 if (insn & (1 << 22))
516 gen_op_imull_T0_T1();
519 if (insn & (1 << 21))
520 gen_op_addq_T0_T1(rn, rd);
521 if (insn & (1 << 20))
523 gen_movl_reg_T0(s, rn);
524 gen_movl_reg_T1(s, rd);
527 /* SWP instruction */
528 rn = (insn >> 16) & 0xf;
529 rd = (insn >> 12) & 0xf;
532 gen_movl_T0_reg(s, rm);
533 gen_movl_T1_reg(s, rn);
534 if (insn & (1 << 22)) {
539 gen_movl_reg_T0(s, rd);
542 /* load/store half word */
543 rn = (insn >> 16) & 0xf;
544 rd = (insn >> 12) & 0xf;
545 gen_movl_T1_reg(s, rn);
546 if (insn & (1 << 24))
547 gen_add_datah_offset(s, insn);
548 if (insn & (1 << 20)) {
562 gen_movl_reg_T0(s, rd);
565 gen_movl_T0_reg(s, rd);
568 if (!(insn & (1 << 24))) {
569 gen_add_datah_offset(s, insn);
570 gen_movl_reg_T1(s, rn);
571 } else if (insn & (1 << 21)) {
572 gen_movl_reg_T1(s, rn);
580 /* load/store byte/word */
581 rn = (insn >> 16) & 0xf;
582 rd = (insn >> 12) & 0xf;
583 gen_movl_T1_reg(s, rn);
584 if (insn & (1 << 24))
585 gen_add_data_offset(s, insn);
586 if (insn & (1 << 20)) {
588 if (insn & (1 << 22))
592 gen_movl_reg_T0(s, rd);
595 gen_movl_T0_reg(s, rd);
596 if (insn & (1 << 22))
601 if (!(insn & (1 << 24))) {
602 gen_add_data_offset(s, insn);
603 gen_movl_reg_T1(s, rn);
604 } else if (insn & (1 << 21))
605 gen_movl_reg_T1(s, rn); {
612 /* load/store multiple words */
613 /* XXX: store correct base if write back */
614 if (insn & (1 << 22))
615 goto illegal_op; /* only usable in supervisor mode */
616 rn = (insn >> 16) & 0xf;
617 gen_movl_T1_reg(s, rn);
619 /* compute total size */
625 /* XXX: test invalid n == 0 case ? */
626 if (insn & (1 << 23)) {
627 if (insn & (1 << 24)) {
629 gen_op_addl_T1_im(4);
634 if (insn & (1 << 24)) {
636 gen_op_addl_T1_im(-(n * 4));
640 gen_op_addl_T1_im(-((n - 1) * 4));
645 if (insn & (1 << i)) {
646 if (insn & (1 << 20)) {
649 gen_movl_reg_T0(s, i);
653 /* special case: r15 = PC + 12 */
654 val = (long)s->pc + 8;
655 gen_op_movl_TN_im[0](val);
657 gen_movl_T0_reg(s, i);
662 /* no need to add after the last transfer */
664 gen_op_addl_T1_im(4);
667 if (insn & (1 << 21)) {
669 if (insn & (1 << 23)) {
670 if (insn & (1 << 24)) {
674 gen_op_addl_T1_im(4);
677 if (insn & (1 << 24)) {
680 gen_op_addl_T1_im(-((n - 1) * 4));
683 gen_op_addl_T1_im(-(n * 4));
686 gen_movl_reg_T1(s, rn);
695 /* branch (and link) */
697 if (insn & (1 << 24)) {
698 gen_op_movl_T0_im(val);
699 gen_op_movl_reg_TN[0][14]();
701 offset = (((int)insn << 8) >> 8);
702 val += (offset << 2) + 4;
703 gen_op_jmp((long)s->tb, val);
704 s->is_jmp = DISAS_TB_JUMP;
709 gen_op_movl_T0_im((long)s->pc);
710 gen_op_movl_reg_TN[0][15]();
712 s->is_jmp = DISAS_JUMP;
716 gen_op_movl_T0_im((long)s->pc - 4);
717 gen_op_movl_reg_TN[0][15]();
719 s->is_jmp = DISAS_JUMP;
725 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
726 basic block 'tb'. If search_pc is TRUE, also generate PC
727 information for each intermediate instruction. */
728 static inline int gen_intermediate_code_internal(CPUState *env,
729 TranslationBlock *tb,
732 DisasContext dc1, *dc = &dc1;
733 uint16_t *gen_opc_end;
737 /* generate intermediate code */
738 pc_start = (uint8_t *)tb->pc;
742 gen_opc_ptr = gen_opc_buf;
743 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
744 gen_opparam_ptr = gen_opparam_buf;
746 dc->is_jmp = DISAS_NEXT;
751 j = gen_opc_ptr - gen_opc_buf;
755 gen_opc_instr_start[lj++] = 0;
757 gen_opc_pc[lj] = (uint32_t)dc->pc;
758 gen_opc_instr_start[lj] = 1;
761 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
762 (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
764 case DISAS_JUMP_NEXT:
766 gen_op_jmp((long)dc->tb, (long)dc->pc);
770 /* indicate that the hash table must be used to find the next TB */
775 /* nothing more to generate */
778 *gen_opc_ptr = INDEX_op_end;
781 if (loglevel & CPU_LOG_TB_IN_ASM) {
782 fprintf(logfile, "----------------\n");
783 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
784 disas(logfile, pc_start, dc->pc - pc_start, 0, 0);
785 fprintf(logfile, "\n");
786 if (loglevel & (CPU_LOG_TB_OP)) {
787 fprintf(logfile, "OP:\n");
788 dump_ops(gen_opc_buf, gen_opparam_buf);
789 fprintf(logfile, "\n");
794 tb->size = dc->pc - pc_start;
798 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
800 return gen_intermediate_code_internal(env, tb, 0);
803 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
805 return gen_intermediate_code_internal(env, tb, 1);
808 CPUARMState *cpu_arm_init(void)
814 env = malloc(sizeof(CPUARMState));
817 memset(env, 0, sizeof(CPUARMState));
821 void cpu_arm_close(CPUARMState *env)
826 void cpu_arm_dump_state(CPUARMState *env, FILE *f, int flags)
831 fprintf(f, "R%02d=%08x", i, env->regs[i]);
837 fprintf(f, "PSR=%08x %c%c%c%c\n",
839 env->cpsr & (1 << 31) ? 'N' : '-',
840 env->cpsr & (1 << 30) ? 'Z' : '-',
841 env->cpsr & (1 << 29) ? 'C' : '-',
842 env->cpsr & (1 << 28) ? 'V' : '-');
845 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)