2 * ARM virtual CPU header
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define TARGET_LONG_BITS 32
25 #define ELF_MACHINE EM_ARM
29 #include "softfloat.h"
31 #define TARGET_HAS_ICE 1
33 #define EXCP_UDEF 1 /* undefined instruction */
34 #define EXCP_SWI 2 /* software interrupt */
35 #define EXCP_PREFETCH_ABORT 3
36 #define EXCP_DATA_ABORT 4
41 /* We currently assume float and double are IEEE single and double
42 precision respectively.
43 Doing runtime conversions is tricky because VFP registers may contain
44 integer values (eg. as the result of a FTOSI instruction).
45 s<2n> maps to the least significant half of d<n>
46 s<2n+1> maps to the most significant half of d<n>
49 typedef struct CPUARMState {
50 /* Regs for current mode. */
52 /* Frequently accessed CPSR bits are stored separately for efficiently.
53 This contains all the other bits. Use cpsr_{read,write} to access
55 uint32_t uncached_cpsr;
58 /* Banked registers. */
59 uint32_t banked_spsr[6];
60 uint32_t banked_r13[6];
61 uint32_t banked_r14[6];
63 /* These hold r8-r12. */
67 /* cpsr flag cache for faster execution */
68 uint32_t CF; /* 0 or 1 */
69 uint32_t VF; /* V is the bit 31. All other bits are undefined */
70 uint32_t NZF; /* N is bit 31. Z is computed from NZF */
71 uint32_t QF; /* 0 or 1 */
73 int thumb; /* 0 = arm mode, 1 = thumb mode */
75 /* System control coprocessor (cp15) */
78 uint32_t c1_sys; /* System control register. */
79 uint32_t c1_coproc; /* Coprocessor access register. */
80 uint32_t c2; /* MMU translation table base. */
81 uint32_t c3; /* MMU domain access control register. */
82 uint32_t c5_insn; /* Fault status registers. */
84 uint32_t c6_insn; /* Fault address registers. */
86 uint32_t c9_insn; /* Cache lockdown registers. */
88 uint32_t c13_fcse; /* FCSE PID. */
89 uint32_t c13_context; /* Context ID. */
92 /* Internal CPU feature flags. */
95 /* exception/interrupt handling */
98 int interrupt_request;
102 /* VFP coprocessor state. */
107 /* We store these fpcsr fields separately for convenience. */
111 /* Temporary variables if we don't have spare fp regs. */
112 float32 tmp0s, tmp1s;
113 float64 tmp0d, tmp1d;
115 float_status fp_status;
118 #if defined(CONFIG_USER_ONLY)
119 /* For usermode syscall translation. */
125 /* These fields after the common ones so thes are preserved on reset. */
127 const char *kernel_filename;
128 const char *kernel_cmdline;
129 const char *initrd_filename;
133 CPUARMState *cpu_arm_init(void);
134 int cpu_arm_exec(CPUARMState *s);
135 void cpu_arm_close(CPUARMState *s);
136 void do_interrupt(CPUARMState *);
137 void switch_mode(CPUARMState *, int);
139 /* you can call this signal handler from your SIGBUS and SIGSEGV
140 signal handlers to inform the virtual CPU of exceptions. non zero
141 is returned if the signal was handled by the virtual CPU. */
142 int cpu_arm_signal_handler(int host_signum, void *pinfo,
145 #define CPSR_M (0x1f)
146 #define CPSR_T (1 << 5)
147 #define CPSR_F (1 << 6)
148 #define CPSR_I (1 << 7)
149 #define CPSR_A (1 << 8)
150 #define CPSR_E (1 << 9)
151 #define CPSR_IT_2_7 (0xfc00)
152 /* Bits 20-23 reserved. */
153 #define CPSR_J (1 << 24)
154 #define CPSR_IT_0_1 (3 << 25)
155 #define CPSR_Q (1 << 27)
156 #define CPSR_NZCV (0xf << 28)
158 #define CACHED_CPSR_BITS (CPSR_T | CPSR_Q | CPSR_NZCV)
159 /* Return the current CPSR value. */
160 static inline uint32_t cpsr_read(CPUARMState *env)
163 ZF = (env->NZF == 0);
164 return env->uncached_cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
165 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
169 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
170 static inline void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
172 /* NOTE: N = 1 and Z = 1 cannot be stored currently */
173 if (mask & CPSR_NZCV) {
174 env->NZF = (val & 0xc0000000) ^ 0x40000000;
175 env->CF = (val >> 29) & 1;
176 env->VF = (val << 3) & 0x80000000;
179 env->QF = ((val & CPSR_Q) != 0);
181 env->thumb = ((val & CPSR_T) != 0);
183 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
184 switch_mode(env, val & CPSR_M);
186 mask &= ~CACHED_CPSR_BITS;
187 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
191 ARM_CPU_MODE_USR = 0x10,
192 ARM_CPU_MODE_FIQ = 0x11,
193 ARM_CPU_MODE_IRQ = 0x12,
194 ARM_CPU_MODE_SVC = 0x13,
195 ARM_CPU_MODE_ABT = 0x17,
196 ARM_CPU_MODE_UND = 0x1b,
197 ARM_CPU_MODE_SYS = 0x1f
200 /* VFP system registers. */
201 #define ARM_VFP_FPSID 0
202 #define ARM_VFP_FPSCR 1
203 #define ARM_VFP_FPEXC 8
204 #define ARM_VFP_FPINST 9
205 #define ARM_VFP_FPINST2 10
210 ARM_FEATURE_AUXCR /* ARM1026 Auxiliary control register. */
213 static inline int arm_feature(CPUARMState *env, int feature)
215 return (env->features & (1u << feature)) != 0;
218 void arm_cpu_list(void);
219 void cpu_arm_set_model(CPUARMState *env, const char *name);
221 #define ARM_CPUID_ARM1026 0x4106a262
222 #define ARM_CPUID_ARM926 0x41069265
224 #if defined(CONFIG_USER_ONLY)
225 #define TARGET_PAGE_BITS 12
227 /* The ARM MMU allows 1k pages. */
228 /* ??? Linux doesn't actually use these, and they're deprecated in recent
229 architecture revisions. Maybe an a configure option to disable them. */
230 #define TARGET_PAGE_BITS 10