2 * Alpha emulation cpu translation for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include "host-utils.h"
31 #include "qemu-common.h"
33 #define DO_SINGLE_STEP
35 #define ALPHA_DEBUG_DISAS
38 typedef struct DisasContext DisasContext;
42 #if !defined (CONFIG_USER_ONLY)
48 /* global register indexes */
50 static TCGv cpu_ir[31];
53 /* dyngen register indexes */
57 static char cpu_reg_names[10*4+21*5];
59 #include "gen-icount.h"
61 static void alpha_translate_init(void)
65 static int done_init = 0;
70 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
72 #if TARGET_LONG_BITS > HOST_LONG_BITS
73 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
74 offsetof(CPUState, t0), "T0");
75 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
76 offsetof(CPUState, t1), "T1");
77 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
78 offsetof(CPUState, t2), "T2");
80 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
81 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
82 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2");
86 for (i = 0; i < 31; i++) {
87 sprintf(p, "ir%d", i);
88 cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
89 offsetof(CPUState, ir[i]), p);
90 p += (i < 10) ? 4 : 5;
93 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
94 offsetof(CPUState, pc), "pc");
96 /* register helpers */
98 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
104 static always_inline void gen_op_nop (void)
106 #if defined(GENERATE_NOP)
111 #define GEN32(func, NAME) \
112 static GenOpFunc *NAME ## _table [32] = { \
113 NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
114 NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
115 NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
116 NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
117 NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
118 NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
119 NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
120 NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
122 static always_inline void func (int n) \
124 NAME ## _table[n](); \
128 /* Special hacks for fir31 */
129 #define gen_op_load_FT0_fir31 gen_op_reset_FT0
130 #define gen_op_load_FT1_fir31 gen_op_reset_FT1
131 #define gen_op_load_FT2_fir31 gen_op_reset_FT2
132 #define gen_op_store_FT0_fir31 gen_op_nop
133 #define gen_op_store_FT1_fir31 gen_op_nop
134 #define gen_op_store_FT2_fir31 gen_op_nop
135 #define gen_op_cmov_fir31 gen_op_nop
136 GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
137 GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
138 GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
139 GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
140 GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
141 GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
142 GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
144 static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
148 gen_op_load_FT0_fir(firn);
151 gen_op_load_FT1_fir(firn);
154 gen_op_load_FT2_fir(firn);
159 static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
163 gen_op_store_FT0_fir(firn);
166 gen_op_store_FT1_fir(firn);
169 gen_op_store_FT2_fir(firn);
175 #if defined(CONFIG_USER_ONLY)
176 #define OP_LD_TABLE(width) \
177 static GenOpFunc *gen_op_ld##width[] = { \
178 &gen_op_ld##width##_raw, \
180 #define OP_ST_TABLE(width) \
181 static GenOpFunc *gen_op_st##width[] = { \
182 &gen_op_st##width##_raw, \
185 #define OP_LD_TABLE(width) \
186 static GenOpFunc *gen_op_ld##width[] = { \
187 &gen_op_ld##width##_kernel, \
188 &gen_op_ld##width##_executive, \
189 &gen_op_ld##width##_supervisor, \
190 &gen_op_ld##width##_user, \
192 #define OP_ST_TABLE(width) \
193 static GenOpFunc *gen_op_st##width[] = { \
194 &gen_op_st##width##_kernel, \
195 &gen_op_st##width##_executive, \
196 &gen_op_st##width##_supervisor, \
197 &gen_op_st##width##_user, \
201 #define GEN_LD(width) \
202 OP_LD_TABLE(width); \
203 static always_inline void gen_ld##width (DisasContext *ctx) \
205 (*gen_op_ld##width[ctx->mem_idx])(); \
208 #define GEN_ST(width) \
209 OP_ST_TABLE(width); \
210 static always_inline void gen_st##width (DisasContext *ctx) \
212 (*gen_op_st##width[ctx->mem_idx])(); \
230 #if 0 /* currently unused */
241 static always_inline void _gen_op_bcond (DisasContext *ctx)
243 #if 0 // Qemu does not know how to do this...
244 gen_op_bcond(ctx->pc);
246 gen_op_bcond(ctx->pc >> 32, ctx->pc);
250 static always_inline void gen_excp (DisasContext *ctx,
251 int exception, int error_code)
255 tcg_gen_movi_i64(cpu_pc, ctx->pc);
256 tmp1 = tcg_const_i32(exception);
257 tmp2 = tcg_const_i32(error_code);
258 tcg_gen_helper_0_2(helper_excp, tmp1, tmp2);
263 static always_inline void gen_invalid (DisasContext *ctx)
265 gen_excp(ctx, EXCP_OPCDEC, 0);
268 static always_inline void gen_load_mem (DisasContext *ctx,
269 void (*gen_load_op)(DisasContext *ctx),
270 int ra, int rb, int32_t disp16,
273 if (ra == 31 && disp16 == 0) {
278 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
280 tcg_gen_movi_i64(cpu_T[0], disp16);
282 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
285 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
289 static always_inline void gen_store_mem (DisasContext *ctx,
290 void (*gen_store_op)(DisasContext *ctx),
291 int ra, int rb, int32_t disp16,
295 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
297 tcg_gen_movi_i64(cpu_T[0], disp16);
299 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
301 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
303 tcg_gen_movi_i64(cpu_T[1], 0);
304 (*gen_store_op)(ctx);
307 static always_inline void gen_load_fmem (DisasContext *ctx,
308 void (*gen_load_fop)(DisasContext *ctx),
309 int ra, int rb, int32_t disp16)
312 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
314 tcg_gen_movi_i64(cpu_T[0], disp16);
315 (*gen_load_fop)(ctx);
316 gen_store_fir(ctx, ra, 1);
319 static always_inline void gen_store_fmem (DisasContext *ctx,
320 void (*gen_store_fop)(DisasContext *ctx),
321 int ra, int rb, int32_t disp16)
324 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
326 tcg_gen_movi_i64(cpu_T[0], disp16);
327 gen_load_fir(ctx, ra, 1);
328 (*gen_store_fop)(ctx);
331 static always_inline void gen_bcond (DisasContext *ctx,
333 int ra, int32_t disp16, int mask)
337 l1 = gen_new_label();
338 l2 = gen_new_label();
339 if (likely(ra != 31)) {
341 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
342 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
343 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
346 tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
348 /* Very uncommon case - Do not bother to optimize. */
349 TCGv tmp = tcg_const_i64(0);
350 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
353 tcg_gen_movi_i64(cpu_pc, ctx->pc);
356 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
360 static always_inline void gen_fbcond (DisasContext *ctx,
361 void (*gen_test_op)(void),
362 int ra, int32_t disp16)
364 tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
365 gen_load_fir(ctx, ra, 0);
370 static always_inline void gen_arith3 (DisasContext *ctx,
371 void (*gen_arith_op)(void),
372 int ra, int rb, int rc,
373 int islit, uint8_t lit)
376 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
378 tcg_gen_movi_i64(cpu_T[0], 0);
380 tcg_gen_movi_i64(cpu_T[1], lit);
382 tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
385 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
388 static always_inline void gen_cmov (DisasContext *ctx,
390 int ra, int rb, int rc,
391 int islit, uint8_t lit, int mask)
395 if (unlikely(rc == 31))
398 l1 = gen_new_label();
402 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
403 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
404 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
407 tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
409 /* Very uncommon case - Do not bother to optimize. */
410 TCGv tmp = tcg_const_i64(0);
411 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
416 tcg_gen_movi_i64(cpu_ir[rc], lit);
418 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
422 static always_inline void gen_farith2 (DisasContext *ctx,
423 void (*gen_arith_fop)(void),
426 gen_load_fir(ctx, rb, 0);
428 gen_store_fir(ctx, rc, 0);
431 static always_inline void gen_farith3 (DisasContext *ctx,
432 void (*gen_arith_fop)(void),
433 int ra, int rb, int rc)
435 gen_load_fir(ctx, ra, 0);
436 gen_load_fir(ctx, rb, 1);
438 gen_store_fir(ctx, rc, 0);
441 static always_inline void gen_fcmov (DisasContext *ctx,
442 void (*gen_test_fop)(void),
443 int ra, int rb, int rc)
445 gen_load_fir(ctx, ra, 0);
446 gen_load_fir(ctx, rb, 1);
451 static always_inline void gen_fti (DisasContext *ctx,
452 void (*gen_move_fop)(void),
455 gen_load_fir(ctx, rc, 0);
458 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
461 static always_inline void gen_itf (DisasContext *ctx,
462 void (*gen_move_fop)(void),
466 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
468 tcg_gen_movi_i64(cpu_T[0], 0);
470 gen_store_fir(ctx, rc, 0);
473 /* EXTWH, EXTWH, EXTLH, EXTQH */
474 static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
475 int ra, int rb, int rc,
476 int islit, uint8_t lit)
478 if (unlikely(rc == 31))
484 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
486 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
489 tmp1 = tcg_temp_new(TCG_TYPE_I64);
490 tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
491 tcg_gen_shli_i64(tmp1, tmp1, 3);
492 tmp2 = tcg_const_i64(64);
493 tcg_gen_sub_i64(tmp1, tmp2, tmp1);
495 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
499 tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
501 tcg_gen_movi_i64(cpu_ir[rc], 0);
504 /* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
505 static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
506 int ra, int rb, int rc,
507 int islit, uint8_t lit)
509 if (unlikely(rc == 31))
514 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
516 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
517 tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
518 tcg_gen_shli_i64(tmp, tmp, 3);
519 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
523 tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]);
525 tcg_gen_movi_i64(cpu_ir[rc], 0);
528 /* Code to call byte manipulation helpers, used by:
529 INSWH, INSLH, INSQH, INSBL, INSWL, INSLL, INSQL,
530 MSKWH, MSKLH, MSKQH, MSKBL, MSKWL, MSKLL, MSKQL,
533 WARNING: it assumes that when ra31 is used, the result is 0.
535 static always_inline void gen_byte_manipulation(void *helper,
536 int ra, int rb, int rc,
537 int islit, uint8_t lit)
539 if (unlikely(rc == 31))
544 TCGv tmp = tcg_const_i64(lit);
545 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp);
548 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
550 tcg_gen_movi_i64(cpu_ir[rc], 0);
553 static always_inline void gen_cmp(TCGCond cond,
554 int ra, int rb, int rc,
555 int islit, int8_t lit)
560 if (unlikely(rc == 31))
563 l1 = gen_new_label();
564 l2 = gen_new_label();
567 tmp = tcg_temp_new(TCG_TYPE_I64);
568 tcg_gen_mov_i64(tmp, cpu_ir[ra]);
570 tmp = tcg_const_i64(0);
572 tcg_gen_brcondi_i64(cond, tmp, lit, l1);
574 tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1);
576 tcg_gen_movi_i64(cpu_ir[rc], 0);
579 tcg_gen_movi_i64(cpu_ir[rc], 1);
583 static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
586 int32_t disp21, disp16, disp12;
588 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
592 /* Decode all instruction fields */
594 ra = (insn >> 21) & 0x1F;
595 rb = (insn >> 16) & 0x1F;
597 sbz = (insn >> 13) & 0x07;
598 islit = (insn >> 12) & 1;
599 if (rb == 31 && !islit) {
603 lit = (insn >> 13) & 0xFF;
604 palcode = insn & 0x03FFFFFF;
605 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
606 disp16 = (int16_t)(insn & 0x0000FFFF);
607 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
608 fn16 = insn & 0x0000FFFF;
609 fn11 = (insn >> 5) & 0x000007FF;
611 fn7 = (insn >> 5) & 0x0000007F;
612 fn2 = (insn >> 5) & 0x00000003;
614 #if defined ALPHA_DEBUG_DISAS
615 if (logfile != NULL) {
616 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
617 opc, ra, rb, rc, disp16);
623 if (palcode >= 0x80 && palcode < 0xC0) {
624 /* Unprivileged PAL call */
625 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
626 #if !defined (CONFIG_USER_ONLY)
627 } else if (palcode < 0x40) {
628 /* Privileged PAL code */
629 if (ctx->mem_idx & 1)
632 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
635 /* Invalid PAL call */
663 if (likely(ra != 31)) {
665 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
667 tcg_gen_movi_i64(cpu_ir[ra], disp16);
672 if (likely(ra != 31)) {
674 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
676 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
681 if (!(ctx->amask & AMASK_BWX))
683 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
687 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
691 if (!(ctx->amask & AMASK_BWX))
693 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
697 if (!(ctx->amask & AMASK_BWX))
699 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
703 if (!(ctx->amask & AMASK_BWX))
705 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
709 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
715 if (likely(rc != 31)) {
718 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
719 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
721 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
722 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
726 tcg_gen_movi_i64(cpu_ir[rc], lit);
728 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
734 if (likely(rc != 31)) {
736 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
737 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
739 tcg_gen_addi_i64(tmp, tmp, lit);
741 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
742 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
746 tcg_gen_movi_i64(cpu_ir[rc], lit);
748 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
754 if (likely(rc != 31)) {
757 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
759 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
760 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
763 tcg_gen_movi_i64(cpu_ir[rc], -lit);
765 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
766 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
772 if (likely(rc != 31)) {
774 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
775 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
777 tcg_gen_subi_i64(tmp, tmp, lit);
779 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
780 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
784 tcg_gen_movi_i64(cpu_ir[rc], -lit);
786 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
787 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
794 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
798 if (likely(rc != 31)) {
800 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
801 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
803 tcg_gen_addi_i64(tmp, tmp, lit);
805 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
806 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
810 tcg_gen_movi_i64(cpu_ir[rc], lit);
812 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
818 if (likely(rc != 31)) {
820 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
821 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
823 tcg_gen_subi_i64(tmp, tmp, lit);
825 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
826 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
830 tcg_gen_movi_i64(cpu_ir[rc], -lit);
832 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
833 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
840 gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit);
844 if (likely(rc != 31)) {
847 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
849 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
852 tcg_gen_movi_i64(cpu_ir[rc], lit);
854 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
860 if (likely(rc != 31)) {
862 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
863 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
865 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
867 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
871 tcg_gen_movi_i64(cpu_ir[rc], lit);
873 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
879 if (likely(rc != 31)) {
882 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
884 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
887 tcg_gen_movi_i64(cpu_ir[rc], -lit);
889 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
895 if (likely(rc != 31)) {
897 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
898 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
900 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
902 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
906 tcg_gen_movi_i64(cpu_ir[rc], -lit);
908 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
914 gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit);
918 if (likely(rc != 31)) {
920 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
921 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
923 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
925 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
929 tcg_gen_movi_i64(cpu_ir[rc], lit);
931 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
937 if (likely(rc != 31)) {
939 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
940 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
942 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
944 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
948 tcg_gen_movi_i64(cpu_ir[rc], -lit);
950 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
956 gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit);
960 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
964 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
968 gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit);
972 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
976 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
980 gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit);
990 if (likely(rc != 31)) {
992 tcg_gen_movi_i64(cpu_ir[rc], 0);
994 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
996 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1001 if (likely(rc != 31)) {
1004 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1006 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1007 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1008 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1012 tcg_gen_movi_i64(cpu_ir[rc], 0);
1017 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
1021 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1);
1025 if (likely(rc != 31)) {
1028 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1030 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1033 tcg_gen_movi_i64(cpu_ir[rc], lit);
1035 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1041 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0);
1045 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
1049 if (likely(rc != 31)) {
1052 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1054 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1055 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1056 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1061 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1063 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1069 if (likely(rc != 31)) {
1072 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1074 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1077 tcg_gen_movi_i64(cpu_ir[rc], lit);
1079 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1085 gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0);
1089 gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0);
1093 if (likely(rc != 31)) {
1096 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1098 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1099 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1100 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1105 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1107 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1113 if (likely(rc != 31)) {
1115 tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit));
1117 tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]);
1122 gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0);
1126 gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0);
1131 tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]);
1141 gen_byte_manipulation(helper_mskbl, ra, rb, rc, islit, lit);
1145 gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit);
1149 gen_byte_manipulation(helper_insbl, ra, rb, rc, islit, lit);
1153 gen_byte_manipulation(helper_mskwl, ra, rb, rc, islit, lit);
1157 gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1161 gen_byte_manipulation(helper_inswl, ra, rb, rc, islit, lit);
1165 gen_byte_manipulation(helper_mskll, ra, rb, rc, islit, lit);
1169 gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
1173 gen_byte_manipulation(helper_insll, ra, rb, rc, islit, lit);
1177 gen_byte_manipulation(helper_zap, ra, rb, rc, islit, lit);
1181 gen_byte_manipulation(helper_zapnot, ra, rb, rc, islit, lit);
1185 gen_byte_manipulation(helper_mskql, ra, rb, rc, islit, lit);
1189 if (likely(rc != 31)) {
1192 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1194 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1195 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1196 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
1197 tcg_temp_free(shift);
1200 tcg_gen_movi_i64(cpu_ir[rc], 0);
1205 gen_ext_l(NULL, ra, rb, rc, islit, lit);
1209 if (likely(rc != 31)) {
1212 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1214 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1215 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1216 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
1217 tcg_temp_free(shift);
1220 tcg_gen_movi_i64(cpu_ir[rc], 0);
1225 gen_byte_manipulation(helper_insql, ra, rb, rc, islit, lit);
1229 if (likely(rc != 31)) {
1232 tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1234 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1235 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1236 tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
1237 tcg_temp_free(shift);
1240 tcg_gen_movi_i64(cpu_ir[rc], 0);
1245 gen_byte_manipulation(helper_mskwh, ra, rb, rc, islit, lit);
1249 gen_byte_manipulation(helper_inswh, ra, rb, rc, islit, lit);
1253 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1257 gen_byte_manipulation(helper_msklh, ra, rb, rc, islit, lit);
1261 gen_byte_manipulation(helper_inslh, ra, rb, rc, islit, lit);
1265 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
1269 gen_byte_manipulation(helper_mskqh, ra, rb, rc, islit, lit);
1273 gen_byte_manipulation(helper_insqh, ra, rb, rc, islit, lit);
1277 gen_ext_h(NULL, ra, rb, rc, islit, lit);
1287 if (likely(rc != 31)) {
1289 tcg_gen_movi_i64(cpu_ir[rc], 0);
1292 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1294 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1295 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1301 if (likely(rc != 31)) {
1303 tcg_gen_movi_i64(cpu_ir[rc], 0);
1305 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1307 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1312 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
1316 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
1320 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
1327 switch (fpfn) { /* f11 & 0x3F */
1330 if (!(ctx->amask & AMASK_FIX))
1332 gen_itf(ctx, &gen_op_itofs, ra, rc);
1336 if (!(ctx->amask & AMASK_FIX))
1338 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
1342 if (!(ctx->amask & AMASK_FIX))
1344 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
1348 if (!(ctx->amask & AMASK_FIX))
1351 gen_itf(ctx, &gen_op_itoff, ra, rc);
1358 if (!(ctx->amask & AMASK_FIX))
1360 gen_itf(ctx, &gen_op_itoft, ra, rc);
1364 if (!(ctx->amask & AMASK_FIX))
1366 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1370 if (!(ctx->amask & AMASK_FIX))
1372 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1379 /* VAX floating point */
1380 /* XXX: rounding mode and trap are ignored (!) */
1381 switch (fpfn) { /* f11 & 0x3F */
1384 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1388 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1392 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1396 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1401 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1408 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1412 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1416 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1420 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1424 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1428 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1432 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1436 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1441 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1448 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1452 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1456 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1463 /* IEEE floating-point */
1464 /* XXX: rounding mode and traps are ignored (!) */
1465 switch (fpfn) { /* f11 & 0x3F */
1468 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1472 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1476 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1480 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1484 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1488 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1492 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1496 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1500 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1504 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1508 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1512 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1515 /* XXX: incorrect */
1516 if (fn11 == 0x2AC) {
1518 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1521 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1526 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1530 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1534 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1544 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1549 if (ra == 31 && rc == 31) {
1554 gen_load_fir(ctx, rb, 0);
1555 gen_store_fir(ctx, rc, 0);
1558 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1563 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1567 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1571 gen_load_fir(ctx, ra, 0);
1572 gen_op_store_fpcr();
1577 gen_store_fir(ctx, ra, 0);
1581 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1585 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1589 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1593 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1597 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1601 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1605 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1609 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1613 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1620 switch ((uint16_t)disp16) {
1623 /* No-op. Just exit from the current tb */
1628 /* No-op. Just exit from the current tb */
1650 tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]);
1655 tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]);
1659 /* XXX: TODO: evict tb cache at address rb */
1669 tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]);
1680 /* HW_MFPR (PALcode) */
1681 #if defined (CONFIG_USER_ONLY)
1686 gen_op_mfpr(insn & 0xFF);
1688 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
1693 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1695 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1697 tcg_gen_movi_i64(cpu_pc, 0);
1698 /* Those four jumps only differ by the branch prediction hint */
1716 /* HW_LD (PALcode) */
1717 #if defined (CONFIG_USER_ONLY)
1723 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1725 tcg_gen_movi_i64(cpu_T[0], 0);
1726 tcg_gen_movi_i64(cpu_T[1], disp12);
1727 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
1728 switch ((insn >> 12) & 0xF) {
1730 /* Longword physical access */
1734 /* Quadword physical access */
1738 /* Longword physical access with lock */
1742 /* Quadword physical access with lock */
1746 /* Longword virtual PTE fetch */
1747 gen_op_ldl_kernel();
1750 /* Quadword virtual PTE fetch */
1751 gen_op_ldq_kernel();
1760 /* Longword virtual access */
1761 gen_op_ld_phys_to_virt();
1765 /* Quadword virtual access */
1766 gen_op_ld_phys_to_virt();
1770 /* Longword virtual access with protection check */
1774 /* Quadword virtual access with protection check */
1778 /* Longword virtual access with altenate access mode */
1779 gen_op_set_alt_mode();
1780 gen_op_ld_phys_to_virt();
1782 gen_op_restore_mode();
1785 /* Quadword virtual access with altenate access mode */
1786 gen_op_set_alt_mode();
1787 gen_op_ld_phys_to_virt();
1789 gen_op_restore_mode();
1792 /* Longword virtual access with alternate access mode and
1795 gen_op_set_alt_mode();
1797 gen_op_restore_mode();
1800 /* Quadword virtual access with alternate access mode and
1803 gen_op_set_alt_mode();
1805 gen_op_restore_mode();
1809 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
1816 if (!(ctx->amask & AMASK_BWX))
1818 if (likely(rc != 31)) {
1820 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
1822 tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
1827 if (!(ctx->amask & AMASK_BWX))
1829 if (likely(rc != 31)) {
1831 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
1833 tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
1838 if (!(ctx->amask & AMASK_CIX))
1840 if (likely(rc != 31)) {
1842 tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
1844 tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]);
1849 if (!(ctx->amask & AMASK_MVI))
1856 if (!(ctx->amask & AMASK_CIX))
1858 if (likely(rc != 31)) {
1860 tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
1862 tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]);
1867 if (!(ctx->amask & AMASK_CIX))
1869 if (likely(rc != 31)) {
1871 tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
1873 tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]);
1878 if (!(ctx->amask & AMASK_MVI))
1885 if (!(ctx->amask & AMASK_MVI))
1892 if (!(ctx->amask & AMASK_MVI))
1899 if (!(ctx->amask & AMASK_MVI))
1906 if (!(ctx->amask & AMASK_MVI))
1913 if (!(ctx->amask & AMASK_MVI))
1920 if (!(ctx->amask & AMASK_MVI))
1927 if (!(ctx->amask & AMASK_MVI))
1934 if (!(ctx->amask & AMASK_MVI))
1941 if (!(ctx->amask & AMASK_MVI))
1948 if (!(ctx->amask & AMASK_MVI))
1955 if (!(ctx->amask & AMASK_MVI))
1962 if (!(ctx->amask & AMASK_FIX))
1964 gen_fti(ctx, &gen_op_ftoit, ra, rb);
1968 if (!(ctx->amask & AMASK_FIX))
1970 gen_fti(ctx, &gen_op_ftois, ra, rb);
1977 /* HW_MTPR (PALcode) */
1978 #if defined (CONFIG_USER_ONLY)
1984 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
1986 tcg_gen_movi_i64(cpu_T[0], 0);
1987 gen_op_mtpr(insn & 0xFF);
1992 /* HW_REI (PALcode) */
1993 #if defined (CONFIG_USER_ONLY)
2003 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
2005 tcg_gen_movi_i64(cpu_T[0], 0);
2006 tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
2007 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
2014 /* HW_ST (PALcode) */
2015 #if defined (CONFIG_USER_ONLY)
2021 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
2023 tcg_gen_movi_i64(cpu_T[0], disp12);
2025 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
2027 tcg_gen_movi_i64(cpu_T[1], 0);
2028 switch ((insn >> 12) & 0xF) {
2030 /* Longword physical access */
2034 /* Quadword physical access */
2038 /* Longword physical access with lock */
2042 /* Quadword physical access with lock */
2046 /* Longword virtual access */
2047 gen_op_st_phys_to_virt();
2051 /* Quadword virtual access */
2052 gen_op_st_phys_to_virt();
2074 /* Longword virtual access with alternate access mode */
2075 gen_op_set_alt_mode();
2076 gen_op_st_phys_to_virt();
2078 gen_op_restore_mode();
2081 /* Quadword virtual access with alternate access mode */
2082 gen_op_set_alt_mode();
2083 gen_op_st_phys_to_virt();
2085 gen_op_restore_mode();
2100 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
2108 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
2115 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
2119 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
2124 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
2132 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
2139 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
2143 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
2147 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
2151 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
2155 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
2159 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
2163 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
2167 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
2171 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
2175 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
2180 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2181 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2186 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
2191 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
2196 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
2202 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2203 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
2208 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
2213 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
2218 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
2223 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
2228 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
2233 gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
2238 gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
2243 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
2248 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
2253 gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
2258 gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
2270 static always_inline void gen_intermediate_code_internal (CPUState *env,
2271 TranslationBlock *tb,
2274 #if defined ALPHA_DEBUG_DISAS
2275 static int insn_count;
2277 DisasContext ctx, *ctxp = &ctx;
2278 target_ulong pc_start;
2280 uint16_t *gen_opc_end;
2287 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2289 ctx.amask = env->amask;
2290 #if defined (CONFIG_USER_ONLY)
2293 ctx.mem_idx = ((env->ps >> 3) & 3);
2294 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2297 max_insns = tb->cflags & CF_COUNT_MASK;
2299 max_insns = CF_COUNT_MASK;
2302 for (ret = 0; ret == 0;) {
2303 if (env->nb_breakpoints > 0) {
2304 for(j = 0; j < env->nb_breakpoints; j++) {
2305 if (env->breakpoints[j] == ctx.pc) {
2306 gen_excp(&ctx, EXCP_DEBUG, 0);
2312 j = gen_opc_ptr - gen_opc_buf;
2316 gen_opc_instr_start[lj++] = 0;
2317 gen_opc_pc[lj] = ctx.pc;
2318 gen_opc_instr_start[lj] = 1;
2319 gen_opc_icount[lj] = num_insns;
2322 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
2324 #if defined ALPHA_DEBUG_DISAS
2326 if (logfile != NULL) {
2327 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
2328 ctx.pc, ctx.mem_idx);
2331 insn = ldl_code(ctx.pc);
2332 #if defined ALPHA_DEBUG_DISAS
2334 if (logfile != NULL) {
2335 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
2340 ret = translate_one(ctxp, insn);
2343 /* if we reach a page boundary or are single stepping, stop
2346 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2347 (env->singlestep_enabled) ||
2348 num_insns >= max_insns) {
2351 #if defined (DO_SINGLE_STEP)
2355 if (ret != 1 && ret != 3) {
2356 tcg_gen_movi_i64(cpu_pc, ctx.pc);
2358 #if defined (DO_TB_FLUSH)
2359 tcg_gen_helper_0_0(helper_tb_flush);
2361 if (tb->cflags & CF_LAST_IO)
2363 /* Generate the return instruction */
2365 gen_icount_end(tb, num_insns);
2366 *gen_opc_ptr = INDEX_op_end;
2368 j = gen_opc_ptr - gen_opc_buf;
2371 gen_opc_instr_start[lj++] = 0;
2373 tb->size = ctx.pc - pc_start;
2374 tb->icount = num_insns;
2376 #if defined ALPHA_DEBUG_DISAS
2377 if (loglevel & CPU_LOG_TB_CPU) {
2378 cpu_dump_state(env, logfile, fprintf, 0);
2380 if (loglevel & CPU_LOG_TB_IN_ASM) {
2381 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2382 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2383 fprintf(logfile, "\n");
2388 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2390 gen_intermediate_code_internal(env, tb, 0);
2393 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2395 gen_intermediate_code_internal(env, tb, 1);
2398 CPUAlphaState * cpu_alpha_init (const char *cpu_model)
2403 env = qemu_mallocz(sizeof(CPUAlphaState));
2407 alpha_translate_init();
2409 /* XXX: should not be hardcoded */
2410 env->implver = IMPLVER_2106x;
2412 #if defined (CONFIG_USER_ONLY)
2416 /* Initialize IPR */
2417 hwpcb = env->ipr[IPR_PCBB];
2418 env->ipr[IPR_ASN] = 0;
2419 env->ipr[IPR_ASTEN] = 0;
2420 env->ipr[IPR_ASTSR] = 0;
2421 env->ipr[IPR_DATFX] = 0;
2423 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2424 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2425 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2426 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2427 env->ipr[IPR_FEN] = 0;
2428 env->ipr[IPR_IPL] = 31;
2429 env->ipr[IPR_MCES] = 0;
2430 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2431 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2432 env->ipr[IPR_SISR] = 0;
2433 env->ipr[IPR_VIRBND] = -1ULL;
2438 void gen_pc_load(CPUState *env, TranslationBlock *tb,
2439 unsigned long searched_pc, int pc_pos, void *puc)
2441 env->pc = gen_opc_pc[pc_pos];