1 /*****************************************************************
3 *****************************************************************/
11 // in : rscratch (0x00hhmmll)
12 // out : rscratch (0xhhll0000)
14 STR regCycles,[regCPUvar,#Cycles_ofs]
19 LDR regCycles,[regCPUvar,#Cycles_ofs]
21 STMFD R13!,{PC} //Push return address
27 // in : rscratch (0x00hhmmll)
28 // out : rscratch (0x0000hhll)
30 STR regCycles,[regCPUvar,#Cycles_ofs]
34 LDR regCycles,[regCPUvar,#Cycles_ofs]
36 STMFD R13!,{PC} //Push return address
41 .macro S9xGetWordRegStatus reg
42 // in : rscratch (0x00hhmmll)
43 // out : reg (0xhhll0000)
44 // flags have to be updated with read value
46 STR regCycles,[regCPUvar,#Cycles_ofs]
50 MOVS \reg, R0, LSL #16
51 LDR regCycles,[regCPUvar,#Cycles_ofs]
53 STMFD R13!,{PC} //Push return address
56 MOVS \reg, R0, LSL #16
59 .macro S9xGetWordRegNS reg
60 // in : rscratch (0x00hhmmll)
61 // out : reg (0xhhll0000)
62 // DOES NOT DESTROY rscratch (R0)
64 STR regCycles,[regCPUvar,#Cycles_ofs]
69 LDR regCycles,[regCPUvar,#Cycles_ofs]
72 STMFD R13!,{PC} //Push return address
79 .macro S9xGetWordLowRegNS reg
80 // in : rscratch (0x00hhmmll)
81 // out : reg (0xhhll0000)
82 // DOES NOT DESTROY rscratch (R0)
84 STR regCycles,[regCPUvar,#Cycles_ofs]
89 LDR regCycles,[regCPUvar,#Cycles_ofs]
92 STMFD R13!,{PC} //Push return address
101 // in : rscratch (0x00hhmmll)
102 // out : rscratch (0xll000000)
104 STR regCycles,[regCPUvar,#Cycles_ofs]
109 LDR regCycles,[regCPUvar,#Cycles_ofs]
111 STMFD R13!,{PC} //Push return address
118 // in : rscratch (0x00hhmmll)
119 // out : rscratch (0x000000ll)
121 STR regCycles,[regCPUvar,#Cycles_ofs]
125 LDR regCycles,[regCPUvar,#Cycles_ofs]
132 .macro S9xGetByteRegStatus reg
133 // in : rscratch (0x00hhmmll)
134 // out : reg (0xll000000)
135 // flags have to be updated with read value
137 STR regCycles,[regCPUvar,#Cycles_ofs]
141 MOVS \reg, R0, LSL #24
142 LDR regCycles,[regCPUvar,#Cycles_ofs]
144 STMFD R13!,{PC} //Push return address
147 MOVS \reg, R0, LSL #24
150 .macro S9xGetByteRegNS reg
151 // in : rscratch (0x00hhmmll)
152 // out : reg (0xll000000)
153 // DOES NOT DESTROY rscratch (R0)
155 STR regCycles,[regCPUvar,#Cycles_ofs]
158 MOV \reg, R0, LSL #24
160 LDR regCycles,[regCPUvar,#Cycles_ofs]
163 STMFD R13!,{PC} //Push return address
166 MOVS \reg, R0, LSL #24
170 .macro S9xGetByteLowRegNS reg
171 // in : rscratch (0x00hhmmll)
172 // out : reg (0x000000ll)
173 // DOES NOT DESTROY rscratch (R0)
175 STR regCycles,[regCPUvar,#Cycles_ofs]
178 MOV \reg, R0, LSL #24
180 LDR regCycles,[regCPUvar,#Cycles_ofs]
183 STMFD R13!,{PC} //Push return address
191 .macro S9xSetWord regValue
192 // in : regValue (0xhhll0000)
193 // in : rscratch=address (0x00hhmmll)
195 STR regCycles,[regCPUvar,#Cycles_ofs]
196 MOV R1,\regValue, LSR #16
200 LDR regCycles,[regCPUvar,#Cycles_ofs]
202 STMFD R13!,{PC} //Push return address
203 MOV R1,\regValue, LSR #16
208 .macro S9xSetWordZero
209 // in : rscratch=address (0x00hhmmll)
211 STR regCycles,[regCPUvar,#Cycles_ofs]
216 LDR regCycles,[regCPUvar,#Cycles_ofs]
218 STMFD R13!,{PC} //Push return address
224 .macro S9xSetWordLow regValue
225 // in : regValue (0x0000hhll)
226 // in : rscratch=address (0x00hhmmll)
228 STR regCycles,[regCPUvar,#Cycles_ofs]
233 LDR regCycles,[regCPUvar,#Cycles_ofs]
235 STMFD R13!,{PC} //Push return address
241 .macro S9xSetByte regValue
242 // in : regValue (0xll000000)
243 // in : rscratch=address (0x00hhmmll)
245 STR regCycles,[regCPUvar,#Cycles_ofs]
246 MOV R1,\regValue, LSR #24
250 LDR regCycles,[regCPUvar,#Cycles_ofs]
252 STMFD R13!,{PC} //Push return address
253 MOV R1,\regValue, LSR #24
258 .macro S9xSetByteZero
259 // in : rscratch=address (0x00hhmmll)
261 STR regCycles,[regCPUvar,#Cycles_ofs]
266 LDR regCycles,[regCPUvar,#Cycles_ofs]
268 STMFD R13!,{PC} //Push return address
274 .macro S9xSetByteLow regValue
275 // in : regValue (0x000000ll)
276 // in : rscratch=address (0x00hhmmll)
278 STR regCycles,[regCPUvar,#Cycles_ofs]
283 LDR regCycles,[regCPUvar,#Cycles_ofs]
285 STMFD R13!,{PC} //Push return address
293 // ===========================================
294 // ===========================================
296 // ===========================================
297 // ===========================================
302 LDRB rscratch2 , [rpc, #1]
303 LDRB rscratch , [rpc],#2
304 ORR rscratch , rscratch, rscratch2, LSL #8
305 ORR rscratch , rscratch, regDBank, LSL #16
307 .macro AbsoluteIndexedIndirectX0
309 LDRB rscratch2 , [rpc, #1]
310 LDRB rscratch , [rpc], #2
311 ORR rscratch , rscratch, rscratch2, LSL #8
312 ADD rscratch , regX, rscratch, LSL #16
313 MOV rscratch , rscratch, LSR #16
314 ORR rscratch , rscratch, regPBank, LSL #16
318 .macro AbsoluteIndexedIndirectX1
320 LDRB rscratch2 , [rpc, #1]
321 LDRB rscratch , [rpc], #2
322 ORR rscratch , rscratch, rscratch2, LSL #8
323 ADD rscratch , rscratch, regX, LSR #24
324 BIC rscratch , rscratch, #0x00FF0000
325 ORR rscratch , rscratch, regPBank, LSL #16
329 .macro AbsoluteIndirectLong
331 LDRB rscratch2 , [rpc, #1]
332 LDRB rscratch , [rpc], #2
333 ORR rscratch , rscratch, rscratch2, LSL #8
334 S9xGetWordLowRegNS rscratch2
335 ADD rscratch , rscratch, #2
336 STMFD r13!,{rscratch2}
338 LDMFD r13!,{rscratch2}
339 ORR rscratch , rscratch2, rscratch, LSL #16
341 .macro AbsoluteIndirect
343 LDRB rscratch2 , [rpc,#1]
344 LDRB rscratch , [rpc], #2
345 ORR rscratch , rscratch, rscratch2, LSL #8
347 ORR rscratch , rscratch, regPBank, LSL #16
349 .macro AbsoluteIndexedX0
351 LDRB rscratch2 , [rpc, #1]
352 LDRB rscratch , [rpc], #2
353 ORR rscratch , rscratch, rscratch2, LSL #8
354 ORR rscratch , rscratch, regDBank, LSL #16
355 ADD rscratch , rscratch, regX, LSR #16
357 .macro AbsoluteIndexedX1
359 LDRB rscratch2 , [rpc, #1]
360 LDRB rscratch , [rpc], #2
361 ORR rscratch , rscratch, rscratch2, LSL #8
362 ORR rscratch , rscratch, regDBank, LSL #16
363 ADD rscratch , rscratch, regX, LSR #24
367 .macro AbsoluteIndexedY0
369 LDRB rscratch2 , [rpc, #1]
370 LDRB rscratch , [rpc], #2
371 ORR rscratch , rscratch, rscratch2, LSL #8
372 ORR rscratch , rscratch, regDBank, LSL #16
373 ADD rscratch , rscratch, regY, LSR #16
375 .macro AbsoluteIndexedY1
377 LDRB rscratch2 , [rpc, #1]
378 LDRB rscratch , [rpc], #2
379 ORR rscratch , rscratch, rscratch2, LSL #8
380 ORR rscratch , rscratch, regDBank, LSL #16
381 ADD rscratch , rscratch, regY, LSR #24
385 LDRB rscratch2 , [rpc, #1]
386 LDRB rscratch , [rpc], #2
387 ORR rscratch , rscratch, rscratch2, LSL #8
388 LDRB rscratch2 , [rpc], #1
389 ORR rscratch , rscratch, rscratch2, LSL #16
393 .macro AbsoluteLongIndexedX0
395 LDRB rscratch2 , [rpc, #1]
396 LDRB rscratch , [rpc], #2
397 ORR rscratch , rscratch, rscratch2, LSL #8
398 LDRB rscratch2 , [rpc], #1
399 ORR rscratch , rscratch, rscratch2, LSL #16
400 ADD rscratch , rscratch, regX, LSR #16
401 BIC rscratch, rscratch, #0xFF000000
403 .macro AbsoluteLongIndexedX1
405 LDRB rscratch2 , [rpc, #1]
406 LDRB rscratch , [rpc], #2
407 ORR rscratch , rscratch, rscratch2, LSL #8
408 LDRB rscratch2 , [rpc], #1
409 ORR rscratch , rscratch, rscratch2, LSL #16
410 ADD rscratch , rscratch, regX, LSR #24
411 BIC rscratch, rscratch, #0xFF000000
415 LDRB rscratch , [rpc], #1
416 ADD rscratch , regD, rscratch, LSL #16
417 MOV rscratch, rscratch, LSR #16
419 .macro DirectIndirect
421 LDRB rscratch , [rpc], #1
422 ADD rscratch , regD, rscratch, LSL #16
423 MOV rscratch, rscratch, LSR #16
425 ORR rscratch , rscratch, regDBank, LSL #16
427 .macro DirectIndirectLong
429 LDRB rscratch , [rpc], #1
430 ADD rscratch , regD, rscratch, LSL #16
431 MOV rscratch, rscratch, LSR #16
432 S9xGetWordLowRegNS rscratch2
433 ADD rscratch , rscratch,#2
434 STMFD r13!,{rscratch2}
436 LDMFD r13!,{rscratch2}
437 ORR rscratch , rscratch2, rscratch, LSL #16
439 .macro DirectIndirectIndexed0
441 LDRB rscratch , [rpc], #1
442 ADD rscratch , regD, rscratch, LSL #16
443 MOV rscratch, rscratch, LSR #16
445 ORR rscratch, rscratch,regDBank, LSL #16
446 ADD rscratch, rscratch,regY, LSR #16
448 .macro DirectIndirectIndexed1
450 LDRB rscratch , [rpc], #1
451 ADD rscratch , regD, rscratch, LSL #16
452 MOV rscratch, rscratch, LSR #16
454 ORR rscratch, rscratch,regDBank, LSL #16
455 ADD rscratch, rscratch,regY, LSR #24
457 .macro DirectIndirectIndexedLong0
459 LDRB rscratch , [rpc], #1
460 ADD rscratch , regD, rscratch, LSL #16
461 MOV rscratch, rscratch, LSR #16
462 S9xGetWordLowRegNS rscratch2
463 ADD rscratch , rscratch,#2
464 STMFD r13!,{rscratch2}
466 LDMFD r13!,{rscratch2}
467 ORR rscratch , rscratch2, rscratch, LSL #16
468 ADD rscratch, rscratch,regY, LSR #16
470 .macro DirectIndirectIndexedLong1
472 LDRB rscratch , [rpc], #1
473 ADD rscratch , regD, rscratch, LSL #16
474 MOV rscratch, rscratch, LSR #16
475 S9xGetWordLowRegNS rscratch2
476 ADD rscratch , rscratch,#2
477 STMFD r13!,{rscratch2}
479 LDMFD r13!,{rscratch2}
480 ORR rscratch , rscratch2, rscratch, LSL #16
481 ADD rscratch, rscratch,regY, LSR #24
483 .macro DirectIndexedIndirect0
485 LDRB rscratch , [rpc], #1
486 ADD rscratch2 , regD , regX
487 ADD rscratch , rscratch2 , rscratch, LSL #16
488 MOV rscratch, rscratch, LSR #16
490 ORR rscratch , rscratch , regDBank, LSL #16
492 .macro DirectIndexedIndirect1
494 LDRB rscratch , [rpc], #1
495 ADD rscratch2 , regD , regX, LSR #8
496 ADD rscratch , rscratch2 , rscratch, LSL #16
497 MOV rscratch, rscratch, LSR #16
499 ORR rscratch , rscratch , regDBank, LSL #16
501 .macro DirectIndexedX0
503 LDRB rscratch , [rpc], #1
504 ADD rscratch2 , regD , regX
505 ADD rscratch , rscratch2 , rscratch, LSL #16
506 MOV rscratch, rscratch, LSR #16
508 .macro DirectIndexedX1
510 LDRB rscratch , [rpc], #1
511 ADD rscratch2 , regD , regX, LSR #8
512 ADD rscratch , rscratch2 , rscratch, LSL #16
513 MOV rscratch, rscratch, LSR #16
515 .macro DirectIndexedY0
517 LDRB rscratch , [rpc], #1
518 ADD rscratch2 , regD , regY
519 ADD rscratch , rscratch2 , rscratch, LSL #16
520 MOV rscratch, rscratch, LSR #16
522 .macro DirectIndexedY1
524 LDRB rscratch , [rpc], #1
525 ADD rscratch2 , regD , regY, LSR #8
526 ADD rscratch , rscratch2 , rscratch, LSL #16
527 MOV rscratch, rscratch, LSR #16
530 ADD rscratch, rpc, regPBank, LSL #16
531 SUB rscratch, rscratch, regpcbase
535 ADD rscratch, rpc, regPBank, LSL #16
536 SUB rscratch, rscratch, regpcbase
541 LDRSB rscratch , [rpc],#1
542 ADD rscratch , rscratch , rpc
543 SUB rscratch , rscratch, regpcbase
544 BIC rscratch,rscratch,#0x00FF0000
545 BIC rscratch,rscratch,#0xFF000000
547 .macro asmRelativeLong
549 LDRB rscratch2 , [rpc, #1]
550 LDRB rscratch , [rpc], #2
551 ORR rscratch , rscratch, rscratch2, LSL #8
552 SUB rscratch2 , rpc, regpcbase
553 ADD rscratch , rscratch2, rscratch
554 BIC rscratch,rscratch,#0x00FF0000
558 .macro StackasmRelative
560 LDRB rscratch , [rpc], #1
561 ADD rscratch , rscratch, regS
562 BIC rscratch,rscratch,#0x00FF0000
564 .macro StackasmRelativeIndirectIndexed0
566 LDRB rscratch , [rpc], #1
567 ADD rscratch , rscratch, regS
568 BIC rscratch,rscratch,#0x00FF0000
570 ORR rscratch , rscratch, regDBank, LSL #16
571 ADD rscratch , rscratch, regY, LSR #16
572 BIC rscratch, rscratch, #0xFF000000
574 .macro StackasmRelativeIndirectIndexed1
576 LDRB rscratch , [rpc], #1
577 ADD rscratch , rscratch, regS
578 BIC rscratch,rscratch,#0x00FF0000
580 ORR rscratch , rscratch, regDBank, LSL #16
581 ADD rscratch , rscratch, regY, LSR #24
582 BIC rscratch, rscratch, #0xFF000000
586 /****************************************/
603 MOV rscratch2,rscratch
605 S9xSetWordLow rscratch2
620 MOV \reg,rscratch,LSL #24
642 MOV \reg,rscratch,LSL #16
658 MOVS \reg,rscratch,LSL #24
664 MOVS rscratch,rscratch,LSL #24
676 MOVS rscratch,rscratch
682 MOVS \reg,rscratch, LSL #16
688 MOVS rscratch,rscratch, LSL #16
700 MOVS rscratch,rscratch
709 //uint8 aaS9xGetByte(uint32 address);
711 // in : R0 = 0x00hhmmll
712 // out : R0 = 0x000000ll
713 // DESTROYED : R1,R2,R3
714 // UPDATE : regCycles
716 MOV R1,R0,LSR #MEMMAP_SHIFT
717 //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
718 //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
719 //so AND MEMMAP_MASK is BIC 0xFF000
721 //R2 <= Map[block] (GetAddress)
722 LDR R2,[regCPUvar,#Map_ofs]
723 LDR R2,[R2,R1,LSL #2]
725 BLO GBSpecial //special
726 // Direct ROM/RAM acess
727 //R2 <= GetAddress + Address & 0xFFFF
728 //R3 <= MemorySpeed[block]
729 LDR R3,[regCPUvar,#MemorySpeed_ofs]
734 ADD regCycles,regCycles,R3
735 //R3 = BlockIsRAM[block]
736 LDR R3,[regCPUvar,#BlockIsRAM_ofs]
737 //Get value to return
741 // if BlockIsRAM => update for CPUShutdown
742 LDRNE R1,[regCPUvar,#PCAtOpcodeStart_ofs]
743 STRNE R1,[regCPUvar,#WaitAddress_ofs]
745 LDMFD R13!,{PC} //Return
749 LDR R3,[regCPUvar,#PALMOS_R10_ofs]
750 LDR R2,[PC,R2,LSL #2]
753 LDR PC,[PC,R2,LSL #2]
754 MOV R0,R0 //nop, for align
773 LDRB R1,[regCPUvar,#InDMA_ofs]
775 ADDEQ regCycles,regCycles,#ONE_CYCLE //No -> update Cycles
776 MOV R0,R0,LSL #16 //S9xGetPPU(Address&0xFFFF);
777 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
782 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
783 LDMFD R13!,{PC} //Return
785 ADD regCycles,regCycles,#ONE_CYCLE //update Cycles
786 MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
787 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
792 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
793 LDMFD R13!,{PC} //Return
795 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
796 MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
797 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
802 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
803 LDMFD R13!,{PC} //Return
805 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
806 LDRH R2,[regCPUvar,#SRAMMask]
807 LDR R1,[regCPUvar,#SRAM]
808 AND R0,R2,R0 //Address&SRAMMask
809 LDRB R0,[R1,R0] //*Memory.SRAM + Address&SRAMMask
813 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
817 MOV R1,R1,LSR #17 //Address&0x7FFF
818 MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3)
820 LDRH R2,[regCPUvar,#SRAMMask]
821 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
822 LDR R1,[regCPUvar,#SRAM]
823 AND R0,R2,R0 //Address&SRAMMask
824 LDRB R0,[R1,R0] //*Memory.SRAM + Address&SRAMMask
825 LDMFD R13!,{PC} //return
830 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
834 /*ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
838 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
839 MOV R0,R0,LSL #16 //S9xGetC4(Address&0xFFFF);
840 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
845 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
846 LDMFD R13!,{PC} //Return
850 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
851 MOV R0,R0,LSR #17 //Address&0x7FFF
852 LDR R1,[regCPUvar,#BWRAM]
853 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
854 LDRB R0,[R0,R1] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
858 //uint16 aaS9xGetWord(uint32 address);
860 // in : R0 = 0x00hhmmll
861 // out : R0 = 0x000000ll
862 // DESTROYED : R1,R2,R3
863 // UPDATE : regCycles
888 MOV R1,R0,LSR #MEMMAP_SHIFT
889 //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
890 //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
891 //so AND MEMMAP_MASK is BIC 0xFF000
893 //R2 <= Map[block] (GetAddress)
894 LDR R2,[regCPUvar,#Map_ofs]
895 LDR R2,[R2,R1,LSL #2]
897 BLO GWSpecial //special
898 // Direct ROM/RAM acess
902 //R2 <= GetAddress + Address & 0xFFFF
903 //R3 <= MemorySpeed[block]
904 LDR R3,[regCPUvar,#MemorySpeed_ofs]
909 ADD regCycles,regCycles,R3, LSL #1
910 //R3 = BlockIsRAM[block]
911 LDR R3,[regCPUvar,#BlockIsRAM_ofs]
912 //Get value to return
916 // if BlockIsRAM => update for CPUShutdown
917 LDRNE R1,[regCPUvar,#PCAtOpcodeStart_ofs]
918 STRNE R1,[regCPUvar,#WaitAddress_ofs]
920 LDMFD R13!,{PC} //Return
925 LDRB R3,[R2,R3,LSR #16] //GetAddress+ (Address+1)&0xFFFF
926 LDRB R0,[R2,R0,LSR #16] //GetAddress+ Address&0xFFFF
929 // if BlockIsRAM => update for CPUShutdown
930 LDR R3,[regCPUvar,#BlockIsRAM_ofs]
931 LDR R2,[regCPUvar,#MemorySpeed_ofs]
932 LDRB R3,[R3,R1] //R3 = BlockIsRAM[block]
933 LDRB R2,[R2,R1] //R2 <= MemorySpeed[block]
934 MOVS R3,R3 //IsRAM ? CPUShutdown stuff
935 LDRNE R1,[regCPUvar,#PCAtOpcodeStart_ofs]
936 STRNE R1,[regCPUvar,#WaitAddress_ofs]
937 ADD regCycles,regCycles,R2, LSL #1 //Update CPU.Cycles
938 LDMFD R13!,{PC} //Return
941 LDR R3,[regCPUvar,#PALMOS_R10_ofs]
942 LDR R2,[PC,R2,LSL #2]
945 LDR PC,[PC,R2,LSL #2]
946 MOV R0,R0 //nop, for align
963 /* MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
964 MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
965 MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
969 LDRB R1,[regCPUvar,#InDMA_ofs]
971 ADDEQ regCycles,regCycles,#(ONE_CYCLE*2) //No -> update Cycles
972 MOV R0,R0,LSL #16 //S9xGetPPU(Address&0xFFFF);
973 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
984 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
985 LDMFD R13!,{PC} //Return
987 ADD regCycles,regCycles,#(ONE_CYCLE*2) //update Cycles
988 MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
989 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1000 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1001 LDMFD R13!,{PC} //Return
1003 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1004 MOV R0,R0,LSL #16 //S9xGetCPU(Address&0xFFFF);
1005 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1012 //BIC R0,R0,#0x10000
1016 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1017 LDMFD R13!,{PC} //Return
1019 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1023 LDRH R2,[regCPUvar,#SRAMMask]
1024 LDR R1,[regCPUvar,#SRAM]
1025 AND R3,R2,R0 //Address&SRAMMask
1026 LDRH R0,[R3,R1] //*Memory.SRAM + Address&SRAMMask
1027 LDMFD R13!,{PC} //return
1029 LDRH R2,[regCPUvar,#SRAMMask]
1030 LDR R1,[regCPUvar,#SRAM]
1031 AND R3,R2,R0 //Address&SRAMMask
1033 AND R2,R0,R2 //Address&SRAMMask
1034 LDRB R3,[R1,R3] //*Memory.SRAM + Address&SRAMMask
1035 LDRB R2,[R1,R2] //*Memory.SRAM + Address&SRAMMask
1037 LDMFD R13!,{PC} //return
1040 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1047 MOV R1,R1,LSR #17 //Address&0x7FFF
1048 MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1050 LDRH R2,[regCPUvar,#SRAMMask]
1051 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1052 LDR R1,[regCPUvar,#SRAM]
1053 AND R0,R2,R0 //Address&SRAMMask
1054 LDRH R0,[R1,R0] //*Memory.SRAM + Address&SRAMMask
1055 LDMFD R13!,{PC} //return
1060 MOV R3,R3,LSR #17 //Address&0x7FFF
1061 MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1064 SUB R2,R2,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1067 MOV R3,R3,LSR #17 //(Address+1)&0x7FFF
1068 MOV R0,R0,LSR #3 //((Address+1)&0xF0000 >> 3)
1070 LDRH R3,[regCPUvar,#SRAMMask] //reload mask
1071 SUB R0,R0,#0x6000 //(((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1072 AND R2,R3,R2 //Address...&SRAMMask
1073 AND R0,R3,R0 //(Address+1...)&SRAMMask
1075 LDR R3,[regCPUvar,#SRAM]
1076 LDRB R0,[R0,R3] //*Memory.SRAM + (Address...)&SRAMMask
1077 LDRB R2,[R2,R3] //*Memory.SRAM + (Address+1...)&SRAMMask
1080 LDMFD R13!,{PC} //return
1085 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1090 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1094 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1095 MOV R0,R0,LSL #16 //S9xGetC4(Address&0xFFFF);
1096 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1103 //BIC R0,R0,#0x10000
1107 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1108 LDMFD R13!,{PC} //Return
1113 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1114 MOV R0,R0,LSR #17 //Address&0x7FFF
1115 LDR R1,[regCPUvar,#BWRAM]
1116 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1117 LDRH R0,[R1,R0] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1118 LDMFD R13!,{PC} //return
1121 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1123 MOV R0,R0,LSR #17 //Address&0x7FFF
1124 MOV R3,R3,LSR #17 //(Address+1)&0x7FFF
1125 LDR R1,[regCPUvar,#BWRAM]
1126 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1127 SUB R3,R3,#0x6000 //(((Address+1) & 0x7fff) - 0x6000)
1128 LDRB R0,[R1,R0] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1129 LDRB R3,[R1,R3] //*Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1131 LDMFD R13!,{PC} //return
1136 //void aaS9xSetByte(uint32 address,uint8 val);
1138 // in : R0=0x00hhmmll R1=0x000000ll
1139 // DESTROYED : R0,R1,R2,R3
1140 // UPDATE : regCycles
1143 STR R2,[regCPUvar,#WaitAddress_ofs]
1147 MOV R3,R0,LSR #MEMMAP_SHIFT
1148 //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1149 //R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1150 //so AND MEMMAP_MASK is BIC 0xFF000
1152 //R2 <= Map[block] (SetAddress)
1153 LDR R2,[regCPUvar,#WriteMap_ofs]
1154 LDR R2,[R2,R3,LSL #2]
1156 BLO SBSpecial //special
1157 // Direct ROM/RAM acess
1159 //R2 <= SetAddress + Address & 0xFFFF
1161 ADD R2,R2,R0,LSR #16
1162 LDR R0,[regCPUvar,#MemorySpeed_ofs]
1165 //R0 <= MemorySpeed[block]
1168 ADD regCycles,regCycles,R0
1170 //only SA1 here : TODO
1175 LDR R3,[regCPUvar,#PALMOS_R10_ofs]
1176 LDR R2,[PC,R2,LSL #2]
1179 LDR PC,[PC,R2,LSL #2]
1180 MOV R0,R0 //nop, for align
1199 LDRB R2,[regCPUvar,#InDMA_ofs]
1201 ADDEQ regCycles,regCycles,#ONE_CYCLE //No -> update Cycles
1203 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1211 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1212 LDMFD R13!,{PC} //Return
1214 ADD regCycles,regCycles,#ONE_CYCLE //update Cycles
1216 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1217 MOV R0,R0,LSR #16 //Address&0xFFFF
1224 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1225 LDMFD R13!,{PC} //Return
1227 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1229 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1230 MOV R0,R0,LSR #16 //Address&0xFFFF
1237 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1238 LDMFD R13!,{PC} //Return
1240 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1241 LDRH R2,[regCPUvar,#SRAMMask]
1243 LDMEQFD R13!,{PC} //return if SRAMMask=0
1244 LDR R3,[regCPUvar,#SRAM]
1245 AND R0,R2,R0 //Address&SRAMMask
1246 STRB R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask
1249 STRB R0,[regCPUvar,#SRAMModified_ofs]
1250 LDMFD R13!,{PC} //return
1253 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1257 MOV R3,R3,LSR #17 //Address&0x7FFF
1258 MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1261 LDRH R2,[regCPUvar,#SRAMMask]
1263 LDMEQFD R13!,{PC} //return if SRAMMask=0
1265 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1266 LDR R3,[regCPUvar,#SRAM]
1267 AND R0,R2,R0 //Address&SRAMMask
1268 STRB R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask
1271 STRB R0,[regCPUvar,#SRAMModified_ofs]
1272 LDMFD R13!,{PC} //return
1277 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1280 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1282 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1283 MOV R0,R0,LSR #16 //Address&0xFFFF
1290 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1291 LDMFD R13!,{PC} //Return
1294 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1295 MOV R0,R0,LSR #17 //Address&0x7FFF
1296 LDR R2,[regCPUvar,#BWRAM]
1297 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1298 STRB R1,[R0,R2] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1301 STRB R0,[regCPUvar,#SRAMModified_ofs]
1307 //void aaS9xSetWord(uint32 address,uint16 val);
1309 // in : R0 = 0x00hhmmll R1=0x0000hhll
1310 // DESTROYED : R0,R1,R2,R3
1311 // UPDATE : regCycles
1335 STR R2,[regCPUvar,#WaitAddress_ofs]
1338 MOV R3,R0,LSR #MEMMAP_SHIFT
1339 //MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1340 //R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1341 //so AND MEMMAP_MASK is BIC 0xFF000
1343 //R2 <= Map[block] (SetAddress)
1344 LDR R2,[regCPUvar,#WriteMap_ofs]
1345 LDR R2,[R2,R3,LSL #2]
1347 BLO SWSpecial //special
1348 // Direct ROM/RAM acess
1351 //check if address is 16bits aligned or not
1356 ADD R2,R2,R0,LSR #16 //address & 0xFFFF + SetAddress
1357 LDR R0,[regCPUvar,#MemorySpeed_ofs]
1360 //R1 <= MemorySpeed[block]
1363 ADD regCycles,regCycles,R0, LSL #1
1365 //only SA1 here : TODO
1370 //R1 = (Address&0xFFFF)<<16
1372 //First write @address
1373 STRB R1,[R2,R0,LSR #16]
1376 //Second write @address+1
1377 STRB R1,[R2,R0,LSR #16]
1378 //R1 <= MemorySpeed[block]
1379 LDR R0,[regCPUvar,#MemorySpeed_ofs]
1382 ADD regCycles,regCycles,R0,LSL #1
1384 //only SA1 here : TODO
1389 LDR R3,[regCPUvar,#PALMOS_R10_ofs]
1390 LDR R2,[PC,R2,LSL #2]
1393 LDR PC,[PC,R2,LSL #2]
1394 MOV R0,R0 //nop, for align
1413 LDRB R2,[regCPUvar,#InDMA_ofs]
1415 ADDEQ regCycles,regCycles,#(ONE_CYCLE*2) //No -> update Cycles
1417 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1430 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1431 LDMFD R13!,{PC} //Return
1433 ADD regCycles,regCycles,#(ONE_CYCLE*2) //update Cycles
1435 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1436 MOV R0,R0,LSR #16 //Address&0xFFFF
1448 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1449 LDMFD R13!,{PC} //Return
1451 ADD regCycles,regCycles,#SLOW_ONE_CYCLE //update Cycles
1453 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1454 MOV R0,R0,LSR #16 //Address&0xFFFF
1466 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1467 LDMFD R13!,{PC} //Return
1469 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1470 LDRH R2,[regCPUvar,#SRAMMask]
1472 LDMEQFD R13!,{PC} //return if SRAMMask=0
1474 AND R3,R2,R0 //Address&SRAMMask
1478 LDR R0,[regCPUvar,#SRAM]
1479 STRH R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask
1481 STRB R0,[regCPUvar,#SRAMModified_ofs]
1482 LDMFD R13!,{PC} //return
1486 AND R2,R2,R0 //(Address+1)&SRAMMask
1487 LDR R0,[regCPUvar,#SRAM]
1488 STRB R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask
1490 STRB R1,[R0,R2] //*Memory.SRAM + (Address+1)&SRAMMask
1492 STRB R0,[regCPUvar,#SRAMModified_ofs]
1493 LDMFD R13!,{PC} //return
1496 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1498 LDRH R2,[regCPUvar,#SRAMMask]
1500 LDMEQFD R13!,{PC} //return if SRAMMask=0
1507 MOV R3,R3,LSR #17 //Address&0x7FFF
1508 MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1510 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1511 LDRH R2,[regCPUvar,#SRAMMask]
1512 LDR R3,[regCPUvar,#SRAM]
1513 AND R0,R2,R0 //Address&SRAMMask
1514 STRH R1,[R0,R3] //*Memory.SRAM + Address&SRAMMask
1516 STRB R0,[regCPUvar,#SRAMModified_ofs]
1517 LDMFD R13!,{PC} //return
1521 MOV R3,R3,LSR #17 //Address&0x7FFF
1522 MOV R2,R2,LSR #3 //(Address&0xF0000 >> 3)
1524 SUB R2,R2,#0x6000 //((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1529 MOV R3,R3,LSR #17 //(Address+1)&0x7FFF
1530 MOV R0,R0,LSR #3 //((Address+1)&0xF0000 >> 3)
1532 LDRH R3,[regCPUvar,#SRAMMask] //reload mask
1533 SUB R0,R0,#0x6000 //(((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1534 AND R2,R3,R2 //Address...&SRAMMask
1535 AND R0,R3,R0 //(Address+1...)&SRAMMask
1537 LDR R3,[regCPUvar,#SRAM]
1538 STRB R1,[R2,R3] //*Memory.SRAM + (Address...)&SRAMMask
1540 STRB R1,[R0,R3] //*Memory.SRAM + (Address+1...)&SRAMMask
1543 STRB R0,[regCPUvar,#SRAMModified_ofs]
1544 LDMFD R13!,{PC} //return
1549 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1550 LDMFD R13!,{PC} //return
1552 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1554 STR regCycles,[regCPUvar,#Cycles_ofs] //Save Cycles
1555 MOV R0,R0,LSR #16 //Address&0xFFFF
1567 LDR regCycles,[regCPUvar,#Cycles_ofs] //Load Cycles
1568 LDMFD R13!,{PC} //Return
1570 ADD regCycles,regCycles,#(SLOW_ONE_CYCLE*2) //update Cycles
1575 LDR R2,[regCPUvar,#BWRAM]
1576 MOV R0,R0,LSR #17 //Address&0x7FFF
1577 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1579 STRH R1,[R0,R2] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1580 STRB R3,[regCPUvar,#SRAMModified_ofs]
1581 LDMFD R13!,{PC} //return
1585 MOV R0,R0,LSR #17 //Address&0x7FFF
1586 MOV R3,R3,LSR #17 //(Address+1)&0x7FFF
1587 LDR R2,[regCPUvar,#BWRAM]
1588 SUB R0,R0,#0x6000 //((Address & 0x7fff) - 0x6000)
1589 SUB R3,R3,#0x6000 //(((Address+1) & 0x7fff) - 0x6000)
1590 STRB R1,[R2,R0] //*Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1592 STRB R1,[R2,R3] //*Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1594 STRB R0,[regCPUvar,#SRAMModified_ofs]
1595 LDMFD R13!,{PC} //return