vcs.maemo.org Git - drnoksnes/blob - os9x_65c816.s

   1         .DATA
   2 /****************************************************************
   3 ****************************************************************/
   4         .align 4
   5
   6     @ notaz
   7         .equiv ASM_SPC700,              1               ;@ 1 = use notaz's ASM_SPC700 core
   8
   9 /****************************************************************
  10         DEFINES
  11 ****************************************************************/
  12
  13 .equ MAP_LAST,  12
  14
  15 rstatus         .req R4  @ format : 0xff800000
  16 reg_d_bank      .req R4  @ format : 0x000000ll
  17 reg_a           .req R5  @ format : 0xhhll0000 or 0xll000000
  18 reg_d           .req R6  @ format : 0xhhll0000
  19 reg_p_bank      .req R6  @ format : 0x000000ll
  20 reg_x           .req R7  @ format : 0xhhll0000 or 0xll000000
  21 reg_s           .req R8  @ format : 0x0000hhll
  22 reg_y           .req R9  @ format : 0xhhll0000 or 0xll000000
  23
  24 rpc             .req R10 @ 32bits address
  25 reg_cycles      .req R11 @ 32bits counter
  26 regpcbase       .req R12 @ 32bits address
  27
  28 rscratch        .req R0  @ format : 0xhhll0000 if data and calculation or return of S9XREADBYTE or WORD
  29 regopcode       .req R0  @ format : 0x000000ll
  30 rscratch2       .req R1  @ format : 0xhhll for calculation and value
  31 rscratch3       .req R2  @
  32 rscratch4       .req R3  @ ??????
  33
  34 @ used for SBC opcode
  35 rscratch9       .req R10 @ ??????
  36
  37 reg_cpu_var .req R14
  38
  39
  40
  41 @ not used
  42 @ R13   @ Pointer 32 bit on a struct.
  43
  44 @ R15 = pc (sic!)
  45
  46
  47 /*
  48 .equ Carry       1
  49 .equ Zero        2
  50 .equ IRQ         4
  51 .equ Decimal     8
  52 .equ IndexFlag  16
  53 .equ MemoryFlag 32
  54 .equ Overflow   64
  55 .equ Negative  128
  56 .equ Emulation 256*/
  57
  58 .equ STATUS_SHIFTER,            24
  59 .equ MASK_EMUL,         (1<<(STATUS_SHIFTER-1))
  60 .equ MASK_SHIFTER_CARRY,        (STATUS_SHIFTER+1)
  61 .equ    MASK_CARRY,             (1<<(STATUS_SHIFTER))  @ 0
  62 .equ    MASK_ZERO,              (2<<(STATUS_SHIFTER))  @ 1
  63 .equ MASK_IRQ,          (4<<(STATUS_SHIFTER))  @ 2
  64 .equ MASK_DECIMAL,              (8<<(STATUS_SHIFTER))  @ 3
  65 .equ    MASK_INDEX,             (16<<(STATUS_SHIFTER)) @ 4  @ 1
  66 .equ    MASK_MEM,               (32<<(STATUS_SHIFTER)) @ 5  @ 2
  67 .equ    MASK_OVERFLOW,          (64<<(STATUS_SHIFTER)) @ 6  @ 4
  68 .equ    MASK_NEG,               (128<<(STATUS_SHIFTER))@ 7  @ 8
  69
  70 .equ ONE_CYCLE, 6
  71 .equ SLOW_ONE_CYCLE, 8
  72
  73 .equ    NMI_FLAG,           (1 << 7)
  74 .equ IRQ_PENDING_FLAG,    (1 << 11)
  75 .equ SCAN_KEYS_FLAG,        (1 << 4)
  76
  77
  78 .equ MEMMAP_BLOCK_SIZE, (0x1000)
  79 .equ MEMMAP_SHIFT, 12
  80 .equ MEMMAP_MASK, (0xFFF)
  81
  82 /****************************************************************
  83         MACROS
  84 ****************************************************************/
  85
  86 @ #include "os9x_65c816_mac_gen.h"
  87 /*****************************************************************/
  88 /*     Offset in SCPUState structure                             */
  89 /*****************************************************************/
  90 .equ Flags_ofs,             0
  91 .equ BranchSkip_ofs,    4
  92 .equ NMIActive_ofs,             5
  93 .equ IRQActive_ofs,             6
  94 .equ WaitingForInterrupt_ofs,   7
  95
  96 .equ    RPB_ofs,                8
  97 .equ    RDB_ofs,                9
  98 .equ    RP_ofs,             10
  99 .equ    RA_ofs,             12
 100 .equ    RAH_ofs,            13
 101 .equ    RD_ofs,             14
 102 .equ    RX_ofs,             16
 103 .equ    RS_ofs,             18
 104 .equ    RY_ofs,             20
 105 @.equ   RPC_ofs,                22
 106
 107 .equ PC_ofs,                    24
 108 .equ Cycles_ofs,                28
 109 .equ PCBase_ofs,                32
 110
 111 .equ PCAtOpcodeStart_ofs,       36
 112 .equ WaitAddress_ofs,           40
 113 .equ WaitCounter_ofs,           44
 114 .equ NextEvent_ofs,                 48
 115 .equ V_Counter_ofs,                 52
 116 .equ MemSpeed_ofs,                  56
 117 .equ MemSpeedx2_ofs,            60
 118 .equ FastROMSpeed_ofs,      64
 119 .equ AutoSaveTimer_ofs,     68
 120 .equ NMITriggerPoint_ofs,       72
 121 .equ NMICycleCount_ofs,     76
 122 .equ IRQCycleCount_ofs,     80
 123
 124 .equ InDMA_ofs,                 84
 125 .equ WhichEvent,                    85
 126 .equ SRAMModified_ofs,      86
 127 .equ BRKTriggered_ofs,      87
 128 .equ    asm_OPTABLE_ofs,                88
 129 .equ TriedInterleavedMode2_ofs, 92
 130
 131 .equ Map_ofs,               96
 132 .equ WriteMap_ofs,      100
 133 .equ MemorySpeed_ofs,   104
 134 .equ BlockIsRAM_ofs,    108
 135 .equ SRAM,                      112
 136 .equ BWRAM,             116
 137 .equ SRAMMask,          120
 138
 139 .equ    APUExecuting_ofs,   122
 140 @ notaz
 141 .equ    APU_Cycles,         124
 142
 143 /*****************************************************************/
 144
 145 /* prepare */
 146 .macro          PREPARE_C_CALL
 147         STMFD   R13!,{R12,R14}
 148 .endm
 149 .macro          PREPARE_C_CALL_R0
 150         STMFD   R13!,{R0,R12,R14}
 151 .endm
 152 .macro          PREPARE_C_CALL_R0R1
 153         STMFD   R13!,{R0,R1,R12,R14}
 154 .endm
 155 .macro          PREPARE_C_CALL_LIGHT
 156         STMFD   R13!,{R14}
 157 .endm
 158 .macro          PREPARE_C_CALL_LIGHTR12
 159         STMFD   R13!,{R12,R14}
 160 .endm
 161 /* restore */
 162 .macro          RESTORE_C_CALL
 163         LDMFD   R13!,{R12,R14}
 164 .endm
 165 .macro          RESTORE_C_CALL_R0
 166         LDMFD   R13!,{R0,R12,R14}
 167 .endm
 168 .macro          RESTORE_C_CALL_R1
 169         LDMFD   R13!,{R1,R12,R14}
 170 .endm
 171 .macro          RESTORE_C_CALL_LIGHT
 172         LDMFD   R13!,{R14}
 173 .endm
 174 .macro          RESTORE_C_CALL_LIGHTR12
 175         LDMFD   R13!,{R12,R14}
 176 .endm
 177
 178
 179 @ --------------
 180 .macro          LOAD_REGS
 181     @ notaz
 182     add     r0,reg_cpu_var,#8
 183     ldmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 184     @ rstatus (P) & reg_d_bank
 185     mov     reg_d_bank,r1,lsl #16
 186     mov     reg_d_bank,reg_d_bank,lsr #24
 187     mov     r0,r1,lsr #16
 188         orrs    rstatus, rstatus, r0,lsl #STATUS_SHIFTER @ 24
 189         @ if Carry set, then EMULATION bit was set
 190         orrcs   rstatus,rstatus,#MASK_EMUL
 191     @ reg_d & reg_p_bank
 192     mov     reg_d,reg_a,lsr #16
 193     mov     reg_d,reg_d,lsl #8
 194     orr     reg_d,reg_d,r1,lsl #24
 195     mov     reg_d,reg_d,ror #24    @ 0xdddd00pb
 196     @ reg_x, reg_s
 197     mov     reg_s,reg_x,lsr #16
 198         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 199         tst             rstatus,#MASK_INDEX
 200         movne   reg_x,reg_x,lsl #24
 201         movne   reg_y,reg_y,lsl #24
 202         moveq   reg_x,reg_x,lsl #16
 203         moveq   reg_y,reg_y,lsl #16
 204         tst             rstatus,#MASK_MEM
 205         movne   reg_a,reg_a,lsl #24
 206         moveq   reg_a,reg_a,lsl #16
 207
 208 /*
 209     @ reg_d & reg_p_bank share the same register
 210         LDRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 211         LDRH            rscratch,[reg_cpu_var,#RD_ofs]
 212         ORR             reg_d,reg_d,rscratch, LSL #16
 213         @ rstatus & reg_d_bank share the same register
 214         LDRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 215         LDRH            rscratch,[reg_cpu_var,#RP_ofs]
 216         ORRS            rstatus, rstatus, rscratch,LSL #STATUS_SHIFTER @ 24
 217         @ if Carry set, then EMULATION bit was set
 218         ORRCS           rstatus,rstatus,#MASK_EMUL
 219         @
 220         LDRH            reg_a,[reg_cpu_var,#RA_ofs]
 221         LDRH            reg_x,[reg_cpu_var,#RX_ofs]
 222         LDRH            reg_y,[reg_cpu_var,#RY_ofs]
 223         LDRH            reg_s,[reg_cpu_var,#RS_ofs]
 224         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 225         TST             rstatus,#MASK_INDEX
 226         MOVNE           reg_x,reg_x,LSL #24
 227         MOVNE           reg_y,reg_y,LSL #24
 228         MOVEQ           reg_x,reg_x,LSL #16
 229         MOVEQ           reg_y,reg_y,LSL #16
 230         TST             rstatus,#MASK_MEM
 231         MOVNE           reg_a,reg_a,LSL #24
 232         MOVEQ           reg_a,reg_a,LSL #16
 233
 234         LDR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 235         LDR             rpc,[reg_cpu_var,#PC_ofs]
 236         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 237 */
 238 .endm
 239
 240
 241 .macro          SAVE_REGS
 242     @ notaz
 243     @ reg_p_bank, reg_d_bank and rstatus
 244     mov         r1, rstatus, lsr #16
 245     orr     r1, r1, reg_p_bank, lsl #24
 246         movs    r1, r1, lsr #8
 247         orrcs   r1, r1, #0x100 @ EMULATION bit
 248     orr     r1, r1, reg_d_bank, lsl #24
 249     mov     r1, r1, ror #16
 250     @ reg_a, reg_d
 251         tst             rstatus,#MASK_MEM
 252         ldrneh  r0, [reg_cpu_var,#RA_ofs]
 253         bicne   r0, r0,#0xFF
 254         orrne   reg_a, r0, reg_a,lsr #24
 255         moveq   reg_a, reg_a, lsr #16
 256     mov     reg_d, reg_d, lsr #16
 257         orr     reg_a, reg_a, reg_d, lsl #16
 258         @ Shift X&Y according to the current mode (INDEX, MEMORY bits)
 259         tst             rstatus,#MASK_INDEX
 260         movne   reg_x,reg_x,LSR #24
 261         movne   reg_y,reg_y,LSR #24
 262         moveq   reg_x,reg_x,LSR #16
 263         moveq   reg_y,reg_y,LSR #16
 264     @ reg_x, reg_s
 265         orr     reg_x, reg_x, reg_s, lsl #16
 266     @ store
 267     add     r0,reg_cpu_var,#8
 268     stmia   r0,{r1,reg_a,reg_x,reg_y,rpc,reg_cycles,regpcbase}
 269
 270 /*
 271     @ reg_d & reg_p_bank is same register
 272         STRB            reg_p_bank,[reg_cpu_var,#RPB_ofs]
 273         MOV             rscratch,reg_d, LSR #16
 274         STRH            rscratch,[reg_cpu_var,#RD_ofs]
 275         @ rstatus & reg_d_bank is same register
 276         STRB            reg_d_bank,[reg_cpu_var,#RDB_ofs]
 277         MOVS            rscratch, rstatus, LSR #STATUS_SHIFTER
 278         ORRCS           rscratch,rscratch,#0x100 @ EMULATION bit
 279         STRH            rscratch,[reg_cpu_var,#RP_ofs]
 280         @
 281         @ Shift X,Y & A according to the current mode (INDEX, MEMORY bits)
 282         TST             rstatus,#MASK_INDEX
 283         MOVNE           rscratch,reg_x,LSR #24
 284         MOVNE           rscratch2,reg_y,LSR #24
 285         MOVEQ           rscratch,reg_x,LSR #16
 286         MOVEQ           rscratch2,reg_y,LSR #16
 287         STRH            rscratch,[reg_cpu_var,#RX_ofs]
 288         STRH            rscratch2,[reg_cpu_var,#RY_ofs]
 289         TST             rstatus,#MASK_MEM
 290         LDRNEH          rscratch,[reg_cpu_var,#RA_ofs]
 291         BICNE           rscratch,rscratch,#0xFF
 292         ORRNE           rscratch,rscratch,reg_a,LSR #24
 293         MOVEQ           rscratch,reg_a,LSR #16
 294         STRH            rscratch,[reg_cpu_var,#RA_ofs]
 295
 296         STRH            reg_s,[reg_cpu_var,#RS_ofs]
 297         STR             regpcbase,[reg_cpu_var,#PCBase_ofs]
 298         STR             rpc,[reg_cpu_var,#PC_ofs]
 299
 300         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 301 */
 302 .endm
 303
 304 /*****************************************************************/
 305 .macro          ADD1CYCLE
 306                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 307 .endm
 308 .macro          ADD1CYCLENE
 309                 addne   reg_cycles,reg_cycles, #ONE_CYCLE
 310 .endm
 311 .macro          ADD1CYCLEEQ
 312                 addeq   reg_cycles,reg_cycles, #ONE_CYCLE
 313 .endm
 314
 315 .macro          ADD2CYCLE
 316                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 317 .endm
 318 .macro          ADD2CYCLENE
 319                 addne   reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 320 .endm
 321 .macro          ADD2CYCLE2MEM
 322                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 323                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 324                 add     reg_cycles, reg_cycles, rscratch, LSL #1
 325 .endm
 326 .macro          ADD2CYCLE1MEM
 327                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 328                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*2)
 329                 add     reg_cycles, reg_cycles, rscratch
 330 .endm
 331
 332 .macro          ADD3CYCLE
 333                 add     reg_cycles,reg_cycles, #(ONE_CYCLE*3)
 334 .endm
 335
 336 .macro          ADD1CYCLE1MEM
 337                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 338                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 339                 add     reg_cycles, reg_cycles, rscratch
 340 .endm
 341
 342 .macro          ADD1CYCLE2MEM
 343                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 344                 add     reg_cycles,reg_cycles, #ONE_CYCLE
 345                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 346 .endm
 347
 348 .macro          ADD1MEM
 349                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 350                 add     reg_cycles, reg_cycles, rscratch
 351 .endm
 352
 353 .macro          ADD2MEM
 354                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 355                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 356 .endm
 357
 358 .macro          ADD3MEM
 359                 ldr     rscratch,[reg_cpu_var,#MemSpeed_ofs]
 360                 add     reg_cycles, rscratch, reg_cycles
 361                 add     reg_cycles, reg_cycles, rscratch, lsl #1
 362 .endm
 363
 364 /**************/
 365 .macro          ClearDecimal
 366                 BIC     rstatus,rstatus,#MASK_DECIMAL
 367 .endm
 368 .macro          SetDecimal
 369                 ORR     rstatus,rstatus,#MASK_DECIMAL
 370 .endm
 371 .macro          SetIRQ
 372                 ORR     rstatus,rstatus,#MASK_IRQ
 373 .endm
 374 .macro          ClearIRQ
 375                 BIC     rstatus,rstatus,#MASK_IRQ
 376 .endm
 377
 378 .macro          CPUShutdown
 379 @ if (Settings.Shutdown && CPU.PC == CPU.WaitAddress)
 380                 LDR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 381                 CMP             rpc,rscratch
 382                 BNE             5431f
 383 @ if (CPU.WaitCounter == 0 && !(CPU.Flags & (IRQ_PENDING_FLAG | NMI_FLAG)))
 384                 LDR             rscratch,[reg_cpu_var,#Flags_ofs]
 385                 LDR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 386                 TST             rscratch,#(IRQ_PENDING_FLAG|NMI_FLAG)
 387                 BNE             5432f
 388                 MOVS            rscratch2,rscratch2
 389                 BNE             5432f
 390 @ CPU.WaitAddress = NULL;
 391                 MOV             rscratch,#0
 392                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
 393 @ if (Settings.SA1)
 394 @               S9xSA1ExecuteDuringSleep ();            : TODO
 395
 396 @           CPU.Cycles = CPU.NextEvent;
 397                 LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
 398                 LDRB            r0,[reg_cpu_var,#APUExecuting_ofs]
 399                 MOVS            r0,r0
 400                 BEQ             5431f
 401 @           if (IAPU.APUExecuting)
 402 /*          {
 403                 ICPU.CPUExecuting = FALSE;
 404                 do
 405                 {
 406                     APU_EXECUTE1();
 407                 } while (APU.Cycles < CPU.NextEvent);
 408                 ICPU.CPUExecuting = TRUE;
 409             }
 410         */
 411                 asmAPU_EXECUTE2
 412                 B               5431f
 413 @.pool
 414 5432:
 415 /*      else
 416         if (CPU.WaitCounter >= 2)
 417             CPU.WaitCounter = 1;
 418         else
 419             CPU.WaitCounter--;
 420 */
 421                 CMP             rscratch2,#1
 422                 MOVHI           rscratch2,#1
 423                 @ SUBLS         rscratch2,rscratch2,#1
 424                 MOVLS           rscratch2,#0
 425                 STR             rscratch2,[reg_cpu_var,#WaitCounter_ofs]
 426 5431:
 427
 428 .endm
 429 .macro          BranchCheck0
 430                 /*in rsctach : OpAddress
 431                 /*destroy rscratch2*/
 432                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 433                 MOVS    rscratch2,rscratch2
 434                 BEQ     1110f
 435                 MOV     rscratch2,#0
 436                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 437                 SUB     rscratch2,rpc,regpcbase
 438                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 439                 CMP     rscratch2,rscratch
 440                 BHI     1111f
 441 1110:
 442 .endm
 443 .macro          BranchCheck1
 444                 /*in rsctach : OpAddress
 445                 /*destroy rscratch2*/
 446                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 447                 MOVS    rscratch2,rscratch2
 448                 BEQ     1110f
 449                 MOV     rscratch2,#0
 450                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 451                 SUB     rscratch2,rpc,regpcbase
 452                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 453                 CMP     rscratch2,rscratch
 454                 BHI     1111f
 455 1110:
 456 .endm
 457 .macro          BranchCheck2
 458                 /*in rsctach : OpAddress
 459                 /*destroy rscratch2*/
 460                 LDRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 461                 MOVS    rscratch2,rscratch2
 462                 BEQ     1110f
 463                 MOV     rscratch2,#0
 464                 STRB    rscratch2,[reg_cpu_var,#BranchSkip_ofs]
 465                 SUB     rscratch2,rpc,regpcbase
 466                 @ if( CPU.PC - CPU.PCBase > OpAddress) return;
 467                 CMP     rscratch2,rscratch
 468                 BHI     1111f
 469 1110:
 470 .endm
 471
 472 .macro          S9xSetPCBase
 473                 @  in  : rscratch (0x00hhmmll)
 474                 PREPARE_C_CALL
 475                 BL      asm_S9xSetPCBase
 476                 RESTORE_C_CALL
 477                 LDR     rpc,[reg_cpu_var,#PC_ofs]
 478                 LDR     regpcbase,[reg_cpu_var,#PCBase_ofs]
 479 .endm
 480
 481 .macro          S9xFixCycles
 482                 TST             rstatus,#MASK_EMUL
 483                 LDRNE           rscratch, = jumptable1     @ Mode 0 : M=1,X=1
 484                 BNE             991111f
 485                 @ EMULATION=0
 486                 TST             rstatus,#MASK_MEM
 487                 BEQ             991112f
 488                 @ MEMORY=1
 489                 TST             rstatus,#MASK_INDEX
 490                 @ INDEX=1  @ Mode 0 : M=1,X=1
 491                 LDRNE           rscratch, = jumptable1
 492                 @ INDEX=0  @ Mode 1 : M=1,X=0
 493                 LDREQ           rscratch, = jumptable2
 494                 B               991111f
 495 991112:         @ MEMORY=0
 496                 TST             rstatus,#MASK_INDEX
 497                 @ INDEX=1   @ Mode 3 : M=0,X=1
 498                 LDRNE           rscratch, = jumptable4
 499                 @ INDEX=0   @ Mode 2 : M=0,X=0
 500                 LDREQ           rscratch, = jumptable3
 501 991111:
 502                 STR             rscratch,[reg_cpu_var,#asm_OPTABLE_ofs]
 503 .endm
 504 /*
 505 .macro          S9xOpcode_NMI
 506                 SAVE_REGS
 507                 PREPARE_C_CALL_LIGHT
 508                 BL      asm_S9xOpcode_NMI
 509                 RESTORE_C_CALL_LIGHT
 510                 LOAD_REGS
 511 .endm
 512 .macro          S9xOpcode_IRQ
 513                 SAVE_REGS
 514                 PREPARE_C_CALL_LIGHT
 515                 BL      asm_S9xOpcode_IRQ
 516                 RESTORE_C_CALL_LIGHT
 517                 LOAD_REGS
 518 .endm
 519 */
 520 .macro          S9xDoHBlankProcessing
 521                 SAVE_REGS
 522                 PREPARE_C_CALL_LIGHT
 523 @               BL      asm_S9xDoHBlankProcessing
 524                 BL      S9xDoHBlankProcessing
 525                 RESTORE_C_CALL_LIGHT
 526                 LOAD_REGS
 527 .endm
 528
 529 /********************************/
 530 .macro          EXEC_OP
 531                 LDR             R1,[reg_cpu_var,#asm_OPTABLE_ofs]
 532                 STR             rpc,[reg_cpu_var,#PCAtOpcodeStart_ofs]
 533                 ADD1MEM
 534                 LDRB            R0, [rpc], #1
 535
 536                 LDR             PC, [R1,R0, LSL #2]
 537 .endm
 538 .macro          NEXTOPCODE
 539                 LDR                     rscratch,[reg_cpu_var,#NextEvent_ofs]
 540                 CMP                     reg_cycles,rscratch
 541                 BLT                     mainLoop
 542                 S9xDoHBlankProcessing
 543                 B                       mainLoop
 544 .endm
 545
 546 .macro          asmAPU_EXECUTE
 547                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 548                 CMP             R0,#1   @ spc700 enabled, hack mode off
 549                 BNE                 43210f
 550                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 551         SUBS        R0,reg_cycles,R0
 552         BMI         43210f
 553 .if ASM_SPC700
 554                 PREPARE_C_CALL_LIGHTR12
 555                 BL              spc700_execute
 556                 RESTORE_C_CALL_LIGHTR12
 557         SUB     R0,reg_cycles,R0 @ sub cycles left
 558                 STR             R0,[reg_cpu_var,#APU_Cycles]
 559 .else
 560         @ SAVE_REGS
 561                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 562                 PREPARE_C_CALL_LIGHTR12
 563                 BL              asm_APU_EXECUTE
 564                 RESTORE_C_CALL_LIGHTR12
 565                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 566 .endif
 567         @ LOAD_REGS
 568                 @ S9xFixCycles
 569 43210:
 570 .endm
 571
 572 .macro          asmAPU_EXECUTE2
 573 .if ASM_SPC700
 574                 LDRB            R0,[reg_cpu_var,#APUExecuting_ofs]
 575                 CMP             R0,#1   @ spc700 enabled, hack mode off
 576                 BNE                 43211f
 577                 LDR                 R0,[reg_cpu_var,#APU_Cycles]
 578         SUBS        R0,reg_cycles,R0 @ reg_cycles == NextEvent
 579         BLE         43211f
 580                 PREPARE_C_CALL_LIGHTR12
 581                 BL              spc700_execute
 582                 RESTORE_C_CALL_LIGHTR12
 583         SUB     R0,reg_cycles,R0 @ sub cycles left
 584                 STR             R0,[reg_cpu_var,#APU_Cycles]
 585 43211:
 586 .else
 587                 @ SAVE_REGS
 588                 STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 589                 PREPARE_C_CALL_LIGHTR12
 590                 BL              asm_APU_EXECUTE2
 591                 RESTORE_C_CALL_LIGHTR12
 592                 LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs]
 593                 @ LOAD_REGS
 594 .endif
 595 .endm
 596
 597 @ #include "os9x_65c816_mac_mem.h"
 598 .macro          S9xGetWord
 599                 @  in  : rscratch (0x00hhmmll)
 600                 @  out : rscratch (0xhhll0000)
 601                 STMFD   R13!,{PC} @ Push return address
 602                 B       asmS9xGetWord
 603                 MOV     R0,R0
 604                 MOV     R0, R0, LSL #16
 605 .endm
 606 .macro          S9xGetWordLow
 607                 @  in  : rscratch (0x00hhmmll)
 608                 @  out : rscratch (0x0000hhll)
 609                 STMFD   R13!,{PC} @ Push return address
 610                 B       asmS9xGetWord
 611                 MOV     R0,R0
 612 .endm
 613 .macro          S9xGetWordRegStatus     reg
 614                 @  in  : rscratch (0x00hhmmll)
 615                 @  out : reg      (0xhhll0000)
 616                 @  flags have to be updated with read value
 617                 STMFD   R13!,{PC} @ Push return address
 618                 B       asmS9xGetWord
 619                 MOV     R0,R0
 620                 MOVS    \reg, R0, LSL #16
 621 .endm
 622 .macro          S9xGetWordRegNS reg
 623                 @  in  : rscratch (0x00hhmmll)
 624                 @  out : reg (0xhhll0000)
 625                 @  DOES NOT DESTROY rscratch (R0)
 626                 STMFD   R13!,{R0}
 627                 STMFD   R13!,{PC} @ Push return address
 628                 B       asmS9xGetWord
 629                 MOV     R0,R0
 630                 MOV     \reg, R0, LSL #16
 631                 LDMFD   R13!,{R0}
 632 .endm
 633 .macro          S9xGetWordLowRegNS      reg
 634                 @  in  : rscratch (0x00hhmmll)
 635                 @  out : reg (0xhhll0000)
 636                 @  DOES NOT DESTROY rscratch (R0)
 637                 STMFD   R13!,{R0}
 638                 STMFD   R13!,{PC} @ Push return address
 639                 B       asmS9xGetWord
 640                 MOV     R0,R0
 641                 MOV     \reg, R0
 642                 LDMFD   R13!,{R0}
 643 .endm
 644
 645 .macro          S9xGetByte
 646                 @  in  : rscratch (0x00hhmmll)
 647                 @  out : rscratch (0xll000000)
 648                 STMFD   R13!,{PC} @ Push return address
 649                 B       asmS9xGetByte
 650                 MOV     R0,R0
 651                 MOV     R0, R0, LSL #24
 652 .endm
 653 .macro          S9xGetByteLow
 654                 @  in  : rscratch (0x00hhmmll)
 655                 @  out : rscratch (0x000000ll)
 656                 STMFD   R13!,{PC}
 657                 B       asmS9xGetByte
 658                 MOV     R0,R0
 659 .endm
 660 .macro          S9xGetByteRegStatus     reg
 661                 @  in  : rscratch (0x00hhmmll)
 662                 @  out : reg      (0xll000000)
 663                 @  flags have to be updated with read value
 664                 STMFD   R13!,{PC} @ Push return address
 665                 B       asmS9xGetByte
 666                 MOV     R0,R0
 667                 MOVS    \reg, R0, LSL #24
 668 .endm
 669 .macro          S9xGetByteRegNS reg
 670                 @  in  : rscratch (0x00hhmmll)
 671                 @  out : reg      (0xll000000)
 672                 @  DOES NOT DESTROY rscratch (R0)
 673                 STMFD   R13!,{R0}
 674                 STMFD   R13!,{PC} @ Push return address
 675                 B       asmS9xGetByte
 676                 MOV     R0,R0
 677                 MOVS    \reg, R0, LSL #24
 678                 LDMFD   R13!,{R0}
 679 .endm
 680 .macro          S9xGetByteLowRegNS      reg
 681                 @  in  : rscratch (0x00hhmmll)
 682                 @  out : reg      (0x000000ll)
 683                 @  DOES NOT DESTROY rscratch (R0)
 684                 STMFD   R13!,{R0}
 685                 STMFD   R13!,{PC} @ Push return address
 686                 B       asmS9xGetByte
 687                 MOV     R0,R0
 688                 MOVS    \reg, R0
 689                 LDMFD   R13!,{R0}
 690 .endm
 691
 692 .macro          S9xSetWord      regValue
 693                 @  in  : regValue  (0xhhll0000)
 694                 @  in  : rscratch=address   (0x00hhmmll)
 695                 MOV     R1,\regValue, LSR #16
 696                 STMFD   R13!,{PC} @ Push return address
 697                 B       asmS9xSetWord
 698                 MOV     R0,R0
 699 .endm
 700 .macro          S9xSetWordZero
 701                 @  in  : rscratch=address   (0x00hhmmll)
 702                 MOV     R1,#0
 703                 STMFD   R13!,{PC} @ Push return address
 704                 B       asmS9xSetWord
 705                 MOV     R0,R0
 706 .endm
 707 .macro          S9xSetWordLow   regValue
 708                 @  in  : regValue  (0x0000hhll)
 709                 @  in  : rscratch=address   (0x00hhmmll)
 710                 MOV     R1,\regValue
 711                 STMFD   R13!,{PC} @ Push return address
 712                 B       asmS9xSetWord
 713                 MOV     R0,R0
 714 .endm
 715 .macro          S9xSetByte      regValue
 716                 @  in  : regValue  (0xll000000)
 717                 @  in  : rscratch=address   (0x00hhmmll)
 718                 MOV     R1,\regValue, LSR #24
 719                 STMFD   R13!,{PC} @ Push return address
 720                 B       asmS9xSetByte
 721                 MOV     R0,R0
 722 .endm
 723 .macro          S9xSetByteZero
 724                 @  in  : rscratch=address   (0x00hhmmll)
 725                 MOV     R1,#0
 726                 STMFD   R13!,{PC} @ Push return address
 727                 B       asmS9xSetByte
 728                 MOV     R0,R0
 729 .endm
 730 .macro          S9xSetByteLow   regValue
 731                 @  in  : regValue  (0x000000ll)
 732                 @  in  : rscratch=address   (0x00hhmmll)
 733                 MOV     R1,\regValue
 734                 STMFD   R13!,{PC} @ Push return address
 735                 B       asmS9xSetByte
 736                 MOV     R0,R0
 737 .endm
 738
 739
 740 @  ===========================================
 741 @  ===========================================
 742 @  Adressing mode
 743 @  ===========================================
 744 @  ===========================================
 745
 746
 747 .macro          Absolute
 748                 ADD2MEM
 749                 LDRB    rscratch2    , [rpc, #1]
 750                 LDRB    rscratch   , [rpc],#2
 751                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 752                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 753 .endm
 754 .macro          AbsoluteIndexedIndirectX0
 755                 ADD2MEM
 756                 LDRB    rscratch2    , [rpc, #1]
 757                 LDRB    rscratch   , [rpc], #2
 758                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 759                 ADD     rscratch    , reg_x, rscratch, LSL #16
 760                 MOV     rscratch , rscratch, LSR #16
 761                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 762                 S9xGetWordLow
 763
 764 .endm
 765 .macro          AbsoluteIndexedIndirectX1
 766                 ADD2MEM
 767                 LDRB    rscratch2    , [rpc, #1]
 768                 LDRB    rscratch   , [rpc], #2
 769                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 770                 ADD     rscratch    , rscratch, reg_x, LSR #24
 771                 BIC     rscratch , rscratch, #0x00FF0000
 772                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 773                 S9xGetWordLow
 774
 775 .endm
 776 .macro          AbsoluteIndirectLong
 777                 ADD2MEM
 778                 LDRB                    rscratch2    , [rpc, #1]
 779                 LDRB                    rscratch   , [rpc], #2
 780                 ORR                     rscratch    , rscratch, rscratch2, LSL #8
 781                 S9xGetWordLowRegNS      rscratch2
 782                 ADD                     rscratch   , rscratch,  #2
 783                 STMFD                   r13!,{rscratch2}
 784                 S9xGetByteLow
 785                 LDMFD                   r13!,{rscratch2}
 786                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 787 .endm
 788 .macro          AbsoluteIndirect
 789                 ADD2MEM
 790                 LDRB    rscratch2    , [rpc,#1]
 791                 LDRB    rscratch   , [rpc], #2
 792                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 793                 S9xGetWordLow
 794                 ORR     rscratch    , rscratch, reg_p_bank, LSL #16
 795 .endm
 796 .macro          AbsoluteIndexedX0
 797                 ADD2MEM
 798                 LDRB    rscratch2    , [rpc, #1]
 799                 LDRB    rscratch   , [rpc], #2
 800                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 801                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 802                 ADD     rscratch    , rscratch, reg_x, LSR #16
 803 .endm
 804 .macro          AbsoluteIndexedX1
 805                 ADD2MEM
 806                 LDRB    rscratch2    , [rpc, #1]
 807                 LDRB    rscratch   , [rpc], #2
 808                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 809                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 810                 ADD     rscratch    , rscratch, reg_x, LSR #24
 811 .endm
 812
 813
 814 .macro          AbsoluteIndexedY0
 815                 ADD2MEM
 816                 LDRB    rscratch2    , [rpc, #1]
 817                 LDRB    rscratch   , [rpc], #2
 818                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 819                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 820                 ADD     rscratch    , rscratch, reg_y, LSR #16
 821 .endm
 822 .macro          AbsoluteIndexedY1
 823                 ADD2MEM
 824                 LDRB    rscratch2    , [rpc, #1]
 825                 LDRB    rscratch   , [rpc], #2
 826                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 827                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 828                 ADD     rscratch    , rscratch, reg_y, LSR #24
 829 .endm
 830 .macro          AbsoluteLong
 831                 ADD3MEM
 832                 LDRB    rscratch2    , [rpc, #1]
 833                 LDRB    rscratch   , [rpc], #2
 834                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 835                 LDRB    rscratch2   , [rpc], #1
 836                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 837 .endm
 838
 839
 840 .macro          AbsoluteLongIndexedX0
 841                 ADD3MEM
 842                 LDRB    rscratch2    , [rpc, #1]
 843                 LDRB    rscratch   , [rpc], #2
 844                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 845                 LDRB    rscratch2   , [rpc], #1
 846                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 847                 ADD     rscratch    , rscratch, reg_x, LSR #16
 848                 BIC     rscratch, rscratch, #0xFF000000
 849 .endm
 850 .macro          AbsoluteLongIndexedX1
 851                 ADD3MEM
 852                 LDRB    rscratch2    , [rpc, #1]
 853                 LDRB    rscratch   , [rpc], #2
 854                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 855                 LDRB    rscratch2   , [rpc], #1
 856                 ORR     rscratch    , rscratch, rscratch2, LSL #16
 857                 ADD     rscratch    , rscratch, reg_x, LSR #24
 858                 BIC     rscratch, rscratch, #0xFF000000
 859 .endm
 860 .macro          Direct
 861                 ADD1MEM
 862                 LDRB    rscratch    , [rpc], #1
 863                 ADD     rscratch    , reg_d, rscratch, LSL #16
 864                 MOV     rscratch, rscratch, LSR #16
 865 .endm
 866 .macro          DirectIndirect
 867                 ADD1MEM
 868                 LDRB    rscratch    , [rpc], #1
 869                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 870                 MOV     rscratch, rscratch, LSR #16
 871                 S9xGetWordLow
 872                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
 873 .endm
 874 .macro          DirectIndirectLong
 875                 ADD1MEM
 876                 LDRB                    rscratch    , [rpc], #1
 877                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 878                 MOV                     rscratch, rscratch, LSR #16
 879                 S9xGetWordLowRegNS      rscratch2
 880                 ADD                     rscratch    , rscratch,#2
 881                 STMFD                   r13!,{rscratch2}
 882                 S9xGetByteLow
 883                 LDMFD                   r13!,{rscratch2}
 884                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 885 .endm
 886 .macro          DirectIndirectIndexed0
 887                 ADD1MEM
 888                 LDRB    rscratch    , [rpc], #1
 889                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 890                 MOV     rscratch, rscratch, LSR #16
 891                 S9xGetWordLow
 892                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 893                 ADD     rscratch, rscratch,reg_y, LSR #16
 894 .endm
 895 .macro          DirectIndirectIndexed1
 896                 ADD1MEM
 897                 LDRB    rscratch    , [rpc], #1
 898                 ADD     rscratch    , reg_d, rscratch,   LSL #16
 899                 MOV     rscratch, rscratch, LSR #16
 900                 S9xGetWordLow
 901                 ORR     rscratch, rscratch,reg_d_bank, LSL #16
 902                 ADD     rscratch, rscratch,reg_y, LSR #24
 903 .endm
 904 .macro          DirectIndirectIndexedLong0
 905                 ADD1MEM
 906                 LDRB                    rscratch    , [rpc], #1
 907                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 908                 MOV                     rscratch, rscratch, LSR #16
 909                 S9xGetWordLowRegNS      rscratch2
 910                 ADD                     rscratch    , rscratch,#2
 911                 STMFD                   r13!,{rscratch2}
 912                 S9xGetByteLow
 913                 LDMFD                   r13!,{rscratch2}
 914                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 915                 ADD                     rscratch, rscratch,reg_y, LSR #16
 916 .endm
 917 .macro          DirectIndirectIndexedLong1
 918                 ADD1MEM
 919                 LDRB                    rscratch    , [rpc], #1
 920                 ADD                     rscratch    , reg_d, rscratch,   LSL #16
 921                 MOV                     rscratch, rscratch, LSR #16
 922                 S9xGetWordLowRegNS      rscratch2
 923                 ADD                     rscratch    , rscratch,#2
 924                 STMFD                   r13!,{rscratch2}
 925                 S9xGetByteLow
 926                 LDMFD                   r13!,{rscratch2}
 927                 ORR                     rscratch   , rscratch2, rscratch, LSL #16
 928                 ADD                     rscratch, rscratch,reg_y, LSR #24
 929 .endm
 930 .macro          DirectIndexedIndirect0
 931                 ADD1CYCLE1MEM
 932                 LDRB    rscratch    , [rpc], #1
 933                 ADD     rscratch2   , reg_d , reg_x
 934                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 935                 MOV     rscratch, rscratch, LSR #16
 936                 S9xGetWordLow
 937                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 938 .endm
 939 .macro          DirectIndexedIndirect1
 940                 ADD1CYCLE1MEM
 941                 LDRB    rscratch    , [rpc], #1
 942                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 943                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 944                 MOV     rscratch, rscratch, LSR #16
 945                 S9xGetWordLow
 946                 ORR     rscratch    , rscratch , reg_d_bank, LSL #16
 947 .endm
 948 .macro          DirectIndexedX0
 949                 ADD1CYCLE1MEM
 950                 LDRB    rscratch    , [rpc], #1
 951                 ADD     rscratch2   , reg_d , reg_x
 952                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 953                 MOV     rscratch, rscratch, LSR #16
 954 .endm
 955 .macro          DirectIndexedX1
 956                 ADD1CYCLE1MEM
 957                 LDRB    rscratch    , [rpc], #1
 958                 ADD     rscratch2   , reg_d , reg_x, LSR #8
 959                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 960                 MOV     rscratch, rscratch, LSR #16
 961 .endm
 962 .macro          DirectIndexedY0
 963                 ADD1CYCLE1MEM
 964                 LDRB    rscratch    , [rpc], #1
 965                 ADD     rscratch2   , reg_d , reg_y
 966                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 967                 MOV     rscratch, rscratch, LSR #16
 968 .endm
 969 .macro          DirectIndexedY1
 970                 ADD1CYCLE1MEM
 971                 LDRB    rscratch    , [rpc], #1
 972                 ADD     rscratch2   , reg_d , reg_y, LSR #8
 973                 ADD     rscratch    , rscratch2 , rscratch, LSL #16
 974                 MOV     rscratch, rscratch, LSR #16
 975 .endm
 976 .macro          Immediate8
 977                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 978                 SUB     rscratch, rscratch, regpcbase
 979                 ADD     rpc, rpc, #1
 980 .endm
 981 .macro          Immediate16
 982                 ADD     rscratch, rpc, reg_p_bank, LSL #16
 983                 SUB     rscratch, rscratch, regpcbase
 984                 ADD     rpc, rpc, #2
 985 .endm
 986 .macro          asmRelative
 987                 ADD1MEM
 988                 LDRSB   rscratch    , [rpc],#1
 989                 ADD     rscratch , rscratch , rpc
 990                 SUB     rscratch , rscratch, regpcbase
 991                 UXTH rscratch,rscratch
 992 .endm
 993 .macro          asmRelativeLong
 994                 ADD1CYCLE2MEM
 995                 LDRB    rscratch2    , [rpc, #1]
 996                 LDRB    rscratch   , [rpc], #2
 997                 ORR     rscratch    , rscratch, rscratch2, LSL #8
 998                 SUB     rscratch2    , rpc, regpcbase
 999                 ADD     rscratch    , rscratch2, rscratch
1000                 BIC     rscratch,rscratch,#0x00FF0000
1001 .endm
1002
1003
1004 .macro          StackasmRelative
1005                 ADD1CYCLE1MEM
1006                 LDRB    rscratch    , [rpc], #1
1007                 ADD     rscratch    , rscratch, reg_s
1008                 BIC     rscratch,rscratch,#0x00FF0000
1009 .endm
1010 .macro          StackasmRelativeIndirectIndexed0
1011                 ADD2CYCLE1MEM
1012                 LDRB    rscratch    , [rpc], #1
1013                 ADD     rscratch    , rscratch, reg_s
1014                 BIC     rscratch,rscratch,#0x00FF0000
1015                 S9xGetWordLow
1016                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1017                 ADD     rscratch    , rscratch, reg_y, LSR #16
1018                 BIC     rscratch, rscratch, #0xFF000000
1019 .endm
1020 .macro          StackasmRelativeIndirectIndexed1
1021                 ADD2CYCLE1MEM
1022                 LDRB    rscratch    , [rpc], #1
1023                 ADD     rscratch    , rscratch, reg_s
1024                 BIC     rscratch,rscratch,#0x00FF0000
1025                 S9xGetWordLow
1026                 ORR     rscratch    , rscratch, reg_d_bank, LSL #16
1027                 ADD     rscratch    , rscratch, reg_y, LSR #24
1028                 BIC     rscratch, rscratch, #0xFF000000
1029 .endm
1030
1031
1032 /****************************************/
1033 .macro          PushB           reg
1034                 MOV             rscratch,reg_s
1035                 S9xSetByte      \reg
1036                 SUB             reg_s,reg_s,#1
1037 .endm
1038 .macro          PushBLow        reg
1039                 MOV             rscratch,reg_s
1040                 S9xSetByteLow   \reg
1041                 SUB             reg_s,reg_s,#1
1042 .endm
1043 .macro          PushWLow        reg
1044                 SUB             rscratch,reg_s,#1
1045                 S9xSetWordLow   \reg
1046                 SUB             reg_s,reg_s,#2
1047 .endm
1048 .macro          PushWrLow
1049                 MOV             rscratch2,rscratch
1050                 SUB             rscratch,reg_s,#1
1051                 S9xSetWordLow   rscratch2
1052                 SUB             reg_s,reg_s,#2
1053 .endm
1054 .macro          PushW           reg
1055                 SUB             rscratch,reg_s,#1
1056                 S9xSetWord      \reg
1057                 SUB             reg_s,reg_s,#2
1058 .endm
1059
1060 /********/
1061
1062 .macro          PullB           reg
1063                 ADD             rscratch,reg_s,#1
1064                 S9xGetByteLow
1065                 ADD             reg_s,reg_s,#1
1066                 MOV             \reg,rscratch,LSL #24
1067 .endm
1068 .macro          PullBr
1069                 ADD             rscratch,reg_s,#1
1070                 S9xGetByte
1071                 ADD             reg_s,reg_s,#1
1072 .endm
1073 .macro          PullBLow        reg
1074                 ADD             rscratch,reg_s,#1
1075                 S9xGetByteLow
1076                 ADD             reg_s,reg_s,#1
1077                 MOV             \reg,rscratch
1078 .endm
1079 .macro          PullBrLow
1080                 ADD             rscratch,reg_s,#1
1081                 S9xGetByteLow
1082                 ADD             reg_s,reg_s,#1
1083 .endm
1084 .macro          PullW           reg
1085                 ADD             rscratch,reg_s,#1
1086                 S9xGetWordLow
1087                 ADD             reg_s,reg_s,#2
1088                 MOV             \reg,rscratch,LSL #16
1089 .endm
1090
1091 .macro          PullWLow        reg
1092                 ADD             rscratch,reg_s,#1
1093                 S9xGetWordLow
1094                 ADD             reg_s,reg_s,#2
1095                 MOV             \reg,rscratch
1096 .endm
1097
1098
1099 /*****************/
1100 .macro          PullBS          reg
1101                 ADD             rscratch,reg_s,#1
1102                 S9xGetByteLow
1103                 ADD             reg_s,reg_s,#1
1104                 MOVS            \reg,rscratch,LSL #24
1105 .endm
1106 .macro          PullBrS
1107                 ADD             rscratch,reg_s,#1
1108                 S9xGetByteLow
1109                 ADD             reg_s,reg_s,#1
1110                 MOVS            rscratch,rscratch,LSL #24
1111 .endm
1112 .macro          PullBLowS       reg
1113                 ADD             rscratch,reg_s,#1
1114                 S9xGetByteLow
1115                 ADD             reg_s,reg_s,#1
1116                 MOVS            \reg,rscratch
1117 .endm
1118 .macro          PullBrLowS
1119                 ADD             rscratch,reg_s,#1
1120                 S9xGetByteLow
1121                 ADD             reg_s,reg_s,#1
1122                 MOVS            rscratch,rscratch
1123 .endm
1124 .macro          PullWS          reg
1125                 ADD             rscratch,reg_s,#1
1126                 S9xGetWordLow
1127                 ADD             reg_s,reg_s,#2
1128                 MOVS            \reg,rscratch, LSL #16
1129 .endm
1130 .macro          PullWrS
1131                 ADD             rscratch,reg_s,#1
1132                 S9xGetWordLow
1133                 ADD             reg_s,reg_s,#2
1134                 MOVS            rscratch,rscratch, LSL #16
1135 .endm
1136 .macro          PullWLowS       reg
1137                 ADD             rscratch,reg_s,#1
1138                 S9xGetWordLow
1139                 ADD             reg_s,reg_s,#2
1140                 MOVS            \reg,rscratch
1141 .endm
1142 .macro          PullWrLowS
1143                 ADD             rscratch,reg_s,#1
1144                 S9xGetWordLow
1145                 ADD             reg_s,reg_s,#2
1146                 MOVS            rscratch,rscratch
1147 .endm
1148
1149 @ START OF PROGRAM CODE
1150
1151 .text
1152
1153 .globl asmS9xGetByte
1154 .globl asmS9xGetWord
1155 .globl asmS9xSetByte
1156 .globl asmS9xSetWord
1157
1158 @ uint8 aaS9xGetByte(uint32 address);
1159 asmS9xGetByte:
1160         @  in : R0  = 0x00hhmmll
1161         @  out : R0 = 0x000000ll
1162         @  DESTROYED : R1,R2,R3
1163         @  UPDATE : reg_cycles
1164         @ R1 <= block
1165         MOV             R1,R0,LSR #MEMMAP_SHIFT
1166         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1167         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1168         @ so AND MEMMAP_MASK is BIC 0xFF000
1169         BIC             R1,R1,#0xFF000
1170         @ R2 <= Map[block] (GetAddress)
1171         LDR             R2,[reg_cpu_var,#Map_ofs]
1172         LDR             R2,[R2,R1,LSL #2]
1173         CMP             R2,#MAP_LAST
1174         BLO             GBSpecial  @ special
1175         @  Direct ROM/RAM acess
1176         @ R2 <= GetAddress + Address & 0xFFFF
1177         @ R3 <= MemorySpeed[block]
1178         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1179         MOV             R0,R0,LSL #16
1180         LDRB            R3,[R3,R1]
1181         ADD             R2,R2,R0,LSR #16
1182         @ Update CPU.Cycles
1183         ADD             reg_cycles,reg_cycles,R3
1184         @ R3 = BlockIsRAM[block]
1185         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1186         @ Get value to return
1187         LDRB            R0,[R2]
1188         LDRB            R3,[R3,R1]
1189         MOVS            R3,R3
1190         @  if BlockIsRAM => update for CPUShutdown
1191         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1192         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1193
1194         LDMFD           R13!,{PC} @ Return
1195 GBSpecial:
1196
1197         LDR             PC,[PC,R2,LSL #2]
1198         MOV             R0,R0           @ nop, for align
1199         .long GBPPU
1200         .long GBCPU
1201         .long GBDSP
1202         .long GBLSRAM
1203         .long GBHSRAM
1204         .long GBNONE
1205         .long GBDEBUG
1206         .long GBC4
1207         .long GBBWRAM
1208         .long GBNONE
1209         .long GBNONE
1210         .long GBNONE
1211         /*.long GB7ROM
1212         .long GB7RAM
1213         .long GB7SRM*/
1214 GBPPU:
1215         @ InDMA ?
1216         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1217         MOVS            R1,R1
1218         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1219         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1220         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1221         MOV             R0,R0,LSR #16
1222                 PREPARE_C_CALL
1223         BL              S9xGetPPU
1224                 RESTORE_C_CALL
1225         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1226         LDMFD           R13!,{PC} @ Return
1227 GBCPU:
1228         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1229         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1230         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1231         MOV             R0,R0,LSR #16
1232                 PREPARE_C_CALL
1233         BL              S9xGetCPU
1234                 RESTORE_C_CALL
1235         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1236         LDMFD           R13!,{PC} @ Return
1237 GBDSP:
1238         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1239         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1240         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1241         MOV             R0,R0,LSR #16
1242                 PREPARE_C_CALL
1243         BL              S9xGetDSP
1244                 RESTORE_C_CALL
1245         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1246         LDMFD           R13!,{PC} @ Return
1247 GBLSRAM:
1248         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1249         LDRH            R2,[reg_cpu_var,#SRAMMask]
1250         LDR             R1,[reg_cpu_var,#SRAM]
1251         AND             R0,R2,R0                @ Address&SRAMMask
1252         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1253         LDMFD           R13!,{PC}
1254 GB7SRM:
1255 GBHSRAM:
1256         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1257
1258         MOV             R1,R0,LSL #17
1259         AND             R2,R0,#0xF0000
1260         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1261         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1262         ADD             R0,R2,R1
1263         LDRH            R2,[reg_cpu_var,#SRAMMask]
1264         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1265         LDR             R1,[reg_cpu_var,#SRAM]
1266         AND             R0,R2,R0                @ Address&SRAMMask
1267         LDRB            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1268         LDMFD           R13!,{PC}               @ return
1269 GB7ROM:
1270 GB7RAM:
1271 GBNONE:
1272         MOV             R0,R0,LSR #8
1273         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1274         AND             R0,R0,#0xFF
1275         LDMFD           R13!,{PC}
1276 @ GBDEBUG:
1277         /*ADD           reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1278         MOV             R0,#0
1279         LDMFD           R13!,{PC}*/
1280 GBC4:
1281         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1282         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1283         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1284         MOV             R0,R0,LSR #16
1285                 PREPARE_C_CALL
1286         BL              S9xGetC4
1287                 RESTORE_C_CALL
1288         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1289         LDMFD           R13!,{PC} @ Return
1290 GBDEBUG:
1291 GBBWRAM:
1292         MOV             R0,R0,LSL #17
1293         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1294         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1295         LDR             R1,[reg_cpu_var,#BWRAM]
1296         SUB             R0,R0,#0x6000   @ ((Address & 0x7fff) - 0x6000)
1297         LDRB            R0,[R0,R1]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1298         LDMFD           R13!,{PC}
1299
1300
1301 @ uint16 aaS9xGetWord(uint32 address);
1302 asmS9xGetWord:
1303         @  in : R0  = 0x00hhmmll
1304         @  out : R0 = 0x000000ll
1305         @  DESTROYED : R1,R2,R3
1306         @  UPDATE : reg_cycles
1307
1308
1309         MOV             R1,R0,LSL #19
1310         ADDS            R1,R1,#0x80000
1311         @ if = 0x1FFF => 0
1312         BNE             GW_NotBoundary
1313
1314         STMFD           R13!,{R0}
1315                 STMFD           R13!,{PC}
1316         B               asmS9xGetByte
1317                 MOV             R0,R0
1318         LDMFD           R13!,{R1}
1319         STMFD           R13!,{R0}
1320         ADD             R0,R1,#1
1321                 STMFD           R13!,{PC}
1322         B               asmS9xGetByte
1323                 MOV             R0,R0
1324         LDMFD           R13!,{R1}
1325         ORR             R0,R1,R0,LSL #8
1326         LDMFD           R13!,{PC}
1327
1328 GW_NotBoundary:
1329
1330         @ R1 <= block
1331         MOV             R1,R0,LSR #MEMMAP_SHIFT
1332         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1333         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1334         @ so AND MEMMAP_MASK is BIC 0xFF000
1335         BIC             R1,R1,#0xFF000
1336         @ R2 <= Map[block] (GetAddress)
1337         LDR             R2,[reg_cpu_var,#Map_ofs]
1338         LDR             R2,[R2,R1,LSL #2]
1339         CMP             R2,#MAP_LAST
1340         BLO             GWSpecial  @ special
1341         @  Direct ROM/RAM acess
1342
1343         TST             R0,#1
1344         BNE             GW_Not_Aligned1
1345         @ R2 <= GetAddress + Address & 0xFFFF
1346         @ R3 <= MemorySpeed[block]
1347         LDR             R3,[reg_cpu_var,#MemorySpeed_ofs]
1348         MOV             R0,R0,LSL #16
1349         LDRB            R3,[R3,R1]
1350         MOV             R0,R0,LSR #16
1351         @ Update CPU.Cycles
1352         ADD             reg_cycles,reg_cycles,R3, LSL #1
1353         @ R3 = BlockIsRAM[block]
1354         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1355         @ Get value to return
1356         LDRH            R0,[R2,R0]
1357         LDRB            R3,[R3,R1]
1358         MOVS            R3,R3
1359         @  if BlockIsRAM => update for CPUShutdown
1360         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1361         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1362
1363         LDMFD           R13!,{PC} @ Return
1364 GW_Not_Aligned1:
1365
1366         MOV             R0,R0,LSL #16
1367         ADD             R3,R0,#0x10000
1368         LDRB            R3,[R2,R3,LSR #16]      @ GetAddress+ (Address+1)&0xFFFF
1369         LDRB            R0,[R2,R0,LSR #16]      @ GetAddress+ Address&0xFFFF
1370         ORR             R0,R0,R3,LSL #8
1371
1372         @  if BlockIsRAM => update for CPUShutdown
1373         LDR             R3,[reg_cpu_var,#BlockIsRAM_ofs]
1374         LDR             R2,[reg_cpu_var,#MemorySpeed_ofs]
1375         LDRB            R3,[R3,R1]   @ R3 = BlockIsRAM[block]
1376         LDRB            R2,[R2,R1]   @ R2 <= MemorySpeed[block]
1377         MOVS            R3,R3       @ IsRAM ? CPUShutdown stuff
1378         LDRNE           R1,[reg_cpu_var,#PCAtOpcodeStart_ofs]
1379         STRNE           R1,[reg_cpu_var,#WaitAddress_ofs]
1380         ADD             reg_cycles,reg_cycles,R2, LSL #1 @ Update CPU.Cycles
1381         LDMFD           R13!,{PC}  @ Return
1382 GWSpecial:
1383         LDR             PC,[PC,R2,LSL #2]
1384         MOV             R0,R0           @ nop, for align
1385         .long GWPPU
1386         .long GWCPU
1387         .long GWDSP
1388         .long GWLSRAM
1389         .long GWHSRAM
1390         .long GWNONE
1391         .long GWDEBUG
1392         .long GWC4
1393         .long GWBWRAM
1394         .long GWNONE
1395         .long GWNONE
1396         .long GWNONE
1397         /*.long GW7ROM
1398         .long GW7RAM
1399         .long GW7SRM*/
1400 /*      MAP_PPU, MAP_CPU, MAP_DSP, MAP_LOROM_SRAM, MAP_HIROM_SRAM,
1401         MAP_NONE, MAP_DEBUG, MAP_C4, MAP_BWRAM, MAP_BWRAM_BITMAP,
1402         MAP_BWRAM_BITMAP2, MAP_SA1RAM, MAP_LAST*/
1403
1404 GWPPU:
1405         @ InDMA ?
1406         LDRB            R1,[reg_cpu_var,#InDMA_ofs]
1407         MOVS            R1,R1
1408         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1409         MOV             R0,R0,LSL #16   @ S9xGetPPU(Address&0xFFFF);
1410         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1411         MOV             R0,R0,LSR #16
1412                 PREPARE_C_CALL_R0
1413         BL              S9xGetPPU
1414         LDMFD           R13!,{R1}
1415         STMFD           R13!,{R0}
1416         ADD             R0,R1,#1
1417         @ BIC           R0,R0,#0x10000
1418         BL              S9xGetPPU
1419                 RESTORE_C_CALL_R1
1420         ORR             R0,R1,R0,LSL #8
1421         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1422         LDMFD           R13!,{PC} @ Return
1423 GWCPU:
1424         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1425         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1426         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1427         MOV             R0,R0,LSR #16
1428                 PREPARE_C_CALL_R0
1429         BL              S9xGetCPU
1430         LDMFD           R13!,{R1}
1431         STMFD           R13!,{R0}
1432         ADD             R0,R1,#1
1433         @ BIC           R0,R0,#0x10000
1434         BL              S9xGetCPU
1435                 RESTORE_C_CALL_R1
1436         ORR             R0,R1,R0,LSL #8
1437         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1438         LDMFD           R13!,{PC} @ Return
1439 GWDSP:
1440         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1441         MOV             R0,R0,LSL #16 @ S9xGetCPU(Address&0xFFFF);
1442         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1443         MOV             R0,R0,LSR #16
1444                 PREPARE_C_CALL_R0
1445         BL              S9xGetDSP
1446         LDMFD           R13!,{R1}
1447         STMFD           R13!,{R0}
1448         ADD             R0,R1,#1
1449         @ BIC           R0,R0,#0x10000
1450         BL              S9xGetDSP
1451                 RESTORE_C_CALL_R1
1452         ORR             R0,R1,R0,LSL #8
1453         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1454         LDMFD           R13!,{PC} @ Return
1455 GWLSRAM:
1456         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1457
1458         TST             R0,#1
1459         BNE             GW_Not_Aligned2
1460         LDRH            R2,[reg_cpu_var,#SRAMMask]
1461         LDR             R1,[reg_cpu_var,#SRAM]
1462         AND             R3,R2,R0                @ Address&SRAMMask
1463         LDRH            R0,[R3,R1]              @ *Memory.SRAM + Address&SRAMMask
1464         LDMFD           R13!,{PC}       @ return
1465 GW_Not_Aligned2:
1466         LDRH            R2,[reg_cpu_var,#SRAMMask]
1467         LDR             R1,[reg_cpu_var,#SRAM]
1468         AND             R3,R2,R0                @ Address&SRAMMask
1469         ADD             R0,R0,#1
1470         AND             R2,R0,R2                @ Address&SRAMMask
1471         LDRB            R3,[R1,R3]              @ *Memory.SRAM + Address&SRAMMask
1472         LDRB            R2,[R1,R2]              @ *Memory.SRAM + Address&SRAMMask
1473         ORR             R0,R3,R2,LSL #8
1474         LDMFD           R13!,{PC}       @ return
1475 GW7SRM:
1476 GWHSRAM:
1477         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1478
1479         TST             R0,#1
1480         BNE             GW_Not_Aligned3
1481
1482         MOV             R1,R0,LSL #17
1483         AND             R2,R0,#0xF0000
1484         MOV             R1,R1,LSR #17   @ Address&0x7FFF
1485         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1486         ADD             R0,R2,R1
1487         LDRH            R2,[reg_cpu_var,#SRAMMask]
1488         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1489         LDR             R1,[reg_cpu_var,#SRAM]
1490         AND             R0,R2,R0                @ Address&SRAMMask
1491         LDRH            R0,[R1,R0]              @ *Memory.SRAM + Address&SRAMMask
1492         LDMFD           R13!,{PC}               @ return
1493
1494 GW_Not_Aligned3:
1495         MOV             R3,R0,LSL #17
1496         AND             R2,R0,#0xF0000
1497         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1498         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1499         ADD             R2,R2,R3
1500         ADD             R0,R0,#1
1501         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1502         MOV             R3,R0,LSL #17
1503         AND             R0,R0,#0xF0000
1504         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1505         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1506         ADD             R0,R0,R3
1507         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1508         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1509         AND             R2,R3,R2                @ Address...&SRAMMask
1510         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1511
1512         LDR             R3,[reg_cpu_var,#SRAM]
1513         LDRB            R0,[R0,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1514         LDRB            R2,[R2,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1515         ORR             R0,R2,R0,LSL #8
1516
1517         LDMFD           R13!,{PC}               @ return
1518 GW7ROM:
1519 GW7RAM:
1520 GWNONE:
1521         MOV             R0,R0,LSL #16
1522         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1523         MOV             R0,R0,LSR #24
1524         ORR             R0,R0,R0,LSL #8
1525         LDMFD           R13!,{PC}
1526 GWDEBUG:
1527         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1528         MOV             R0,#0
1529         LDMFD           R13!,{PC}
1530 GWC4:
1531         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1532         MOV             R0,R0,LSL #16 @ S9xGetC4(Address&0xFFFF);
1533         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1534         MOV             R0,R0,LSR #16
1535                 PREPARE_C_CALL_R0
1536         BL              S9xGetC4
1537         LDMFD           R13!,{R1}
1538         STMFD           R13!,{R0}
1539         ADD             R0,R1,#1
1540         @ BIC           R0,R0,#0x10000
1541         BL              S9xGetC4
1542                 RESTORE_C_CALL_R1
1543         ORR             R0,R1,R0,LSL #8
1544         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1545         LDMFD           R13!,{PC} @ Return
1546 GWBWRAM:
1547         TST             R0,#1
1548         BNE             GW_Not_Aligned4
1549         MOV             R0,R0,LSL #17
1550         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1551         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1552         LDR             R1,[reg_cpu_var,#BWRAM]
1553         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1554         LDRH            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1555         LDMFD           R13!,{PC}               @ return
1556 GW_Not_Aligned4:
1557         MOV             R0,R0,LSL #17
1558         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1559         ADD             R3,R0,#0x20000
1560         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1561         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1562         LDR             R1,[reg_cpu_var,#BWRAM]
1563         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1564         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
1565         LDRB            R0,[R1,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1566         LDRB            R3,[R1,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
1567         ORR             R0,R0,R3,LSL #8
1568         LDMFD           R13!,{PC}               @ return
1569
1570
1571
1572
1573 @ void aaS9xSetByte(uint32 address,uint8 val);
1574 asmS9xSetByte:
1575         @  in : R0=0x00hhmmll  R1=0x000000ll
1576         @  DESTROYED : R0,R1,R2,R3
1577         @  UPDATE : reg_cycles
1578         @ cpu shutdown
1579         MOV             R2,#0
1580         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1581         @
1582
1583         @ R3 <= block
1584         MOV             R3,R0,LSR #MEMMAP_SHIFT
1585         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1586         @ R0 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1587         @ so AND MEMMAP_MASK is BIC 0xFF000
1588         BIC             R3,R3,#0xFF000
1589         @ R2 <= Map[block] (SetAddress)
1590         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1591         LDR             R2,[R2,R3,LSL #2]
1592         CMP             R2,#MAP_LAST
1593         BLO             SBSpecial  @ special
1594         @  Direct ROM/RAM acess
1595
1596         @ R2 <= SetAddress + Address & 0xFFFF
1597         MOV             R0,R0,LSL #16
1598         ADD             R2,R2,R0,LSR #16
1599         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1600         @ Set byte
1601         STRB            R1,[R2]
1602         @ R0 <= MemorySpeed[block]
1603         LDRB            R0,[R0,R3]
1604         @ Update CPU.Cycles
1605         ADD             reg_cycles,reg_cycles,R0
1606         @ CPUShutdown
1607         @ only SA1 here : TODO
1608         @ Return
1609         LDMFD           R13!,{PC}
1610 SBSpecial:
1611         LDR             PC,[PC,R2,LSL #2]
1612         MOV             R0,R0           @ nop, for align
1613         .long SBPPU
1614         .long SBCPU
1615         .long SBDSP
1616         .long SBLSRAM
1617         .long SBHSRAM
1618         .long SBNONE
1619         .long SBDEBUG
1620         .long SBC4
1621         .long SBBWRAM
1622         .long SBNONE
1623         .long SBNONE
1624         .long SBNONE
1625         /*.long SB7ROM
1626         .long SB7RAM
1627         .long SB7SRM*/
1628 SBPPU:
1629         @ InDMA ?
1630         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1631         MOVS            R2,R2
1632         ADDEQ           reg_cycles,reg_cycles,#ONE_CYCLE                @ No -> update Cycles
1633         MOV             R0,R0,LSL #16
1634         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1635         MOV             R0,R0,LSR #16
1636                 PREPARE_C_CALL
1637         MOV             R12,R0
1638         UXTB    R0,R1
1639         MOV             R1,R12
1640         BL              S9xSetPPU
1641                 RESTORE_C_CALL
1642         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1643         LDMFD           R13!,{PC} @ Return
1644 SBCPU:
1645         ADD             reg_cycles,reg_cycles,#ONE_CYCLE        @ update Cycles
1646         MOV             R0,R0,LSL #16
1647         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1648         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1649                 PREPARE_C_CALL
1650         MOV             R12,R0
1651         UXTB    R0,R1
1652         MOV             R1,R12
1653         BL              S9xSetCPU
1654                 RESTORE_C_CALL
1655         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1656         LDMFD           R13!,{PC} @ Return
1657 SBDSP:
1658         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1659         MOV             R0,R0,LSL #16
1660         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1661         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1662                 PREPARE_C_CALL
1663         MOV             R12,R0
1664         UXTB    R0,R1
1665         MOV             R1,R12
1666         BL              S9xSetDSP
1667                 RESTORE_C_CALL
1668         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1669         LDMFD           R13!,{PC} @ Return
1670 SBLSRAM:
1671         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1672         LDRH            R2,[reg_cpu_var,#SRAMMask]
1673         MOVS            R2,R2
1674         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1675         LDR             R3,[reg_cpu_var,#SRAM]
1676         AND             R0,R2,R0                @ Address&SRAMMask
1677         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1678
1679         MOV             R0,#1
1680         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1681         LDMFD           R13!,{PC}  @ return
1682 SB7SRM:
1683 SBHSRAM:
1684         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1685
1686         MOV             R3,R0,LSL #17
1687         AND             R2,R0,#0xF0000
1688         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1689         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1690         ADD             R0,R2,R3
1691
1692         LDRH            R2,[reg_cpu_var,#SRAMMask]
1693         MOVS            R2,R2
1694         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1695
1696         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1697         LDR             R3,[reg_cpu_var,#SRAM]
1698         AND             R0,R2,R0                @ Address&SRAMMask
1699         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1700
1701         MOV             R0,#1
1702         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1703         LDMFD           R13!,{PC}       @ return
1704 SB7ROM:
1705 SB7RAM:
1706 SBNONE:
1707 SBDEBUG:
1708         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1709         LDMFD           R13!,{PC}
1710 SBC4:
1711         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1712         MOV             R0,R0,LSL #16
1713         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1714         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1715                 PREPARE_C_CALL
1716         MOV             R12,R0
1717         UXTB    R0,R1
1718         MOV             R1,R12
1719         BL              S9xSetC4
1720                 RESTORE_C_CALL
1721         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1722         LDMFD           R13!,{PC} @ Return
1723 SBBWRAM:
1724         MOV             R0,R0,LSL #17
1725         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1726         MOV             R0,R0,LSR #17   @ Address&0x7FFF
1727         LDR             R2,[reg_cpu_var,#BWRAM]
1728         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
1729         STRB            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
1730
1731         MOV             R0,#1
1732         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1733
1734         LDMFD           R13!,{PC}
1735
1736
1737
1738 @ void aaS9xSetWord(uint32 address,uint16 val);
1739 asmS9xSetWord:
1740         @  in : R0  = 0x00hhmmll R1=0x0000hhll
1741         @  DESTROYED : R0,R1,R2,R3
1742         @  UPDATE : reg_cycles
1743         @ R1 <= block
1744
1745         MOV             R2,R0,LSL #19
1746         ADDS            R2,R2,#0x80000
1747         @ if = 0x1FFF => 0
1748         BNE             SW_NotBoundary
1749
1750         STMFD           R13!,{R0,R1}
1751                 STMFD           R13!,{PC}
1752         B               asmS9xSetByte
1753                 MOV             R0,R0
1754         LDMFD           R13!,{R0,R1}
1755         ADD             R0,R0,#1
1756         MOV             R1,R1,LSR #8
1757                 STMFD           R13!,{PC}
1758         B               asmS9xSetByte
1759                 MOV             R0,R0
1760
1761         LDMFD           R13!,{PC}
1762
1763 SW_NotBoundary:
1764
1765         MOV             R2,#0
1766         STR             R2,[reg_cpu_var,#WaitAddress_ofs]
1767         @
1768         @ R3 <= block
1769         MOV             R3,R0,LSR #MEMMAP_SHIFT
1770         @ MEMMAP_SHIFT is 12, Address is 0xFFFFFFFF at max, so
1771         @ R1 is maxed by 0x000FFFFF, MEMMAP_MASK is 0x1000-1=0xFFF
1772         @ so AND MEMMAP_MASK is BIC 0xFF000
1773         BIC             R3,R3,#0xFF000
1774         @ R2 <= Map[block] (SetAddress)
1775         LDR             R2,[reg_cpu_var,#WriteMap_ofs]
1776         LDR             R2,[R2,R3,LSL #2]
1777         CMP             R2,#MAP_LAST
1778         BLO             SWSpecial  @ special
1779         @  Direct ROM/RAM acess
1780
1781
1782         @ check if address is 16bits aligned or not
1783         TST             R0,#1
1784         BNE             SW_not_aligned1
1785         @ aligned
1786         MOV             R0,R0,LSL #16
1787         ADD             R2,R2,R0,LSR #16        @ address & 0xFFFF + SetAddress
1788         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1789         @ Set word
1790         STRH            R1,[R2]
1791         @ R1 <= MemorySpeed[block]
1792         LDRB            R0,[R0,R3]
1793         @ Update CPU.Cycles
1794         ADD             reg_cycles,reg_cycles,R0, LSL #1
1795         @ CPUShutdown
1796         @ only SA1 here : TODO
1797         @ Return
1798         LDMFD           R13!,{PC}
1799
1800 SW_not_aligned1:
1801         @ R1 = (Address&0xFFFF)<<16
1802         MOV             R0,R0,LSL #16
1803         @ First write @address
1804         STRB            R1,[R2,R0,LSR #16]
1805         ADD             R0,R0,#0x10000
1806         MOV             R1,R1,LSR #8
1807         @ Second write @address+1
1808         STRB            R1,[R2,R0,LSR #16]
1809         @ R1 <= MemorySpeed[block]
1810         LDR             R0,[reg_cpu_var,#MemorySpeed_ofs]
1811         LDRB            R0,[R0,R3]
1812         @ Update CPU.Cycles
1813         ADD             reg_cycles,reg_cycles,R0,LSL #1
1814         @ CPUShutdown
1815         @ only SA1 here : TODO
1816         @ Return
1817         LDMFD           R13!,{PC}
1818 SWSpecial:
1819         LDR             PC,[PC,R2,LSL #2]
1820         MOV             R0,R0           @ nop, for align
1821         .long SWPPU
1822         .long SWCPU
1823         .long SWDSP
1824         .long SWLSRAM
1825         .long SWHSRAM
1826         .long SWNONE
1827         .long SWDEBUG
1828         .long SWC4
1829         .long SWBWRAM
1830         .long SWNONE
1831         .long SWNONE
1832         .long SWNONE
1833         /*.long SW7ROM
1834         .long SW7RAM
1835         .long SW7SRM*/
1836 SWPPU:
1837         @ InDMA ?
1838         LDRB            R2,[reg_cpu_var,#InDMA_ofs]
1839         MOVS            R2,R2
1840         ADDEQ           reg_cycles,reg_cycles,#(ONE_CYCLE*2)            @ No -> update Cycles
1841         MOV             R0,R0,LSL #16
1842         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs]    @ Save Cycles
1843         MOV             R0,R0,LSR #16
1844         MOV             R2,R1
1845         MOV             R1,R0
1846         MOV             R0,R2
1847                 PREPARE_C_CALL_R0R1
1848         UXTB    R0,R0
1849         BL              S9xSetPPU
1850         LDMFD           R13!,{R0,R1}
1851         ADD             R1,R1,#1
1852         UXTB    R0,R0,ROR #8
1853         BIC             R1,R1,#0x10000
1854         BL              S9xSetPPU
1855                 RESTORE_C_CALL
1856         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1857         LDMFD           R13!,{PC} @ Return
1858 SWCPU:
1859         ADD             reg_cycles,reg_cycles,#(ONE_CYCLE*2)    @ update Cycles
1860         MOV             R0,R0,LSL #16
1861         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1862         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1863         MOV             R2,R1
1864         MOV             R1,R0
1865         MOV             R0,R2
1866                 PREPARE_C_CALL_R0R1
1867         UXTB    R0,R0
1868         BL              S9xSetCPU
1869         LDMFD           R13!,{R0,R1}
1870         ADD             R1,R1,#1
1871         UXTB    R0,R0,ROR #8    @ ((R0 >> 8) & 0xFF)
1872         BIC             R1,R1,#0x10000
1873         BL              S9xSetCPU
1874                 RESTORE_C_CALL
1875         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1876         LDMFD           R13!,{PC} @ Return
1877 SWDSP:
1878         ADD             reg_cycles,reg_cycles,#SLOW_ONE_CYCLE   @ update Cycles
1879         MOV             R0,R0,LSL #16
1880         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1881         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1882         MOV             R2,R1
1883         MOV             R1,R0
1884         MOV             R0,R2
1885                 PREPARE_C_CALL_R0R1
1886         UXTB    R0,R0
1887         BL              S9xSetDSP
1888         LDMFD           R13!,{R0,R1}
1889         ADD             R1,R1,#1
1890         UXTB    R0,R0,ROR #8
1891         BIC             R1,R1,#0x10000
1892         BL              S9xSetDSP
1893                 RESTORE_C_CALL
1894         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1895         LDMFD           R13!,{PC} @ Return
1896 SWLSRAM:
1897         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1898         LDRH            R2,[reg_cpu_var,#SRAMMask]
1899         MOVS            R2,R2
1900         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1901
1902         AND             R3,R2,R0                @ Address&SRAMMask
1903         TST             R0,#1
1904         BNE             SW_not_aligned2
1905         @ aligned
1906         LDR             R0,[reg_cpu_var,#SRAM]
1907         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1908         MOV             R0,#1
1909         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1910         LDMFD           R13!,{PC}  @ return
1911 SW_not_aligned2:
1912
1913         ADD             R0,R0,#1
1914         AND             R2,R2,R0                @ (Address+1)&SRAMMask
1915         LDR             R0,[reg_cpu_var,#SRAM]
1916         STRB            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1917         MOV             R1,R1,LSR #8
1918         STRB            R1,[R0,R2]              @ *Memory.SRAM + (Address+1)&SRAMMask
1919         MOV             R0,#1
1920         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1921         LDMFD           R13!,{PC}  @ return
1922 SW7SRM:
1923 SWHSRAM:
1924         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1925
1926         LDRH            R2,[reg_cpu_var,#SRAMMask]
1927         MOVS            R2,R2
1928         LDMEQFD         R13!,{PC} @ return if SRAMMask=0
1929
1930         TST             R0,#1
1931         BNE             SW_not_aligned3
1932         @ aligned
1933         MOV             R3,R0,LSL #17
1934         AND             R2,R0,#0xF0000
1935         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1936         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1937         ADD             R0,R2,R3
1938         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1939         LDRH            R2,[reg_cpu_var,#SRAMMask]
1940         LDR             R3,[reg_cpu_var,#SRAM]
1941         AND             R0,R2,R0                @ Address&SRAMMask
1942         STRH            R1,[R0,R3]              @ *Memory.SRAM + Address&SRAMMask
1943         MOV             R0,#1
1944         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1945         LDMFD           R13!,{PC}       @ return
1946 SW_not_aligned3:
1947         MOV             R3,R0,LSL #17
1948         AND             R2,R0,#0xF0000
1949         MOV             R3,R3,LSR #17   @ Address&0x7FFF
1950         MOV             R2,R2,LSR #3 @ (Address&0xF0000 >> 3)
1951         ADD             R2,R2,R3
1952         SUB             R2,R2,#0x6000 @ ((Address & 0x7fff) - 0x6000 + ((Address & 0xf0000) >> 3))
1953
1954         ADD             R0,R0,#1
1955         MOV             R3,R0,LSL #17
1956         AND             R0,R0,#0xF0000
1957         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
1958         MOV             R0,R0,LSR #3 @ ((Address+1)&0xF0000 >> 3)
1959         ADD             R0,R0,R3
1960         LDRH            R3,[reg_cpu_var,#SRAMMask]      @ reload mask
1961         SUB             R0,R0,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000 + (((Address+1) & 0xf0000) >> 3))
1962         AND             R2,R3,R2                @ Address...&SRAMMask
1963         AND             R0,R3,R0                @ (Address+1...)&SRAMMask
1964
1965         LDR             R3,[reg_cpu_var,#SRAM]
1966         STRB            R1,[R2,R3]              @ *Memory.SRAM + (Address...)&SRAMMask
1967         MOV             R1,R1,LSR #8
1968         STRB            R1,[R0,R3]              @ *Memory.SRAM + (Address+1...)&SRAMMask
1969
1970         MOV             R0,#1
1971         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
1972         LDMFD           R13!,{PC}       @ return
1973 SW7ROM:
1974 SW7RAM:
1975 SWNONE:
1976 SWDEBUG:
1977         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1978         LDMFD           R13!,{PC}       @ return
1979 SWC4:
1980         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
1981         MOV             R0,R0,LSL #16
1982         STR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Save Cycles
1983         MOV             R0,R0,LSR #16   @ Address&0xFFFF
1984         MOV             R2,R1
1985         MOV             R1,R0
1986         MOV             R0,R2
1987                 PREPARE_C_CALL_R0R1
1988         UXTB    R0,R0
1989         BL              S9xSetC4
1990         LDMFD           R13!,{R0,R1}
1991         ADD             R1,R1,#1
1992         UXTB    R0,R0,ROR #8
1993         BIC             R1,R1,#0x10000
1994         BL              S9xSetC4
1995                 RESTORE_C_CALL
1996         LDR             reg_cycles,[reg_cpu_var,#Cycles_ofs] @ Load Cycles
1997         LDMFD           R13!,{PC} @ Return
1998 SWBWRAM:
1999         ADD             reg_cycles,reg_cycles,#(SLOW_ONE_CYCLE*2)       @ update Cycles
2000         TST             R0,#1
2001         BNE             SW_not_aligned4
2002         @ aligned
2003         MOV             R0,R0,LSL #17
2004         LDR             R2,[reg_cpu_var,#BWRAM]
2005         MOV             R0,R0,LSR #17   @ Address&0x7FFF
2006         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2007         MOV             R3,#1
2008         STRH            R1,[R0,R2]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2009         STRB            R3,[reg_cpu_var,#SRAMModified_ofs]
2010         LDMFD           R13!,{PC}       @ return
2011 SW_not_aligned4:
2012         MOV             R0,R0,LSL #17
2013         ADD             R3,R0,#0x20000
2014         MOV             R0,R0,LSR #17   @ Address&0x7FFF
2015         MOV             R3,R3,LSR #17   @ (Address+1)&0x7FFF
2016         LDR             R2,[reg_cpu_var,#BWRAM]
2017         SUB             R0,R0,#0x6000 @ ((Address & 0x7fff) - 0x6000)
2018         SUB             R3,R3,#0x6000 @ (((Address+1) & 0x7fff) - 0x6000)
2019         STRB            R1,[R2,R0]              @ *Memory.BWRAM + ((Address & 0x7fff) - 0x6000)
2020         MOV             R1,R1,LSR #8
2021         STRB            R1,[R2,R3]              @ *Memory.BWRAM + (((Address+1) & 0x7fff) - 0x6000)
2022         MOV             R0,#1
2023         STRB            R0,[reg_cpu_var,#SRAMModified_ofs]
2024         LDMFD           R13!,{PC}               @ return
2025
2026
2027
2028
2029
2030 /*****************************************************************
2031         FLAGS
2032 *****************************************************************/
2033
2034 .macro          UPDATE_C
2035                 @  CC : ARM Carry Clear
2036                 BICCC   rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2037                 @  CS : ARM Carry Set
2038                 ORRCS   rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2039 .endm
2040 .macro          UPDATE_Z
2041                 @  NE : ARM Zero Clear
2042                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2043                 @  EQ : ARM Zero Set
2044                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2045 .endm
2046 .macro          UPDATE_ZN
2047                 @  NE : ARM Zero Clear
2048                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2049                 @  EQ : ARM Zero Set
2050                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2051                 @  PL : ARM Neg Clear
2052                 BICPL   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2053                 @  MI : ARM Neg Set
2054                 ORRMI   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2055 .endm
2056
2057 /*****************************************************************
2058         OPCODES_MAC
2059 *****************************************************************/
2060
2061
2062
2063
2064 .macro ADC8
2065                 TST rstatus, #MASK_DECIMAL
2066                 BEQ 1111f
2067                 S9xGetByte
2068
2069
2070                 STMFD   R13!,{rscratch}
2071                 MOV     rscratch4,#0x0F000000
2072                 @ rscratch2=xxW1xxxxxxxxxxxx
2073                 AND     rscratch2, rscratch, rscratch4
2074                 @ rscratch=xxW2xxxxxxxxxxxx
2075                 AND     rscratch, rscratch4, rscratch, LSR #4
2076                 @ rscratch3=xxA2xxxxxxxxxxxx
2077                 AND     rscratch3, rscratch4, reg_a, LSR #4
2078                 @ rscratch4=xxA1xxxxxxxxxxxx
2079                 AND     rscratch4,reg_a,rscratch4
2080                 @ R1=A1+W1+CARRY
2081                 TST     rstatus, #MASK_CARRY
2082                 ADDNE   rscratch2, rscratch2, #0x01000000
2083                 ADD     rscratch2,rscratch2,rscratch4
2084                 @  if R1 > 9
2085                 CMP     rscratch2, #0x09000000
2086                 @  then R1 -= 10
2087                 SUBGT   rscratch2, rscratch2, #0x0A000000
2088                 @  then A2++
2089                 ADDGT   rscratch3, rscratch3, #0x01000000
2090                 @  R2 = A2+W2
2091                 ADD     rscratch3, rscratch3, rscratch
2092                 @  if R2 > 9
2093                 CMP     rscratch3, #0x09000000
2094                 @  then R2 -= 10@
2095                 SUBGT   rscratch3, rscratch3, #0x0A000000
2096                 @  then SetCarry()
2097                 ORRGT   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2098                 @  else ClearCarry()
2099                 BICLE   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2100                 @  gather rscratch3 and rscratch2 into ans8
2101                 @  rscratch3 : 0R2000000
2102                 @  rscratch2 : 0R1000000
2103                 @  -> 0xR2R1000000
2104                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2105                 LDMFD   R13!,{rscratch}
2106                 @ only last bit
2107                 AND     rscratch,rscratch,#0x80000000
2108                 @  (register.AL ^ Work8)
2109                 EORS    rscratch3, reg_a, rscratch
2110                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2111                 BNE     1112f
2112                 @  (Work8 ^ Ans8)
2113                 EORS    rscratch3, rscratch2, rscratch
2114                 @  & 0x80
2115                 TSTNE   rscratch3,#0x80000000
2116                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2117                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2118 1112:
2119                 MOVS reg_a, rscratch2
2120                 UPDATE_ZN
2121                 B 1113f
2122 1111:
2123                 S9xGetByteLow
2124                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2125                 SUBCS rscratch, rscratch, #0x100
2126                 ADCS reg_a, reg_a, rscratch, ROR #8
2127                 @ OverFlow
2128                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2129                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2130                 @ Carry
2131                 UPDATE_C
2132                 @ clear lower part
2133                 ANDS reg_a, reg_a, #0xFF000000
2134                 @ Update flag
2135                 UPDATE_ZN
2136 1113:
2137 .endm
2138 /* TO TEST */
2139 .macro ADC16
2140                 TST rstatus, #MASK_DECIMAL
2141                 BEQ 1111f
2142                 S9xGetWord
2143
2144                 @ rscratch = W3W2W1W0........
2145                 LDR     rscratch4, = 0x0F0F0000
2146                 @  rscratch2 = xxW2xxW0xxxxxx
2147                 @  rscratch3 = xxW3xxW1xxxxxx
2148                 AND     rscratch2, rscratch4, rscratch
2149                 AND     rscratch3, rscratch4, rscratch, LSR #4
2150                 @  rscratch2 = xxW3xxW1xxW2xxW0
2151                 ORR     rscratch2, rscratch3, rscratch2, LSR #16
2152                 @  rscratch3 = xxA2xxA0xxxxxx
2153                 @  rscratch4 = xxA3xxA1xxxxxx
2154                 @  rscratch2 = xxA3xxA1xxA2xxA0
2155                 AND     rscratch3, rscratch4, reg_a
2156                 AND     rscratch4, rscratch4, reg_a, LSR #4
2157                 ORR     rscratch3, rscratch4, rscratch3, LSR #16
2158                 ADD     rscratch2, rscratch3, rscratch2
2159                 LDR     rscratch4, = 0x0F0F0000
2160                 @  rscratch2 = A + W
2161                 TST     rstatus, #MASK_CARRY
2162                 ADDNE   rscratch2, rscratch2, #0x1
2163                 @  rscratch2 = A + W + C
2164                 @ A0
2165                 AND     rscratch3, rscratch2, #0x0000001F
2166                 CMP     rscratch3, #0x00000009
2167                 ADDHI   rscratch2, rscratch2, #0x00010000
2168                 SUBHI   rscratch2, rscratch2, #0x0000000A
2169                 @ A1
2170                 AND     rscratch3, rscratch2, #0x001F0000
2171                 CMP     rscratch3, #0x00090000
2172                 ADDHI   rscratch2, rscratch2, #0x00000100
2173                 SUBHI   rscratch2, rscratch2, #0x000A0000
2174                 @ A2
2175                 AND     rscratch3, rscratch2, #0x00001F00
2176                 CMP     rscratch3, #0x00000900
2177                 SUBHI   rscratch2, rscratch2, #0x00000A00
2178                 ADDHI   rscratch2, rscratch2, #0x01000000
2179                 @ A3
2180                 AND     rscratch3, rscratch2, #0x1F000000
2181                 CMP     rscratch3, #0x09000000
2182                 SUBHI   rscratch2, rscratch2, #0x0A000000
2183                 @ SetCarry
2184                 ORRHI   rstatus, rstatus, #MASK_CARRY
2185                 @ ClearCarry
2186                 BICLS   rstatus, rstatus, #MASK_CARRY
2187                 @ rscratch2 = xxR3xxR1xxR2xxR0
2188                 @ Pack result
2189                 @ rscratch3 = xxR3xxR1xxxxxxxx
2190                 AND     rscratch3, rscratch4, rscratch2
2191                 @ rscratch2 = xxR2xxR0xxxxxxxx
2192                 AND     rscratch2, rscratch4, rscratch2,LSL #16
2193                 @ rscratch2 = R3R2R1R0xxxxxxxx
2194                 ORR     rscratch2, rscratch2,rscratch3,LSL #4
2195 @ only last bit
2196                 AND     rscratch,rscratch,#0x80000000
2197                 @  (register.AL ^ Work8)
2198                 EORS    rscratch3, reg_a, rscratch
2199                 BICNE   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2200                 BNE     1112f
2201                 @  (Work8 ^ Ans8)
2202                 EORS    rscratch3, rscratch2, rscratch
2203                 TSTNE   rscratch3,#0x80000000
2204                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2205                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2206 1112:
2207                 MOVS    reg_a, rscratch2
2208                 UPDATE_ZN
2209                 B       1113f
2210 1111:
2211                 S9xGetWordLow
2212                 MOVS rscratch2, rstatus, LSR #MASK_SHIFTER_CARRY
2213                 SUBCS rscratch, rscratch, #0x10000
2214                 ADCS reg_a, reg_a,rscratch, ROR #16
2215                 @ OverFlow
2216                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2217                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2218                 MOV reg_a, reg_a, LSR #16
2219                 @ Carry
2220                 UPDATE_C
2221                 @ clear lower parts
2222                 MOVS reg_a, reg_a, LSL #16
2223                 @ Update flag
2224                 UPDATE_ZN
2225 1113:
2226 .endm
2227
2228
2229 .macro          AND16
2230                 S9xGetWord
2231                 ANDS            reg_a, reg_a, rscratch
2232                 UPDATE_ZN
2233 .endm
2234 .macro          AND8
2235                 S9xGetByte
2236                 ANDS            reg_a, reg_a, rscratch
2237                 UPDATE_ZN
2238 .endm
2239 .macro          A_ASL8
2240                 @  7    instr
2241                 MOVS    reg_a, reg_a, LSL #1
2242                 UPDATE_C
2243                 UPDATE_ZN
2244                 ADD1CYCLE
2245 .endm
2246 .macro          A_ASL16
2247                 @  7    instr
2248                 MOVS    reg_a, reg_a, LSL #1
2249                 UPDATE_C
2250                 UPDATE_ZN
2251                 ADD1CYCLE
2252 .endm
2253 .macro          ASL16
2254                 S9xGetWordRegNS rscratch2             @         do not destroy Opadress in rscratch
2255                 MOVS            rscratch2, rscratch2, LSL #1
2256                 UPDATE_C
2257                 UPDATE_ZN
2258                 S9xSetWord      rscratch2
2259                 ADD1CYCLE
2260 .endm
2261 .macro          ASL8
2262                 S9xGetByteRegNS rscratch2             @         do not destroy Opadress in rscratch
2263                 MOVS            rscratch2, rscratch2, LSL #1
2264                 UPDATE_C
2265                 UPDATE_ZN
2266                 S9xSetByte      rscratch2
2267                 ADD1CYCLE
2268 .endm
2269 .macro          BIT8
2270                 S9xGetByte
2271                 MOVS    rscratch2, rscratch, LSL #1
2272                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2273                 @                                         ARM N = Snes V
2274                 @  If Carry Set, then Set Neg in SNES
2275                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set C to zero
2276                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set C to one
2277                 @  If Neg Set, then Set Overflow in SNES
2278                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set N to zero
2279                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set N to one
2280
2281                 @  Now do a real AND    with A register
2282                 @  Set Zero Flag, bit test
2283                 ANDS    rscratch2, reg_a, rscratch
2284                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2285                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2286 .endm
2287
2288 .macro          BIT16
2289                 S9xGetWord
2290                 MOVS    rscratch2, rscratch, LSL #1
2291                 @  Trick in ASM : shift one more bit    : ARM C = Snes N
2292                 @                                         ARM N = Snes V
2293                 @  If Carry Set, then Set Neg in SNES
2294                 BICCC   rstatus, rstatus, #MASK_NEG     @  0 : AND mask 11111011111 : set N to zero
2295                 ORRCS   rstatus, rstatus, #MASK_NEG     @  1 : OR  mask 00000100000 : set N to one
2296                 @  If Neg Set, then Set Overflow in SNES
2297                 BICPL   rstatus, rstatus, #MASK_OVERFLOW  @  0 : AND mask 11111011111   : set V to zero
2298                 ORRMI   rstatus, rstatus, #MASK_OVERFLOW             @  1 : OR  mask 00000100000        : set V to one
2299                 @  Now do a real AND    with A register
2300                 @  Set Zero Flag, bit test
2301                 ANDS    rscratch2, reg_a, rscratch
2302                 @  Bit set  ->Z=0->xxxNE Clear flag
2303                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2304                 @  Bit clear->Z=1->xxxEQ Set flag
2305                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2306 .endm
2307 .macro          CMP8
2308                 S9xGetByte
2309                 SUBS    rscratch2,reg_a,rscratch
2310                 BICCC   rstatus, rstatus, #MASK_CARRY
2311                 ORRCS   rstatus, rstatus, #MASK_CARRY
2312                 UPDATE_ZN
2313
2314 .endm
2315 .macro          CMP16
2316                 S9xGetWord
2317                 SUBS    rscratch2,reg_a,rscratch
2318                 BICCC   rstatus, rstatus, #MASK_CARRY
2319                 ORRCS   rstatus, rstatus, #MASK_CARRY
2320                 UPDATE_ZN
2321
2322 .endm
2323 .macro          CMX16
2324                 S9xGetWord
2325                 SUBS    rscratch2,reg_x,rscratch
2326                 BICCC   rstatus, rstatus, #MASK_CARRY
2327                 ORRCS   rstatus, rstatus, #MASK_CARRY
2328                 UPDATE_ZN
2329 .endm
2330 .macro          CMX8
2331                 S9xGetByte
2332                 SUBS    rscratch2,reg_x,rscratch
2333                 BICCC   rstatus, rstatus, #MASK_CARRY
2334                 ORRCS   rstatus, rstatus, #MASK_CARRY
2335                 UPDATE_ZN
2336 .endm
2337 .macro          CMY16
2338                 S9xGetWord
2339                 SUBS    rscratch2,reg_y,rscratch
2340                 BICCC   rstatus, rstatus, #MASK_CARRY
2341                 ORRCS   rstatus, rstatus, #MASK_CARRY
2342                 UPDATE_ZN
2343 .endm
2344 .macro          CMY8
2345                 S9xGetByte
2346                 SUBS    rscratch2,reg_y,rscratch
2347                 BICCC   rstatus, rstatus, #MASK_CARRY
2348                 ORRCS   rstatus, rstatus, #MASK_CARRY
2349                 UPDATE_ZN
2350 .endm
2351 .macro          A_DEC8
2352                 MOV             rscratch,#0
2353                 SUBS            reg_a, reg_a, #0x01000000
2354                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2355                 UPDATE_ZN
2356                 ADD1CYCLE
2357 .endm
2358 .macro          A_DEC16
2359                 MOV             rscratch,#0
2360                 SUBS            reg_a, reg_a, #0x00010000
2361                 STR             rscratch,[reg_cpu_var,#WaitAddress_ofs]
2362                 UPDATE_ZN
2363                 ADD1CYCLE
2364 .endm
2365 .macro          DEC16
2366                 S9xGetWordRegNS rscratch2              @  do not        destroy Opadress in rscratch
2367                 MOV             rscratch3,#0
2368                 SUBS            rscratch2, rscratch2, #0x00010000
2369                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2370                 UPDATE_ZN
2371                 S9xSetWord      rscratch2
2372                 ADD1CYCLE
2373 .endm
2374 .macro          DEC8
2375                 S9xGetByteRegNS rscratch2              @  do not        destroy Opadress in rscratch
2376                 MOV             rscratch3,#0
2377                 SUBS            rscratch2, rscratch2, #0x01000000
2378                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2379                 UPDATE_ZN
2380                 S9xSetByte      rscratch2
2381                 ADD1CYCLE
2382 .endm
2383 .macro          EOR16
2384                 S9xGetWord
2385                 EORS            reg_a, reg_a, rscratch
2386                 UPDATE_ZN
2387 .endm
2388 .macro          EOR8
2389                 S9xGetByte
2390                 EORS            reg_a, reg_a, rscratch
2391                 UPDATE_ZN
2392 .endm
2393 .macro          A_INC8
2394                 MOV             rscratch3,#0
2395                 ADDS            reg_a, reg_a, #0x01000000
2396                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2397                 UPDATE_ZN
2398                 ADD1CYCLE
2399 .endm
2400 .macro          A_INC16
2401                 MOV             rscratch3,#0
2402                 ADDS            reg_a, reg_a, #0x00010000
2403                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2404                 UPDATE_ZN
2405                 ADD1CYCLE
2406 .endm
2407 .macro          INC16
2408                 S9xGetWordRegNS rscratch2
2409                 MOV             rscratch3,#0
2410                 ADDS            rscratch2, rscratch2, #0x00010000
2411                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2412                 UPDATE_ZN
2413                 S9xSetWord      rscratch2
2414                 ADD1CYCLE
2415 .endm
2416 .macro          INC8
2417                 S9xGetByteRegNS rscratch2
2418                 MOV             rscratch3,#0
2419                 ADDS            rscratch2, rscratch2, #0x01000000
2420                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2421                 UPDATE_ZN
2422                 S9xSetByte      rscratch2
2423                 ADD1CYCLE
2424 .endm
2425 .macro          LDA16
2426                 S9xGetWordRegStatus reg_a
2427                 UPDATE_ZN
2428 .endm
2429 .macro          LDA8
2430                 S9xGetByteRegStatus reg_a
2431                 UPDATE_ZN
2432 .endm
2433 .macro          LDX16
2434                 S9xGetWordRegStatus reg_x
2435                 UPDATE_ZN
2436 .endm
2437 .macro          LDX8
2438                 S9xGetByteRegStatus reg_x
2439                 UPDATE_ZN
2440 .endm
2441 .macro          LDY16
2442                 S9xGetWordRegStatus reg_y
2443                 UPDATE_ZN
2444 .endm
2445 .macro          LDY8
2446                 S9xGetByteRegStatus reg_y
2447                 UPDATE_ZN
2448 .endm
2449 .macro          A_LSR16
2450                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2451                 MOVS    reg_a, reg_a, LSR #17            @  hhhhhhhh llllllll 00000000 00000000 -> 00000000 00000000 0hhhhhhh hlllllll
2452                 @  Update Zero
2453                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2454                 MOV     reg_a, reg_a, LSL #16                   @  -> 0lllllll 00000000 00000000        00000000
2455                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2456                 @  Note : the two MOV are included between instruction, to optimize
2457                 @  the pipeline.
2458                 UPDATE_C
2459                 ADD1CYCLE
2460 .endm
2461 .macro          A_LSR8
2462                 BIC     rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2463                 MOVS    reg_a, reg_a, LSR #25            @  llllllll 00000000 00000000 00000000 -> 00000000 00000000 00000000 0lllllll
2464                 @  Update Zero
2465                 BICNE   rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2466                 MOV     reg_a, reg_a, LSL #24                   @  -> 00000000 00000000 00000000        0lllllll
2467                 ORREQ   rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2468                 @  Note : the two MOV are included between instruction, to optimize
2469                 @  the pipeline.
2470                 UPDATE_C
2471                 ADD1CYCLE
2472 .endm
2473 .macro          LSR16
2474                 S9xGetWordRegNS rscratch2
2475                 @  N set to zero by >> 1 LSR
2476                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2477                 MOVS            rscratch2, rscratch2, LSR #17              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2478                 @  Update Carry
2479                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2480                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2481                 @  Update Zero
2482                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2483                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2484                 S9xSetWordLow   rscratch2
2485                 ADD1CYCLE
2486 .endm
2487 .macro          LSR8
2488                 S9xGetByteRegNS rscratch2
2489                 @  N set to zero by >> 1 LSR
2490                 BIC             rstatus, rstatus, #MASK_NEG      @  0 : AND mask        11111011111 : set N to zero
2491                 MOVS            rscratch2, rscratch2, LSR #25              @  llllllll 00000000 00000000        00000000 -> 00000000 00000000 00000000 0lllllll
2492                 @  Update Carry
2493                 BICCC           rstatus, rstatus, #MASK_CARRY  @        0 : AND mask 11111011111 : set C to zero
2494                 ORRCS           rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2495                 @  Update Zero
2496                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2497                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2498                 S9xSetByteLow   rscratch2
2499                 ADD1CYCLE
2500 .endm
2501 .macro          ORA8
2502                 S9xGetByte
2503                 ORRS            reg_a, reg_a, rscratch
2504                 UPDATE_ZN
2505 .endm
2506 .macro          ORA16
2507                 S9xGetWord
2508                 ORRS            reg_a, reg_a, rscratch
2509                 UPDATE_ZN
2510 .endm
2511 .macro          A_ROL16
2512                 TST             rstatus, #MASK_CARRY
2513                 ORRNE           reg_a, reg_a, #0x00008000
2514                 MOVS            reg_a, reg_a, LSL #1
2515                 UPDATE_ZN
2516                 UPDATE_C
2517                 ADD1CYCLE
2518 .endm
2519 .macro          A_ROL8
2520                 TST             rstatus, #MASK_CARRY
2521                 ORRNE           reg_a, reg_a, #0x00800000
2522                 MOVS            reg_a, reg_a, LSL #1
2523                 UPDATE_ZN
2524                 UPDATE_C
2525                 ADD1CYCLE
2526 .endm
2527 .macro          ROL16
2528                 S9xGetWordRegNS rscratch2
2529                 TST             rstatus, #MASK_CARRY
2530                 ORRNE           rscratch2, rscratch2, #0x00008000
2531                 MOVS            rscratch2, rscratch2, LSL #1
2532                 UPDATE_ZN
2533                 UPDATE_C
2534                 S9xSetWord      rscratch2
2535                 ADD1CYCLE
2536 .endm
2537 .macro          ROL8
2538                 S9xGetByteRegNS rscratch2
2539                 TST             rstatus, #MASK_CARRY
2540                 ORRNE           rscratch2, rscratch2, #0x00800000
2541                 MOVS            rscratch2, rscratch2, LSL #1
2542                 UPDATE_ZN
2543                 UPDATE_C
2544                 S9xSetByte      rscratch2
2545                 ADD1CYCLE
2546 .endm
2547 .macro          A_ROR16
2548                 MOV                     reg_a,reg_a, LSR #16
2549                 TST                     rstatus, #MASK_CARRY
2550                 ORRNE                   reg_a, reg_a, #0x00010000
2551                 ORRNE                   rstatus,rstatus,#MASK_NEG
2552                 BICEQ                   rstatus,rstatus,#MASK_NEG
2553                 MOVS                    reg_a,reg_a,LSR #1
2554                 UPDATE_C
2555                 UPDATE_Z
2556                 MOV                     reg_a,reg_a, LSL #16
2557                 ADD1CYCLE
2558 .endm
2559 .macro          A_ROR8
2560                 MOV                     reg_a,reg_a, LSR #24
2561                 TST                     rstatus, #MASK_CARRY
2562                 ORRNE                   reg_a, reg_a, #0x00000100
2563                 ORRNE                   rstatus,rstatus,#MASK_NEG
2564                 BICEQ                   rstatus,rstatus,#MASK_NEG
2565                 MOVS                    reg_a,reg_a,LSR #1
2566                 UPDATE_C
2567                 UPDATE_Z
2568                 MOV                     reg_a,reg_a, LSL #24
2569                 ADD1CYCLE
2570 .endm
2571 .macro          ROR16
2572                 S9xGetWordLowRegNS      rscratch2
2573                 TST                     rstatus, #MASK_CARRY
2574                 ORRNE                   rscratch2, rscratch2, #0x00010000
2575                 ORRNE                   rstatus,rstatus,#MASK_NEG
2576                 BICEQ                   rstatus,rstatus,#MASK_NEG
2577                 MOVS                    rscratch2,rscratch2,LSR #1
2578                 UPDATE_C
2579                 UPDATE_Z
2580                 S9xSetWordLow   rscratch2
2581                 ADD1CYCLE
2582
2583 .endm
2584 .macro          ROR8
2585                 S9xGetByteLowRegNS      rscratch2
2586                 TST                     rstatus, #MASK_CARRY
2587                 ORRNE                   rscratch2, rscratch2, #0x00000100
2588                 ORRNE                   rstatus,rstatus,#MASK_NEG
2589                 BICEQ                   rstatus,rstatus,#MASK_NEG
2590                 MOVS                    rscratch2,rscratch2,LSR #1
2591                 UPDATE_C
2592                 UPDATE_Z
2593                 S9xSetByteLow   rscratch2
2594                 ADD1CYCLE
2595 .endm
2596
2597 .macro SBC16
2598         TST rstatus, #MASK_DECIMAL
2599                 BEQ 1111f
2600                 @ TODO
2601                 S9xGetWord
2602
2603                 STMFD   R13!,{rscratch9}
2604                 MOV     rscratch9,#0x000F0000
2605         @ rscratch2 - result
2606         @ rscratch3 - scratch
2607         @ rscratch4 - scratch
2608         @ rscratch9 - pattern
2609
2610                 AND     rscratch2, rscratch, #0x000F0000
2611                 TST     rstatus, #MASK_CARRY
2612                 ADDEQ   rscratch2, rscratch2, #0x00010000  @ W1=W1+!Carry
2613                 AND     rscratch4, reg_a, #0x000F0000
2614         SUB     rscratch2, rscratch4,rscratch2          @ R1=A1-W1-!Carry
2615                 CMP     rscratch2, #0x00090000  @  if R1 > 9
2616                 ADDHI   rscratch2, rscratch2, #0x000A0000 @  then R1 += 10
2617                 AND         rscratch2, rscratch2, #0x000F0000
2618
2619                 AND     rscratch3, rscratch9, rscratch, LSR #4
2620         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W2++)
2621
2622                 AND     rscratch4, rscratch9, reg_a, LSR #4
2623         SUB     rscratch3, rscratch4, rscratch3         @ R2=A2-W2
2624                 CMP     rscratch3, #0x00090000  @  if R2 > 9
2625                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R2 += 10
2626                 AND         rscratch3, rscratch3, #0x000F0000
2627                 ORR         rscratch2, rscratch2, rscratch3,LSL #4
2628
2629                 AND     rscratch3, rscratch9, rscratch, LSR #8
2630         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2631
2632                 AND     rscratch4, rscratch9, reg_a, LSR #8
2633         SUB     rscratch3, rscratch4, rscratch3         @ R3=A3-W3
2634                 CMP     rscratch3, #0x00090000  @  if R3 > 9
2635                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R3 += 10
2636                 AND         rscratch3, rscratch3, #0x000F0000
2637                 ORR         rscratch2, rscratch2, rscratch3,LSL #8
2638
2639                 AND     rscratch3, rscratch9, rscratch, LSR #12
2640         ADDHI   rscratch3, rscratch3, #0x00010000  @  then (W3++)
2641
2642                 AND     rscratch4, rscratch9, reg_a, LSR #12
2643         SUB     rscratch3, rscratch4, rscratch3         @ R4=A4-W4
2644                 CMP     rscratch3, #0x00090000  @  if R4 > 9
2645                 ADDHI   rscratch3, rscratch3, #0x000A0000 @  then R4 += 10
2646                 BICHI   rstatus, rstatus, #MASK_CARRY   @  then ClearCarry
2647                 ORRLS   rstatus, rstatus, #MASK_CARRY   @  else SetCarry
2648
2649                 AND         rscratch3,rscratch3,#0x000F0000
2650                 ORR         rscratch2,rscratch2,rscratch3,LSL #12
2651
2652                 LDMFD   R13!,{rscratch9}
2653                 @ only last bit
2654                 AND     reg_a,reg_a,#0x80000000
2655                 @  (register.A.W ^ Work8)
2656                 EORS    rscratch3, reg_a, rscratch
2657                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2658                 BEQ     1112f
2659                 @  (register.A.W ^ Ans8)
2660                 EORS    rscratch3, reg_a, rscratch2
2661                 @  & 0x80
2662                 TSTNE   rscratch3,#0x80000000
2663                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2664                 ORRNE   rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2665 1112:
2666                 MOVS    reg_a, rscratch2
2667                 UPDATE_ZN
2668                 B 1113f
2669 1111:
2670                 S9xGetWordLow
2671                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2672                 SBCS reg_a, reg_a, rscratch, LSL #16
2673                 @ OverFlow
2674                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2675                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2676                 MOV reg_a, reg_a, LSR #16
2677                 @ Carry
2678                 UPDATE_C
2679                 MOVS reg_a, reg_a, LSL #16
2680                 @ Update flag
2681                 UPDATE_ZN
2682 1113:
2683 .endm
2684
2685 .macro SBC8
2686                 TST rstatus, #MASK_DECIMAL
2687                 BEQ 1111f
2688                 S9xGetByte
2689                 STMFD   R13!,{rscratch}
2690                 MOV     rscratch4,#0x0F000000
2691                 @ rscratch2=xxW1xxxxxxxxxxxx
2692                 AND     rscratch2, rscratch, rscratch4
2693                 @ rscratch=xxW2xxxxxxxxxxxx
2694                 AND     rscratch, rscratch4, rscratch, LSR #4
2695                 @ rscratch3=xxA2xxxxxxxxxxxx
2696                 AND     rscratch3, rscratch4, reg_a, LSR #4
2697                 @ rscratch4=xxA1xxxxxxxxxxxx
2698                 AND     rscratch4,reg_a,rscratch4
2699                 @ R1=A1-W1-!CARRY
2700                 TST     rstatus, #MASK_CARRY
2701                 ADDEQ   rscratch2, rscratch2, #0x01000000
2702                 SUB     rscratch2,rscratch4,rscratch2
2703                 @  if R1 > 9
2704                 CMP     rscratch2, #0x09000000
2705                 @  then R1 += 10
2706                 ADDHI   rscratch2, rscratch2, #0x0A000000
2707                 @  then A2-- (W2++)
2708                 ADDHI   rscratch, rscratch, #0x01000000
2709                 @  R2=A2-W2
2710                 SUB     rscratch3, rscratch3, rscratch
2711                 @  if R2 > 9
2712                 CMP     rscratch3, #0x09000000
2713                 @  then R2 -= 10@
2714                 ADDHI   rscratch3, rscratch3, #0x0A000000
2715                 @  then SetCarry()
2716                 BICHI   rstatus, rstatus, #MASK_CARRY @  1 : OR mask 00000100000 : set C to one
2717                 @  else ClearCarry()
2718                 ORRLS   rstatus, rstatus, #MASK_CARRY @  0 : AND mask 11111011111 : set C to zero
2719                 @  gather rscratch3 and rscratch2 into ans8
2720                 AND     rscratch3,rscratch3,#0x0F000000
2721                 AND     rscratch2,rscratch2,#0x0F000000
2722                 @  rscratch3 : 0R2000000
2723                 @  rscratch2 : 0R1000000
2724                 @  -> 0xR2R1000000
2725                 ORR     rscratch2, rscratch2, rscratch3, LSL #4
2726                 LDMFD   R13!,{rscratch}
2727                 @ only last bit
2728                 AND     reg_a,reg_a,#0x80000000
2729                 @  (register.AL ^ Work8)
2730                 EORS    rscratch3, reg_a, rscratch
2731                 BICEQ   rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2732                 BEQ     1112f
2733                 @  (register.AL ^ Ans8)
2734                 EORS    rscratch3, reg_a, rscratch2
2735                 @  & 0x80
2736                 TSTNE   rscratch3,#0x80000000
2737                 BICEQ rstatus, rstatus, #MASK_OVERFLOW @  0 : AND mask 11111011111 : set V to zero
2738                 ORRNE rstatus, rstatus, #MASK_OVERFLOW @  1 : OR mask 00000100000 : set V to one
2739 1112:
2740                 MOVS reg_a, rscratch2
2741                 UPDATE_ZN
2742                 B 1113f
2743 1111:
2744                 S9xGetByteLow
2745                 MOVS rscratch2,rstatus,LSR #MASK_SHIFTER_CARRY
2746                 SBCS reg_a, reg_a, rscratch, LSL #24
2747                 @ OverFlow
2748                 ORRVS rstatus, rstatus, #MASK_OVERFLOW
2749                 BICVC rstatus, rstatus, #MASK_OVERFLOW
2750                 @ Carry
2751                 UPDATE_C
2752                 @ Update flag
2753                 ANDS reg_a, reg_a, #0xFF000000
2754                 UPDATE_ZN
2755 1113:
2756 .endm
2757
2758 .macro          STA16
2759                 S9xSetWord      reg_a
2760 .endm
2761 .macro          STA8
2762                 S9xSetByte      reg_a
2763 .endm
2764 .macro          STX16
2765                 S9xSetWord      reg_x
2766 .endm
2767 .macro          STX8
2768                 S9xSetByte      reg_x
2769 .endm
2770 .macro          STY16
2771                 S9xSetWord      reg_y
2772 .endm
2773 .macro          STY8
2774                 S9xSetByte      reg_y
2775 .endm
2776 .macro          STZ16
2777                 S9xSetWordZero
2778 .endm
2779 .macro          STZ8
2780                 S9xSetByteZero
2781 .endm
2782 .macro          TSB16
2783                 S9xGetWordRegNS rscratch2
2784                 TST             reg_a, rscratch2
2785                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2786                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2787                 ORR             rscratch2, reg_a, rscratch2
2788                 S9xSetWord      rscratch2
2789                 ADD1CYCLE
2790 .endm
2791 .macro          TSB8
2792                 S9xGetByteRegNS rscratch2
2793                 TST             reg_a, rscratch2
2794                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2795                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2796                 ORR             rscratch2, reg_a, rscratch2
2797                 S9xSetByte      rscratch2
2798                 ADD1CYCLE
2799 .endm
2800 .macro          TRB16
2801                 S9xGetWordRegNS rscratch2
2802                 TST             reg_a, rscratch2
2803                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2804                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2805                 MVN             rscratch3, reg_a
2806                 AND             rscratch2, rscratch3, rscratch2
2807                 S9xSetWord      rscratch2
2808                 ADD1CYCLE
2809 .endm
2810 .macro          TRB8
2811                 S9xGetByteRegNS rscratch2
2812                 TST             reg_a, rscratch2
2813                 BICNE           rstatus, rstatus, #MASK_ZERO     @  0 : AND mask        11111011111 : set Z to zero
2814                 ORREQ           rstatus, rstatus, #MASK_ZERO     @  1 : OR  mask        00000100000  : set Z to one
2815                 MVN             rscratch3, reg_a
2816                 AND             rscratch2, rscratch3, rscratch2
2817                 S9xSetByte      rscratch2
2818                 ADD1CYCLE
2819 .endm
2820 /**************************************************************************/
2821
2822
2823 /**************************************************************************/
2824
2825 .macro          Op09M0          /*ORA*/
2826                 LDRB            rscratch2, [rpc,#1]
2827                 LDRB            rscratch, [rpc], #2
2828                 ORR             rscratch2,rscratch,rscratch2,LSL #8
2829                 ORRS            reg_a,reg_a,rscratch2,LSL #16
2830                 UPDATE_ZN
2831                 ADD2MEM
2832 .endm
2833 .macro          Op09M1          /*ORA*/
2834                 LDRB            rscratch, [rpc], #1
2835                 ORRS            reg_a,reg_a,rscratch,LSL #24
2836                 UPDATE_ZN
2837                 ADD1MEM
2838 .endm
2839 /***********************************************************************/
2840 .macro          Op90    /*BCC*/
2841                 asmRelative
2842                 BranchCheck0
2843                 TST             rstatus, #MASK_CARRY
2844                 BNE             1111f
2845                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2846                 ADD1CYCLE
2847                 CPUShutdown
2848 1111:
2849 .endm
2850 .macro          OpB0    /*BCS*/
2851                 asmRelative
2852                 BranchCheck0
2853                 TST             rstatus, #MASK_CARRY
2854                 BEQ             1111f
2855                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2856                 ADD1CYCLE
2857                 CPUShutdown
2858 1111:
2859 .endm
2860 .macro          OpF0    /*BEQ*/
2861                 asmRelative
2862                 BranchCheck2
2863                 TST             rstatus, #MASK_ZERO
2864                 BEQ             1111f
2865                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2866                 ADD1CYCLE
2867                 CPUShutdown
2868 1111:
2869 .endm
2870 .macro          OpD0    /*BNE*/
2871                 asmRelative
2872                 BranchCheck1
2873                 TST             rstatus, #MASK_ZERO
2874                 BNE             1111f
2875                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2876                 ADD1CYCLE
2877                 CPUShutdown
2878 1111:
2879 .endm
2880 .macro          Op30    /*BMI*/
2881                 asmRelative
2882                 BranchCheck0
2883                 TST             rstatus, #MASK_NEG
2884                 BEQ             1111f
2885                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
2886                 ADD1CYCLE
2887                 CPUShutdown
2888 1111:
2889 .endm
2890 .macro          Op10   /*BPL*/
2891                 asmRelative
2892                 BranchCheck1
2893                 TST             rstatus, #MASK_NEG @  neg, z!=0, NE
2894                 BNE             1111f
2895                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2896                 ADD1CYCLE
2897                 CPUShutdown
2898 1111:
2899 .endm
2900 .macro          Op50   /*BVC*/
2901                 asmRelative
2902                 BranchCheck0
2903                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2904                 BNE             1111f
2905                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2906                 ADD1CYCLE
2907                 CPUShutdown
2908 1111:
2909 .endm
2910 .macro          Op70   /*BVS*/
2911                 asmRelative
2912                 BranchCheck0
2913                 TST             rstatus, #MASK_OVERFLOW @  neg, z!=0, NE
2914                 BEQ             1111f
2915                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2916                 ADD1CYCLE
2917                 CPUShutdown
2918 1111:
2919 .endm
2920 .macro          Op80   /*BRA*/
2921                 asmRelative
2922                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress + PCBase
2923                 ADD1CYCLE
2924                 CPUShutdown
2925 1111:
2926 .endm
2927 /*******************************************************************************************/
2928 /************************************************************/
2929 /* SetFlag Instructions ********************************************************************** */
2930 .macro          Op38 /*SEC*/
2931                 ORR             rstatus, rstatus, #MASK_CARRY      @    1 : OR  mask 00000100000 : set C to one
2932                 ADD1CYCLE
2933 .endm
2934 .macro          OpF8 /*SED*/
2935                 SetDecimal
2936                 ADD1CYCLE
2937 .endm
2938 .macro          Op78 /*SEI*/
2939                 SetIRQ
2940                 ADD1CYCLE
2941 .endm
2942
2943
2944 /****************************************************************************************/
2945 /* ClearFlag Instructions ******************************************************************** */
2946 .macro          Op18  /*CLC*/
2947                 BIC             rstatus, rstatus, #MASK_CARRY
2948                 ADD1CYCLE
2949 .endm
2950 .macro          OpD8 /*CLD*/
2951                 ClearDecimal
2952                 ADD1CYCLE
2953 .endm
2954 .macro          Op58  /*CLI*/
2955                 ClearIRQ
2956                 ADD1CYCLE
2957                 @ CHECK_FOR_IRQ
2958 .endm
2959 .macro          OpB8 /*CLV*/
2960                 BIC             rstatus, rstatus, #MASK_OVERFLOW
2961                 ADD1CYCLE
2962 .endm
2963
2964 /******************************************************************************************/
2965 /* DEX/DEY *********************************************************************************** */
2966
2967 .macro          OpCAX1  /*DEX*/
2968                 MOV             rscratch3,#0
2969                 SUBS            reg_x, reg_x, #0x01000000
2970                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2971                 UPDATE_ZN
2972                 ADD1CYCLE
2973 .endm
2974 .macro          OpCAX0  /*DEX*/
2975                 MOV             rscratch3,#0
2976                 SUBS            reg_x, reg_x, #0x00010000
2977                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2978                 UPDATE_ZN
2979                 ADD1CYCLE
2980 .endm
2981 .macro          Op88X1 /*DEY*/
2982                 MOV             rscratch3,#0
2983                 SUBS            reg_y, reg_y, #0x01000000
2984                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2985                 UPDATE_ZN
2986                 ADD1CYCLE
2987 .endm
2988 .macro          Op88X0 /*DEY*/
2989                 MOV             rscratch3,#0
2990                 SUBS            reg_y, reg_y, #0x00010000
2991                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
2992                 UPDATE_ZN
2993                 ADD1CYCLE
2994 .endm
2995
2996 /******************************************************************************************/
2997 /* INX/INY *********************************************************************************** */
2998 .macro          OpE8X1
2999                 MOV             rscratch3,#0
3000                 ADDS            reg_x, reg_x, #0x01000000
3001                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3002                 UPDATE_ZN
3003                 ADD1CYCLE
3004 .endm
3005 .macro          OpE8X0
3006                 MOV             rscratch3,#0
3007                 ADDS            reg_x, reg_x, #0x00010000
3008                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3009                 UPDATE_ZN
3010                 ADD1CYCLE
3011 .endm
3012 .macro          OpC8X1
3013                 MOV             rscratch3,#0
3014                 ADDS            reg_y, reg_y, #0x01000000
3015                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3016                 UPDATE_ZN
3017                 ADD1CYCLE
3018 .endm
3019 .macro          OpC8X0
3020                 MOV             rscratch3,#0
3021                 ADDS            reg_y, reg_y, #0x00010000
3022                 STR             rscratch3,[reg_cpu_var,#WaitAddress_ofs]
3023                 UPDATE_ZN
3024                 ADD1CYCLE
3025 .endm
3026
3027 /**********************************************************************************************/
3028
3029 /* NOP *************************************************************************************** */
3030 .macro          OpEA
3031                 ADD1CYCLE
3032 .endm
3033
3034 /**************************************************************************/
3035 /* PUSH Instructions **************************************************** */
3036 .macro          OpF4
3037                 Absolute
3038                 PushWrLow
3039 .endm
3040 .macro          OpD4
3041                 DirectIndirect
3042                 PushWrLow
3043 .endm
3044 .macro          Op62
3045                 asmRelativeLong
3046                 PushWrLow
3047 .endm
3048 .macro          Op48M0
3049                 PushW           reg_a
3050                 ADD1CYCLE
3051 .endm
3052 .macro          Op48M1
3053                 PushB           reg_a
3054                 ADD1CYCLE
3055 .endm
3056 .macro          Op8B
3057                 AND             rscratch2, reg_d_bank, #0xFF
3058                 PushBLow        rscratch2
3059                 ADD1CYCLE
3060 .endm
3061 .macro          Op0B
3062                 PushW           reg_d
3063                 ADD1CYCLE
3064 .endm
3065 .macro          Op4B
3066                 PushBlow        reg_p_bank
3067                 ADD1CYCLE
3068 .endm
3069 .macro          Op08
3070                 PushB           rstatus
3071                 ADD1CYCLE
3072 .endm
3073 .macro          OpDAX1
3074                 PushB           reg_x
3075                 ADD1CYCLE
3076 .endm
3077 .macro          OpDAX0
3078                 PushW           reg_x
3079                 ADD1CYCLE
3080 .endm
3081 .macro          Op5AX1
3082                 PushB           reg_y
3083                 ADD1CYCLE
3084 .endm
3085 .macro          Op5AX0
3086                 PushW           reg_y
3087                 ADD1CYCLE
3088 .endm
3089 /**************************************************************************/
3090 /* PULL Instructions **************************************************** */
3091 .macro          Op68M1
3092                 PullBS          reg_a
3093                 UPDATE_ZN
3094                 ADD2CYCLE
3095 .endm
3096 .macro          Op68M0
3097                 PullWS          reg_a
3098                 UPDATE_ZN
3099                 ADD2CYCLE
3100 .endm
3101 .macro          OpAB
3102                 BIC             reg_d_bank,reg_d_bank, #0xFF
3103                 PullBrS
3104                 ORR             reg_d_bank,reg_d_bank,rscratch, LSR #24
3105                 UPDATE_ZN
3106                 ADD2CYCLE
3107 .endm
3108 .macro          Op2B
3109                 BIC             reg_d,reg_d, #0xFF000000
3110                 BIC             reg_d,reg_d, #0x00FF0000
3111                 PullWrS
3112                 ORR             reg_d,rscratch,reg_d
3113                 UPDATE_ZN
3114                 ADD2CYCLE
3115 .endm
3116 .macro          Op28X1M1        /*PLP*/
3117                 @ INDEX set, MEMORY set
3118                 BIC             rstatus,rstatus,#0xFF000000
3119                 PullBr
3120                 ORR             rstatus,rscratch,rstatus
3121                 TST             rstatus, #MASK_INDEX
3122                 @ INDEX clear & was set : 8->16
3123                 MOVEQ           reg_x,reg_x,LSR #8
3124                 MOVEQ           reg_y,reg_y,LSR #8
3125                 TST             rstatus, #MASK_MEM
3126                 @ MEMORY cleared & was set : 8->16
3127                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3128                 MOVEQ           reg_a,reg_a,LSR #8
3129                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3130                 S9xFixCycles
3131                 ADD2CYCLE
3132 .endm
3133 .macro          Op28X0M1        /*PLP*/
3134                 @ INDEX cleared, MEMORY set
3135                 BIC             rstatus,rstatus,#0xFF000000
3136                 PullBr
3137                 ORR             rstatus,rscratch,rstatus
3138                 TST             rstatus, #MASK_INDEX
3139                 @ INDEX set & was cleared : 16->8
3140                 MOVNE           reg_x,reg_x,LSL #8
3141                 MOVNE           reg_y,reg_y,LSL #8
3142                 TST             rstatus, #MASK_MEM
3143                 @ MEMORY cleared & was set : 8->16
3144                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
3145                 MOVEQ           reg_a,reg_a,LSR #8
3146                 ORREQ           reg_a,reg_a,rscratch, LSL #24
3147                 S9xFixCycles
3148                 ADD2CYCLE
3149 .endm
3150 .macro          Op28X1M0        /*PLP*/
3151                 @ INDEX set, MEMORY set
3152                 BIC             rstatus,rstatus,#0xFF000000
3153                 PullBr
3154                 ORR             rstatus,rscratch,rstatus
3155                 TST             rstatus, #MASK_INDEX
3156                 @ INDEX clear & was set : 8->16
3157                 MOVEQ           reg_x,reg_x,LSR #8
3158                 MOVEQ           reg_y,reg_y,LSR #8
3159                 TST             rstatus, #MASK_MEM
3160                 @ MEMORY set & was cleared : 16->8
3161                 MOVNE           rscratch,reg_a,LSR #24
3162                 MOVNE           reg_a,reg_a,LSL #8
3163                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3164                 S9xFixCycles
3165                 ADD2CYCLE
3166 .endm
3167 .macro          Op28X0M0        /*PLP*/
3168                 @ INDEX set, MEMORY set
3169                 BIC             rstatus,rstatus,#0xFF000000
3170                 PullBr
3171                 ORR             rstatus,rscratch,rstatus
3172                 TST             rstatus, #MASK_INDEX
3173                 @ INDEX set & was cleared : 16->8
3174                 MOVNE           reg_x,reg_x,LSL #8
3175                 MOVNE           reg_y,reg_y,LSL #8
3176                 TST             rstatus, #MASK_MEM
3177                 @ MEMORY set & was cleared : 16->8
3178                 MOVNE           rscratch,reg_a,LSR #24
3179                 MOVNE           reg_a,reg_a,LSL #8
3180                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
3181                 S9xFixCycles
3182                 ADD2CYCLE
3183 .endm
3184 .macro          OpFAX1
3185                 PullBS          reg_x
3186                 UPDATE_ZN
3187                 ADD2CYCLE
3188 .endm
3189 .macro          OpFAX0
3190                 PullWS          reg_x
3191                 UPDATE_ZN
3192                 ADD2CYCLE
3193 .endm
3194 .macro          Op7AX1
3195                 PullBS          reg_y
3196                 UPDATE_ZN
3197                 ADD2CYCLE
3198 .endm
3199 .macro          Op7AX0
3200                 PullWS          reg_y
3201                 UPDATE_ZN
3202                 ADD2CYCLE
3203 .endm
3204
3205 /**********************************************************************************************/
3206 /* Transfer Instructions ********************************************************************* */
3207 .macro          OpAAX1M1 /*TAX8*/
3208                 MOVS            reg_x, reg_a
3209                 UPDATE_ZN
3210                 ADD1CYCLE
3211 .endm
3212 .macro          OpAAX0M1 /*TAX16*/
3213                 LDRB            reg_x, [reg_cpu_var,#RAH_ofs]
3214                 MOV             reg_x, reg_x,LSL #24
3215                 ORRS            reg_x, reg_x,reg_a, LSR #8
3216                 UPDATE_ZN
3217                 ADD1CYCLE
3218 .endm
3219 .macro          OpAAX1M0 /*TAX8*/
3220                 MOVS            reg_x, reg_a, LSL #8
3221                 UPDATE_ZN
3222                 ADD1CYCLE
3223 .endm
3224 .macro          OpAAX0M0 /*TAX16*/
3225                 MOVS            reg_x, reg_a
3226                 UPDATE_ZN
3227                 ADD1CYCLE
3228 .endm
3229 .macro          OpA8X1M1 /*TAY8*/
3230                 MOVS            reg_y, reg_a
3231                 UPDATE_ZN
3232                 ADD1CYCLE
3233 .endm
3234 .macro          OpA8X0M1 /*TAY16*/
3235                 LDRB            reg_y, [reg_cpu_var,#RAH_ofs]
3236                 MOV             reg_y, reg_y,LSL #24
3237                 ORRS            reg_y, reg_y,reg_a, LSR #8
3238                 UPDATE_ZN
3239                 ADD1CYCLE
3240 .endm
3241 .macro          OpA8X1M0 /*TAY8*/
3242                 MOVS            reg_y, reg_a, LSL #8
3243                 UPDATE_ZN
3244                 ADD1CYCLE
3245 .endm
3246 .macro          OpA8X0M0 /*TAY16*/
3247                 MOVS            reg_y, reg_a
3248                 UPDATE_ZN
3249                 ADD1CYCLE
3250 .endm
3251 .macro          Op5BM1
3252                 LDRB            rscratch, [reg_cpu_var,#RAH_ofs]
3253                 MOV             reg_d,reg_d,LSL #16
3254                 MOV             rscratch,rscratch,LSL #24
3255                 ORRS            rscratch,rscratch,reg_a, LSR #8
3256                 UPDATE_ZN
3257                 ORR             reg_d,rscratch,reg_d,LSR #16
3258                 ADD1CYCLE
3259 .endm
3260 .macro          Op5BM0
3261                 MOV             reg_d,reg_d,LSL #16
3262                 MOVS            reg_a,reg_a
3263                 UPDATE_ZN
3264                 ORR             reg_d,reg_a,reg_d,LSR #16
3265                 ADD1CYCLE
3266 .endm
3267 .macro          Op1BM1
3268                 TST             rstatus, #MASK_EMUL
3269                 MOVNE           reg_s, reg_a, LSR #24
3270                 ORRNE           reg_s, reg_s, #0x100
3271                 LDREQB          reg_s, [reg_cpu_var,#RAH_ofs]
3272                 ORREQ           reg_s, reg_s, reg_a
3273                 MOVEQ           reg_s, reg_s, ROR #24
3274                 ADD1CYCLE
3275 .endm
3276 .macro          Op1BM0
3277                 MOV             reg_s, reg_a, LSR #16
3278                 ADD1CYCLE
3279 .endm
3280 .macro          Op7BM1
3281                 MOVS            reg_a, reg_d, ASR #16
3282                 UPDATE_ZN
3283                 MOV             rscratch,reg_a,LSR #8
3284                 MOV             reg_a,reg_a, LSL #24
3285                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3286                 ADD1CYCLE
3287 .endm
3288 .macro          Op7BM0
3289                 MOVS            reg_a, reg_d, ASR #16
3290                 UPDATE_ZN
3291                 MOV             reg_a,reg_a, LSL #16
3292                 ADD1CYCLE
3293 .endm
3294 .macro          Op3BM1
3295                 MOV             rscratch,reg_s, LSR #8
3296                 MOVS            reg_a, reg_s, LSL #16
3297                 STRB            rscratch, [reg_cpu_var,#RAH_ofs]
3298                 UPDATE_ZN
3299                 MOV             reg_a,reg_a, LSL #8
3300                 ADD1CYCLE
3301 .endm
3302 .macro          Op3BM0
3303                 MOVS            reg_a, reg_s, LSL #16
3304                 UPDATE_ZN
3305                 ADD1CYCLE
3306 .endm
3307 .macro          OpBAX1
3308                 MOVS            reg_x, reg_s, LSL #24
3309                 UPDATE_ZN
3310                 ADD1CYCLE
3311 .endm
3312 .macro          OpBAX0
3313                 MOVS            reg_x, reg_s, LSL #16
3314                 UPDATE_ZN
3315                 ADD1CYCLE
3316 .endm
3317 .macro          Op8AM1X1
3318                 MOVS            reg_a, reg_x
3319                 UPDATE_ZN
3320                 ADD1CYCLE
3321 .endm
3322 .macro          Op8AM1X0
3323                 MOVS            reg_a, reg_x, LSL #8
3324                 UPDATE_ZN
3325                 ADD1CYCLE
3326 .endm
3327 .macro          Op8AM0X1
3328                 MOVS            reg_a, reg_x, LSR #8
3329                 UPDATE_ZN
3330                 ADD1CYCLE
3331 .endm
3332 .macro          Op8AM0X0
3333                 MOVS            reg_a, reg_x
3334                 UPDATE_ZN
3335                 ADD1CYCLE
3336 .endm
3337 .macro          Op9AX1
3338                 MOV             reg_s, reg_x, LSR #24
3339                 TST             rstatus, #MASK_EMUL
3340                 ORRNE           reg_s, reg_s, #0x100
3341                 ADD1CYCLE
3342 .endm
3343 .macro          Op9AX0
3344                 MOV             reg_s, reg_x, LSR #16
3345                 ADD1CYCLE
3346 .endm
3347 .macro          Op9BX1
3348                 MOVS            reg_y, reg_x
3349                 UPDATE_ZN
3350                 ADD1CYCLE
3351 .endm
3352 .macro          Op9BX0
3353                 MOVS            reg_y, reg_x
3354                 UPDATE_ZN
3355                 ADD1CYCLE
3356 .endm
3357 .macro          Op98M1X1
3358                 MOVS            reg_a, reg_y
3359                 UPDATE_ZN
3360                 ADD1CYCLE
3361 .endm
3362 .macro          Op98M1X0
3363                 MOVS            reg_a, reg_y, LSL #8
3364                 UPDATE_ZN
3365                 ADD1CYCLE
3366 .endm
3367 .macro          Op98M0X1
3368                 MOVS            reg_a, reg_y, LSR #8
3369                 UPDATE_ZN
3370                 ADD1CYCLE
3371 .endm
3372 .macro          Op98M0X0
3373                 MOVS            reg_a, reg_y
3374                 UPDATE_ZN
3375                 ADD1CYCLE
3376 .endm
3377 .macro          OpBBX1
3378                 MOVS            reg_x, reg_y
3379                 UPDATE_ZN
3380                 ADD1CYCLE
3381 .endm
3382 .macro          OpBBX0
3383                 MOVS            reg_x, reg_y
3384                 UPDATE_ZN
3385                 ADD1CYCLE
3386 .endm
3387
3388 /**********************************************************************************************/
3389 /* XCE *************************************************************************************** */
3390
3391 .macro          OpFB
3392     TST         rstatus,#MASK_CARRY
3393     BEQ         1111f
3394     @ CARRY is set
3395     TST         rstatus,#MASK_EMUL
3396     BNE         1112f
3397     @ EMUL is cleared
3398     BIC         rstatus,rstatus,#(MASK_CARRY)
3399     TST         rstatus,#MASK_INDEX
3400     @ X & Y were 16bits before
3401     MOVEQ       reg_x,reg_x,LSL #8
3402     MOVEQ       reg_y,reg_y,LSL #8
3403     TST         rstatus,#MASK_MEM
3404     @ A was 16bits before
3405     @ save AH
3406     MOVEQ       rscratch,reg_a,LSR #24
3407     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3408     MOVEQ       reg_a,reg_a,LSL #8
3409     ORR         rstatus,rstatus,#(MASK_EMUL|MASK_MEM|MASK_INDEX)
3410     AND         reg_s,reg_s,#0xFF
3411     ORR         reg_s,reg_s,#0x100
3412     B           1113f
3413 1112:
3414     @ EMUL is set
3415     TST         rstatus,#MASK_INDEX
3416     @ X & Y were 16bits before
3417     MOVEQ       reg_x,reg_x,LSL #8
3418     MOVEQ       reg_y,reg_y,LSL #8
3419     TST         rstatus,#MASK_MEM
3420     @ A was 16bits before
3421     @ save AH
3422     MOVEQ       rscratch,reg_a,LSR #24
3423     STREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3424     MOVEQ       reg_a,reg_a,LSL #8
3425     ORR         rstatus,rstatus,#(MASK_CARRY|MASK_MEM|MASK_INDEX)
3426     AND         reg_s,reg_s,#0xFF
3427     ORR         reg_s,reg_s,#0x100
3428     B           1113f
3429 1111:
3430     @ CARRY is cleared
3431     TST         rstatus,#MASK_EMUL
3432     BEQ         1115f
3433     @ EMUL was set : X,Y & A were 8bits
3434     @ Now have to check MEMORY & INDEX for potential conversions to 16bits
3435     TST         rstatus,#MASK_INDEX
3436     @  X & Y are now 16bits
3437     MOVEQ       reg_x,reg_x,LSR #8
3438     MOVEQ       reg_y,reg_y,LSR #8
3439     TST         rstatus,#MASK_MEM
3440     @  A is now 16bits
3441     MOVEQ       reg_a,reg_a,LSR #8
3442     @ restore AH
3443     LDREQB      rscratch,[reg_cpu_var,#RAH_ofs]
3444     ORREQ       reg_a,reg_a,rscratch,LSL #24
3445 1115:
3446     BIC         rstatus,rstatus,#(MASK_EMUL)
3447     ORR         rstatus,rstatus,#(MASK_CARRY)
3448 1113:
3449     ADD1CYCLE
3450     S9xFixCycles
3451 .endm
3452
3453 /*******************************************************************************/
3454 /* BRK *************************************************************************/
3455 .macro          Op00            /*BRK*/
3456                 MOV             rscratch,#1
3457                 STRB            rscratch,[reg_cpu_var,#BRKTriggered_ofs]
3458
3459                 TST             rstatus, #MASK_EMUL
3460                 @  EQ is flag to zero (!CheckEmu)
3461                 BNE             2001f@ elseOp00
3462                 PushBLow        reg_p_bank
3463                 SUB             rscratch, rpc, regpcbase
3464                 ADD             rscratch2, rscratch, #1
3465                 PushWLow        rscratch2
3466                 @  PackStatus
3467                 PushB           rstatus
3468                 ClearDecimal
3469                 SetIRQ
3470                 BIC             reg_p_bank, reg_p_bank, #0xFF
3471                 MOV             rscratch, #0xE6
3472                 ORR             rscratch, rscratch, #0xFF00
3473                 S9xGetWordLow
3474                 S9xSetPCBase
3475                 ADD2CYCLE
3476                 B               2002f@ endOp00
3477 2001:@ elseOp00
3478                 SUB             rscratch2, rpc, regpcbase
3479                 PushWLow        rscratch2
3480                 @  PackStatus
3481                 PushB           rstatus
3482                 ClearDecimal
3483                 SetIRQ
3484                 BIC             reg_p_bank,reg_p_bank, #0xFF
3485                 MOV             rscratch, #0xFE
3486                 ORR             rscratch, rscratch, #0xFF00
3487                 S9xGetWordLow
3488                 S9xSetPCBase
3489                 ADD1CYCLE
3490 2002:@ endOp00
3491 .endm
3492
3493
3494 /**********************************************************************************************/
3495 /* BRL ************************************************************************************** */
3496 .macro          Op82    /*BRL*/
3497                 asmRelativeLong
3498                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3499                 S9xSetPCBase
3500 .endm
3501 /**********************************************************************************************/
3502 /* IRQ *************************************************************************************** */
3503 @ void S9xOpcode_IRQ (void)
3504 .macro          S9xOpcode_IRQ   @ IRQ
3505                 TST             rstatus, #MASK_EMUL
3506                 @  EQ is flag to zero (!CheckEmu)
3507                 BNE             2121f@ elseOp02
3508                 PushBLow        reg_p_bank
3509                 SUB             rscratch2, rpc, regpcbase
3510                 PushWLow        rscratch2
3511                 @  PackStatus
3512                 PushB           rstatus
3513                 ClearDecimal
3514                 SetIRQ
3515                 BIC             reg_p_bank, reg_p_bank,#0xFF
3516                 MOV             rscratch, #0xEE
3517                 ORR             rscratch, rscratch, #0xFF00
3518                 S9xGetWordLow
3519                 S9xSetPCBase
3520                 ADD2CYCLE
3521                 B 2122f
3522 2121:@ else
3523                 SUB             rscratch2, rpc, regpcbase
3524                 PushWLow        rscratch2
3525                 @  PackStatus
3526                 PushB           rstatus
3527                 ClearDecimal
3528                 SetIRQ
3529                 BIC             reg_p_bank,reg_p_bank, #0xFF
3530                 MOV             rscratch, #0xFE
3531                 ORR             rscratch, rscratch, #0xFF00
3532                 S9xGetWordLow
3533                 S9xSetPCBase
3534                 ADD1CYCLE
3535 2122:
3536 .endm
3537
3538 /*
3539 void asm_S9xOpcode_IRQ(void)
3540 {
3541     if (!CheckEmulation())
3542     {
3543         PushB (Registers.PB);
3544         PushW (CPU.PC - CPU.PCBase);
3545         PushB (Registers.PL);
3546         ClearDecimal ();
3547         SetIRQ ();
3548
3549         Registers.PB = 0;
3550                 S9xSetPCBase (S9xGetWord (0xFFEE));
3551         CPU.Cycles += TWO_CYCLES;
3552     }
3553     else
3554     {
3555         PushW (CPU.PC - CPU.PCBase);
3556         PushB (Registers.PL);
3557         ClearDecimal ();
3558         SetIRQ ();
3559
3560         Registers.PB = 0;
3561         S9xSetPCBase (S9xGetWord (0xFFFE));
3562         CPU.Cycles += ONE_CYCLE;
3563     }
3564 }
3565 */
3566
3567 /**********************************************************************************************/
3568 /* NMI *************************************************************************************** */
3569 @ void S9xOpcode_NMI (void)
3570 .macro          S9xOpcode_NMI   @ NMI
3571                 TST             rstatus, #MASK_EMUL
3572                 @  EQ is flag to zero (!CheckEmu)
3573                 BNE             2123f@ elseOp02
3574                 PushBLow        reg_p_bank
3575                 SUB             rscratch2, rpc, regpcbase
3576                 PushWLow        rscratch2
3577                 @  PackStatus
3578                 PushB           rstatus
3579                 ClearDecimal
3580                 SetIRQ
3581                 BIC             reg_p_bank, reg_p_bank,#0xFF
3582                 MOV             rscratch, #0xEA
3583                 ORR             rscratch, rscratch, #0xFF00
3584                 S9xGetWordLow
3585                 S9xSetPCBase
3586                 ADD2CYCLE
3587                 B 2124f
3588 2123:@ else
3589                 SUB             rscratch2, rpc, regpcbase
3590                 PushWLow        rscratch2
3591                 @  PackStatus
3592                 PushB           rstatus
3593                 ClearDecimal
3594                 SetIRQ
3595                 BIC             reg_p_bank,reg_p_bank, #0xFF
3596                 MOV             rscratch, #0xFA
3597                 ORR             rscratch, rscratch, #0xFF00
3598                 S9xGetWordLow
3599                 S9xSetPCBase
3600                 ADD1CYCLE
3601 2124:
3602 .endm
3603 /*
3604 void asm_S9xOpcode_NMI(void)
3605 {
3606         if (!CheckEmulation())
3607     {
3608         PushB (Registers.PB);
3609         PushW (CPU.PC - CPU.PCBase);
3610         PushB (Registers.PL);
3611         ClearDecimal ();
3612         SetIRQ ();
3613
3614         Registers.PB = 0;
3615         S9xSetPCBase (S9xGetWord (0xFFEA));
3616         CPU.Cycles += TWO_CYCLES;
3617     }
3618     else
3619     {
3620         PushW (CPU.PC - CPU.PCBase);
3621         PushB (Registers.PL);
3622         ClearDecimal ();
3623         SetIRQ ();
3624
3625         Registers.PB = 0;
3626         S9xSetPCBase (S9xGetWord (0xFFFA));
3627         CPU.Cycles += ONE_CYCLE;
3628     }
3629 }
3630 */
3631
3632 /**********************************************************************************************/
3633 /* COP *************************************************************************************** */
3634 .macro          Op02            /*COP*/
3635                 TST             rstatus, #MASK_EMUL
3636                 @  EQ is flag to zero (!CheckEmu)
3637                 BNE             2021f@ elseOp02
3638                 PushBLow        reg_p_bank
3639                 SUB             rscratch, rpc, regpcbase
3640                 ADD             rscratch2, rscratch, #1
3641                 PushWLow        rscratch2
3642                 @  PackStatus
3643                 PushB           rstatus
3644                 ClearDecimal
3645                 SetIRQ
3646                 BIC             reg_p_bank, reg_p_bank,#0xFF
3647                 MOV             rscratch, #0xE4
3648                 ORR             rscratch, rscratch, #0xFF00
3649                 S9xGetWordLow
3650                 S9xSetPCBase
3651                 ADD2CYCLE
3652                 B 2022f@ endOp02
3653 2021:@ elseOp02
3654                 SUB             rscratch2, rpc, regpcbase
3655                 PushWLow        rscratch2
3656                 @  PackStatus
3657                 PushB           rstatus
3658                 ClearDecimal
3659                 SetIRQ
3660                 BIC             reg_p_bank,reg_p_bank, #0xFF
3661                 MOV             rscratch, #0xF4
3662                 ORR             rscratch, rscratch, #0xFF00
3663                 S9xGetWordLow
3664                 S9xSetPCBase
3665                 ADD1CYCLE
3666 2022:@ endOp02
3667 .endm
3668
3669 /**********************************************************************************************/
3670 /* JML *************************************************************************************** */
3671 .macro          OpDC
3672                 AbsoluteIndirectLong
3673                 BIC             reg_p_bank,reg_p_bank,#0xFF
3674                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3675                 S9xSetPCBase
3676                 ADD2CYCLE
3677 .endm
3678 .macro          Op5C
3679                 AbsoluteLong
3680                 BIC             reg_p_bank,reg_p_bank,#0xFF
3681                 ORR             reg_p_bank,reg_p_bank, rscratch, LSR #16
3682                 S9xSetPCBase
3683 .endm
3684
3685 /**********************************************************************************************/
3686 /* JMP *************************************************************************************** */
3687 .macro          Op4C
3688                 Absolute
3689                 BIC             rscratch, rscratch, #0xFF0000
3690                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3691                 S9xSetPCBase
3692                 CPUShutdown
3693 .endm
3694 .macro          Op6C
3695                 AbsoluteIndirect
3696                 BIC             rscratch, rscratch, #0xFF0000
3697                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3698                 S9xSetPCBase
3699 .endm
3700 .macro          Op7C
3701                 ADD             rscratch, rscratch, reg_p_bank, LSL #16
3702                 S9xSetPCBase
3703                 ADD1CYCLE
3704 .endm
3705
3706 /**********************************************************************************************/
3707 /* JSL/RTL *********************************************************************************** */
3708 .macro          Op22
3709                 PushBlow        reg_p_bank
3710                 SUB             rscratch, rpc, regpcbase
3711                 @ SUB           rscratch2, rscratch2, #1
3712                 ADD             rscratch2, rscratch, #2
3713                 PushWlow        rscratch2
3714                 AbsoluteLong
3715                 BIC             reg_p_bank,reg_p_bank,#0xFF
3716                 ORR             reg_p_bank, reg_p_bank, rscratch, LSR #16
3717                 S9xSetPCBase
3718 .endm
3719 .macro          Op6B
3720                 PullWLow        rpc
3721                 BIC             reg_p_bank,reg_p_bank,#0xFF
3722                 PullBrLow
3723                 ORR             reg_p_bank, reg_p_bank, rscratch
3724                 ADD             rscratch, rpc, #1
3725                 BIC             rscratch, rscratch,#0xFF0000
3726                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3727                 S9xSetPCBase
3728                 ADD2CYCLE
3729 .endm
3730 /**********************************************************************************************/
3731 /* JSR/RTS *********************************************************************************** */
3732 .macro          Op20
3733                 SUB             rscratch, rpc, regpcbase
3734                 @ SUB           rscratch2, rscratch2, #1
3735                 ADD             rscratch2, rscratch, #1
3736                 PushWlow        rscratch2
3737                 Absolute
3738                 BIC             rscratch, rscratch, #0xFF0000
3739                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3740                 S9xSetPCBase
3741                 ADD1CYCLE
3742 .endm
3743 .macro          OpFCX0
3744                 SUB             rscratch, rpc, regpcbase
3745                 @ SUB           rscratch2, rscratch2, #1
3746                 ADD             rscratch2, rscratch, #1
3747                 PushWlow        rscratch2
3748                 AbsoluteIndexedIndirectX0
3749                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3750                 S9xSetPCBase
3751                 ADD1CYCLE
3752 .endm
3753 .macro          OpFCX1
3754                 SUB             rscratch, rpc, regpcbase
3755                 @ SUB           rscratch2, rscratch2, #1
3756                 ADD             rscratch2, rscratch, #1
3757                 PushWlow        rscratch2
3758                 AbsoluteIndexedIndirectX1
3759                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3760                 S9xSetPCBase
3761                 ADD1CYCLE
3762 .endm
3763 .macro          Op60
3764                 PullWLow        rpc
3765                 ADD             rscratch, rpc, #1
3766                 BIC             rscratch, rscratch,#0x10000
3767                 ORR             rscratch, rscratch, reg_p_bank, LSL #16
3768                 S9xSetPCBase
3769                 ADD3CYCLE
3770 .endm
3771
3772 /**********************************************************************************************/
3773 /* MVN/MVP *********************************************************************************** */
3774 .macro          Op54X1M1
3775                 @ Save RegStatus = reg_d_bank >> 24
3776                 MOV             rscratch, reg_d_bank, LSR #16
3777                 LDRB            reg_d_bank    , [rpc], #1
3778                 LDRB            rscratch2    , [rpc], #1
3779                 @ Restore RegStatus = reg_d_bank >> 24
3780                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3781                 MOV             rscratch    , reg_x, LSR #24
3782                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3783                 S9xGetByteLow
3784                 MOV             rscratch2, rscratch
3785                 MOV             rscratch   , reg_y, LSR #24
3786                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3787                 S9xSetByteLow   rscratch2
3788                 @ load 16bits A
3789                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3790                 MOV             reg_a,reg_a,LSR #8
3791                 ORR             reg_a,reg_a,rscratch, LSL #24
3792                 ADD             reg_x, reg_x, #0x01000000
3793                 SUB             reg_a, reg_a, #0x00010000
3794                 ADD             reg_y, reg_y, #0x01000000
3795                 CMP             reg_a, #0xFFFF0000
3796                 SUBNE           rpc, rpc, #3
3797                 @ update AH
3798                 MOV             rscratch, reg_a, LSR #24
3799                 MOV             reg_a,reg_a,LSL #8
3800                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3801                 ADD2CYCLE2MEM
3802 .endm
3803 .macro          Op54X1M0
3804                 @ Save RegStatus = reg_d_bank >> 24
3805                 MOV             rscratch, reg_d_bank, LSR #16
3806                 LDRB            reg_d_bank    , [rpc], #1
3807                 LDRB            rscratch2    , [rpc], #1
3808                 @ Restore RegStatus = reg_d_bank >> 24
3809                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3810                 MOV             rscratch    , reg_x, LSR #24
3811                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3812                 S9xGetByteLow
3813                 MOV             rscratch2, rscratch
3814                 MOV             rscratch   , reg_y, LSR #24
3815                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3816                 S9xSetByteLow   rscratch2
3817                 ADD             reg_x, reg_x, #0x01000000
3818                 SUB             reg_a, reg_a, #0x00010000
3819                 ADD             reg_y, reg_y, #0x01000000
3820                 CMP             reg_a, #0xFFFF0000
3821                 SUBNE           rpc, rpc, #3
3822                 ADD2CYCLE2MEM
3823 .endm
3824 .macro          Op54X0M1
3825                 @ Save RegStatus = reg_d_bank >> 24
3826                 MOV             rscratch, reg_d_bank, LSR #16
3827                 LDRB            reg_d_bank    , [rpc], #1
3828                 LDRB            rscratch2    , [rpc], #1
3829                 @ Restore RegStatus = reg_d_bank >> 24
3830                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3831                 MOV             rscratch    , reg_x, LSR #16
3832                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3833                 S9xGetByteLow
3834                 MOV             rscratch2, rscratch
3835                 MOV             rscratch   , reg_y, LSR #16
3836                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3837                 S9xSetByteLow   rscratch2
3838                 @ load 16bits A
3839                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3840                 MOV             reg_a,reg_a,LSR #8
3841                 ORR             reg_a,reg_a,rscratch, LSL #24
3842                 ADD             reg_x, reg_x, #0x00010000
3843                 SUB             reg_a, reg_a, #0x00010000
3844                 ADD             reg_y, reg_y, #0x00010000
3845                 CMP             reg_a, #0xFFFF0000
3846                 SUBNE           rpc, rpc, #3
3847                 @ update AH
3848                 MOV             rscratch, reg_a, LSR #24
3849                 MOV             reg_a,reg_a,LSL #8
3850                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3851                 ADD2CYCLE2MEM
3852 .endm
3853 .macro          Op54X0M0
3854                 @ Save RegStatus = reg_d_bank >> 24
3855                 MOV             rscratch, reg_d_bank, LSR #16
3856                 LDRB            reg_d_bank    , [rpc], #1
3857                 LDRB            rscratch2    , [rpc], #1
3858                 @ Restore RegStatus = reg_d_bank >> 24
3859                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3860                 MOV             rscratch    , reg_x, LSR #16
3861                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3862                 S9xGetByteLow
3863                 MOV             rscratch2, rscratch
3864                 MOV             rscratch   , reg_y, LSR #16
3865                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3866                 S9xSetByteLow   rscratch2
3867                 ADD             reg_x, reg_x, #0x00010000
3868                 SUB             reg_a, reg_a, #0x00010000
3869                 ADD             reg_y, reg_y, #0x00010000
3870                 CMP             reg_a, #0xFFFF0000
3871                 SUBNE           rpc, rpc, #3
3872                 ADD2CYCLE2MEM
3873 .endm
3874
3875 .macro          Op44X1M1
3876                 @ Save RegStatus = reg_d_bank >> 24
3877                 MOV             rscratch, reg_d_bank, LSR #16
3878                 LDRB            reg_d_bank    , [rpc], #1
3879                 LDRB            rscratch2    , [rpc], #1
3880                 @ Restore RegStatus = reg_d_bank >> 24
3881                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3882                 MOV             rscratch    , reg_x, LSR #24
3883                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3884                 S9xGetByteLow
3885                 MOV             rscratch2, rscratch
3886                 MOV             rscratch   , reg_y, LSR #24
3887                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3888                 S9xSetByteLow   rscratch2
3889                 @ load 16bits A
3890                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3891                 MOV             reg_a,reg_a,LSR #8
3892                 ORR             reg_a,reg_a,rscratch, LSL #24
3893                 SUB             reg_x, reg_x, #0x01000000
3894                 SUB             reg_a, reg_a, #0x00010000
3895                 SUB             reg_y, reg_y, #0x01000000
3896                 CMP             reg_a, #0xFFFF0000
3897                 SUBNE           rpc, rpc, #3
3898                 @ update AH
3899                 MOV             rscratch, reg_a, LSR #24
3900                 MOV             reg_a,reg_a,LSL #8
3901                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3902                 ADD2CYCLE2MEM
3903 .endm
3904 .macro          Op44X1M0
3905                 @ Save RegStatus = reg_d_bank >> 24
3906                 MOV             rscratch, reg_d_bank, LSR #16
3907                 LDRB            reg_d_bank    , [rpc], #1
3908                 LDRB            rscratch2    , [rpc], #1
3909                 @ Restore RegStatus = reg_d_bank >> 24
3910                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3911                 MOV             rscratch    , reg_x, LSR #24
3912                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3913                 S9xGetByteLow
3914                 MOV             rscratch2, rscratch
3915                 MOV             rscratch   , reg_y, LSR #24
3916                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3917                 S9xSetByteLow   rscratch2
3918                 SUB             reg_x, reg_x, #0x01000000
3919                 SUB             reg_a, reg_a, #0x00010000
3920                 SUB             reg_y, reg_y, #0x01000000
3921                 CMP             reg_a, #0xFFFF0000
3922                 SUBNE           rpc, rpc, #3
3923                 ADD2CYCLE2MEM
3924 .endm
3925 .macro          Op44X0M1
3926                 @ Save RegStatus = reg_d_bank >> 24
3927                 MOV             rscratch, reg_d_bank, LSR #16
3928                 LDRB            reg_d_bank    , [rpc], #1
3929                 LDRB            rscratch2    , [rpc], #1
3930                 @ Restore RegStatus = reg_d_bank >> 24
3931                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3932                 MOV             rscratch    , reg_x, LSR #16
3933                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3934                 S9xGetByteLow
3935                 MOV             rscratch2, rscratch
3936                 MOV             rscratch   , reg_y, LSR #16
3937                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3938                 S9xSetByteLow   rscratch2
3939                 @ load 16bits A
3940                 LDRB            rscratch,[reg_cpu_var,#RAH_ofs]
3941                 MOV             reg_a,reg_a,LSR #8
3942                 ORR             reg_a,reg_a,rscratch, LSL #24
3943                 SUB             reg_x, reg_x, #0x00010000
3944                 SUB             reg_a, reg_a, #0x00010000
3945                 SUB             reg_y, reg_y, #0x00010000
3946                 CMP             reg_a, #0xFFFF0000
3947                 SUBNE           rpc, rpc, #3
3948                 @ update AH
3949                 MOV             rscratch, reg_a, LSR #24
3950                 MOV             reg_a,reg_a,LSL #8
3951                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
3952                 ADD2CYCLE2MEM
3953 .endm
3954 .macro          Op44X0M0
3955                 @ Save RegStatus = reg_d_bank >> 24
3956                 MOV             rscratch, reg_d_bank, LSR #16
3957                 LDRB            reg_d_bank    , [rpc], #1
3958                 LDRB            rscratch2    , [rpc], #1
3959                 @ Restore RegStatus = reg_d_bank >> 24
3960                 ORR             reg_d_bank, reg_d_bank, rscratch, LSL #16
3961                 MOV             rscratch    , reg_x, LSR #16
3962                 ORR             rscratch    , rscratch, rscratch2, LSL #16
3963                 S9xGetByteLow
3964                 MOV             rscratch2, rscratch
3965                 MOV             rscratch   , reg_y, LSR #16
3966                 ORR             rscratch   , rscratch, reg_d_bank, LSL #16
3967                 S9xSetByteLow   rscratch2
3968                 SUB             reg_x, reg_x, #0x00010000
3969                 SUB             reg_a, reg_a, #0x00010000
3970                 SUB             reg_y, reg_y, #0x00010000
3971                 CMP             reg_a, #0xFFFF0000
3972                 SUBNE           rpc, rpc, #3
3973                 ADD2CYCLE2MEM
3974 .endm
3975
3976 /**********************************************************************************************/
3977 /* REP/SEP *********************************************************************************** */
3978 .macro          OpC2
3979                 @  status&=~(*rpc++);
3980                 @  so possible changes are :
3981                 @  INDEX = 1 -> 0  : X,Y 8bits -> 16bits
3982                 @  MEM = 1 -> 0 : A 8bits -> 16bits
3983                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
3984                 MOV             rscratch3, rstatus
3985                 LDRB            rscratch, [rpc], #1
3986                 MVN             rscratch, rscratch
3987                 AND             rstatus,rstatus,rscratch, ROR #(32-STATUS_SHIFTER)
3988                 TST             rstatus,#MASK_EMUL
3989                 BEQ             1111f
3990                 @ emulation mode on : no changes since it was on before opcode
3991                 @ just be sure to reset MEM & INDEX accordingly
3992                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
3993                 B               1112f
3994 1111:
3995                 @ NOT in Emulation mode, check INDEX & MEMORY bits
3996                 @ Now check INDEX
3997                 TST             rscratch3,#MASK_INDEX
3998                 BEQ             1113f
3999                 @  X & Y were 8bit before
4000                 TST             rstatus,#MASK_INDEX
4001                 BNE             1113f
4002                 @  X & Y are now 16bits
4003                 MOV             reg_x,reg_x,LSR #8
4004                 MOV             reg_y,reg_y,LSR #8
4005 1113:           @ X & Y still in 16bits
4006                 @ Now check MEMORY
4007                 TST             rscratch3,#MASK_MEM
4008                 BEQ             1112f
4009                 @  A was 8bit before
4010                 TST             rstatus,#MASK_MEM
4011                 BNE             1112f
4012                 @  A is now 16bits
4013                 MOV             reg_a,reg_a,LSR #8
4014                 @ restore AH
4015                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4016                 ORREQ           reg_a,reg_a,rscratch,LSL #24
4017 1112:
4018                 S9xFixCycles
4019                 ADD1CYCLE1MEM
4020 .endm
4021 .macro          OpE2
4022                 @  status|=*rpc++;
4023                 @  so possible changes are :
4024                 @  INDEX = 0 -> 1  : X,Y 16bits -> 8bits
4025                 @  MEM = 0 -> 1 : A 16bits -> 8bits
4026                 @ SAVE OLD status for MASK_INDEX & MASK_MEM comparison
4027                 MOV             rscratch3, rstatus
4028                 LDRB            rscratch, [rpc], #1
4029                 ORR             rstatus,rstatus,rscratch, LSL #STATUS_SHIFTER
4030                 TST             rstatus,#MASK_EMUL
4031                 BEQ             10111f
4032                 @ emulation mode on : no changes sinc eit was on before opcode
4033                 @ just be sure to have mem & index set accordingly
4034                 ORR             rstatus,rstatus,#(MASK_MEM|MASK_INDEX)
4035                 B               10112f
4036 10111:
4037                 @ NOT in Emulation mode, check INDEX & MEMORY bits
4038                 @ Now check INDEX
4039                 TST             rscratch3,#MASK_INDEX
4040                 BNE             10113f
4041                 @  X & Y were 16bit before
4042                 TST             rstatus,#MASK_INDEX
4043                 BEQ             10113f
4044                 @  X & Y are now 8bits
4045                 MOV             reg_x,reg_x,LSL #8
4046                 MOV             reg_y,reg_y,LSL #8
4047 10113:          @ X & Y still in 16bits
4048                 @ Now check MEMORY
4049                 TST             rscratch3,#MASK_MEM
4050                 BNE             10112f
4051                 @  A was 16bit before
4052                 TST             rstatus,#MASK_MEM
4053                 BEQ             10112f
4054                 @  A is now 8bits
4055                 @  save AH
4056                 MOV             rscratch,reg_a,LSR #24
4057                 MOV             reg_a,reg_a,LSL #8
4058                 STRB            rscratch,[reg_cpu_var,#RAH_ofs]
4059 10112:
4060                 S9xFixCycles
4061                 ADD1CYCLE1MEM
4062 .endm
4063
4064 /**********************************************************************************************/
4065 /* XBA *************************************************************************************** */
4066 .macro          OpEBM1
4067                 @ A is 8bits
4068                 ADD             rscratch,reg_cpu_var,#RAH_ofs
4069                 MOV             reg_a,reg_a, LSR #24
4070                 SWPB            reg_a,reg_a,[rscratch]
4071                 MOVS            reg_a,reg_a, LSL #24
4072                 UPDATE_ZN
4073                 ADD2CYCLE
4074 .endm
4075 .macro          OpEBM0
4076                 @ A is 16bits
4077                 MOV             rscratch, reg_a, ROR #24 @  ll0000hh
4078                 ORR             rscratch, rscratch, reg_a, LSR #8@  ll0000hh + 00hhll00 -> llhhllhh
4079                 MOV             reg_a, rscratch, LSL #16@  llhhllhh -> llhh0000
4080                 MOVS            rscratch,rscratch,LSL #24 @ to set Z & N flags with AL
4081                 UPDATE_ZN
4082                 ADD2CYCLE
4083 .endm
4084
4085
4086 /**********************************************************************************************/
4087 /* RTI *************************************************************************************** */
4088 .macro          Op40X1M1
4089                 @ INDEX set, MEMORY set
4090                 BIC             rstatus,rstatus,#0xFF000000
4091                 PullBr
4092                 ORR             rstatus,rscratch,rstatus
4093                 PullWlow        rpc
4094                 TST             rstatus, #MASK_EMUL
4095                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4096                 BNE             2401f
4097                 PullBrLow
4098                 BIC             reg_p_bank,reg_p_bank,#0xFF
4099                 ORR             reg_p_bank,reg_p_bank,rscratch
4100 2401:
4101                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4102                 S9xSetPCBase
4103                 TST             rstatus, #MASK_INDEX
4104                 @ INDEX cleared & was set : 8->16
4105                 MOVEQ           reg_x,reg_x,LSR #8
4106                 MOVEQ           reg_y,reg_y,LSR #8
4107                 TST             rstatus, #MASK_MEM
4108                 @ MEMORY cleared & was set : 8->16
4109                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4110                 MOVEQ           reg_a,reg_a,LSR #8
4111                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4112                 ADD2CYCLE
4113                 S9xFixCycles
4114 .endm
4115 .macro          Op40X0M1
4116                 @ INDEX cleared, MEMORY set
4117                 BIC             rstatus,rstatus,#0xFF000000
4118                 PullBr
4119                 ORR             rstatus,rscratch,rstatus
4120                 PullWlow        rpc
4121                 TST             rstatus, #MASK_EMUL
4122                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4123                 BNE             2401f
4124                 PullBrLow
4125                 BIC             reg_p_bank,reg_p_bank,#0xFF
4126                 ORR             reg_p_bank,reg_p_bank,rscratch
4127 2401:
4128                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4129                 S9xSetPCBase
4130                 TST             rstatus, #MASK_INDEX
4131                 @ INDEX set & was cleared : 16->8
4132                 MOVNE           reg_x,reg_x,LSL #8
4133                 MOVNE           reg_y,reg_y,LSL #8
4134                 TST             rstatus, #MASK_MEM
4135                 @ MEMORY cleared & was set : 8->16
4136                 LDREQB          rscratch,[reg_cpu_var,#RAH_ofs]
4137                 MOVEQ           reg_a,reg_a,LSR #8
4138                 ORREQ           reg_a,reg_a,rscratch, LSL #24
4139                 ADD2CYCLE
4140                 S9xFixCycles
4141 .endm
4142 .macro          Op40X1M0
4143                 @ INDEX set, MEMORY cleared
4144                 BIC             rstatus,rstatus,#0xFF000000
4145                 PullBr
4146                 ORR             rstatus,rscratch,rstatus
4147                 PullWlow        rpc
4148                 TST             rstatus, #MASK_EMUL
4149                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4150                 BNE             2401f
4151                 PullBrLow
4152                 BIC             reg_p_bank,reg_p_bank,#0xFF
4153                 ORR             reg_p_bank,reg_p_bank,rscratch
4154 2401:
4155                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4156                 S9xSetPCBase
4157                 TST             rstatus, #MASK_INDEX
4158                 @ INDEX cleared & was set : 8->16
4159                 MOVEQ           reg_x,reg_x,LSR #8
4160                 MOVEQ           reg_y,reg_y,LSR #8
4161                 TST             rstatus, #MASK_MEM
4162                 @ MEMORY set & was cleared : 16->8
4163                 MOVNE           rscratch,reg_a,LSR #24
4164                 MOVNE           reg_a,reg_a,LSL #8
4165                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4166                 ADD2CYCLE
4167                 S9xFixCycles
4168 .endm
4169 .macro          Op40X0M0
4170                 @ INDEX cleared, MEMORY cleared
4171                 BIC             rstatus,rstatus,#0xFF000000
4172                 PullBr
4173                 ORR             rstatus,rscratch,rstatus
4174                 PullWlow        rpc
4175                 TST             rstatus, #MASK_EMUL
4176                 ORRNE           rstatus, rstatus, #(MASK_MEM|MASK_INDEX)
4177                 BNE             2401f
4178                 PullBrLow
4179                 BIC             reg_p_bank,reg_p_bank,#0xFF
4180                 ORR             reg_p_bank,reg_p_bank,rscratch
4181 2401:
4182                 ADD             rscratch, rpc, reg_p_bank, LSL #16
4183                 S9xSetPCBase
4184                 TST             rstatus, #MASK_INDEX
4185                 @ INDEX set & was cleared : 16->8
4186                 MOVNE           reg_x,reg_x,LSL #8
4187                 MOVNE           reg_y,reg_y,LSL #8
4188                 TST             rstatus, #MASK_MEM
4189                 @ MEMORY set & was cleared : 16->8
4190                 @ MEMORY set & was cleared : 16->8
4191                 MOVNE           rscratch,reg_a,LSR #24
4192                 MOVNE           reg_a,reg_a,LSL #8
4193                 STRNEB          rscratch,[reg_cpu_var,#RAH_ofs]
4194                 ADD2CYCLE
4195                 S9xFixCycles
4196 .endm
4197
4198
4199 /**********************************************************************************************/
4200 /* STP/WAI/DB ******************************************************************************** */
4201 @  WAI
4202 .macro          OpCB    /*WAI*/
4203         LDRB            rscratch,[reg_cpu_var,#IRQActive_ofs]
4204         MOVS            rscratch,rscratch
4205         @ (CPU.IRQActive)
4206         ADD2CYCLENE
4207         BNE             1234f
4208 /*
4209         CPU.WaitingForInterrupt = TRUE;
4210         CPU.PC--;
4211 */
4212         MOV             rscratch,#1
4213         SUB             rpc,rpc,#1
4214 /*
4215             CPU.Cycles = CPU.NextEvent;
4216 */
4217         STRB            rscratch,[reg_cpu_var,#WaitingForInterrupt_ofs]
4218         LDR             reg_cycles,[reg_cpu_var,#NextEvent_ofs]
4219 /*
4220         if (IAPU.APUExecuting)
4221             {
4222                 ICPU.CPUExecuting = FALSE;
4223                 do
4224                 {
4225                     APU_EXECUTE1 ();
4226                 } while (APU.Cycles < CPU.NextEvent);
4227                 ICPU.CPUExecuting = TRUE;
4228             }
4229 */
4230         LDRB            rscratch,[reg_cpu_var,#APUExecuting_ofs]
4231         MOVS            rscratch,rscratch
4232         BEQ             1234f
4233         asmAPU_EXECUTE2
4234
4235 1234:
4236 .endm
4237 .macro          OpDB    /*STP*/
4238                 SUB     rpc,rpc,#1
4239                 @ CPU.Flags |= DEBUG_MODE_FLAG;
4240 .endm
4241 .macro          Op42   /*Reserved Snes9X: SNESAdvance SpeedHack */
4242 @ Explanation: this is a reserved opcode turned into special "idle"/hlt opcode.
4243 @ This means we should do an hblank now.
4244 /*-
4245         CPU.Cycles = CPU.NextEvent;
4246 */      ldr reg_cycles, [reg_cpu_var,#NextEvent_ofs]
4247 @ Now execute the shadowed branch
4248 @ Equivalent to "asmRelative":
4249         ADD1MEM
4250         ldrb rscratch, [rpc], #1
4251         and rscratch2, rscratch, #0xf0  @branch type
4252         orr rscratch, rscratch, #0xf0   @branch dest (always negative, so sign ext)
4253         sxtb rscratch, rscratch
4254         add rscratch, rscratch, rpc
4255         sub rscratch, rscratch, regpcbase
4256         uxth rscratch, rscratch
4257 @ TODO: Do something with rscratch2 before BranchCheck clobbers it.
4258 @ Currently hardcoded to BEQ
4259         BranchCheck2
4260                 TST             rstatus, #MASK_ZERO
4261                 BEQ             1111f
4262                 ADD             rpc, rscratch, regpcbase @  rpc = OpAddress +PCBase
4263                 ADD1CYCLE
4264                 CPUShutdown
4265 .endm
4266
4267 /**********************************************************************************************/
4268 /* AND ******************************************************************************** */
4269 .macro          Op29M1
4270                 LDRB    rscratch    , [rpc], #1
4271                 ANDS    reg_a    , reg_a,       rscratch, LSL #24
4272                 UPDATE_ZN
4273                 ADD1MEM
4274 .endm
4275 .macro          Op29M0
4276                 LDRB    rscratch2  , [rpc,#1]
4277                 LDRB    rscratch   , [rpc], #2
4278                 ORR     rscratch, rscratch, rscratch2, LSL #8
4279                 ANDS    reg_a    , reg_a,       rscratch, LSL #16
4280                 UPDATE_ZN
4281                 ADD2MEM
4282 .endm
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298 /**********************************************************************************************/
4299 /* EOR ******************************************************************************** */
4300 .macro          Op49M0
4301                 LDRB    rscratch2 , [rpc, #1]
4302                 LDRB    rscratch , [rpc], #2
4303                 ORR     rscratch, rscratch, rscratch2,LSL #8
4304                 EORS    reg_a, reg_a, rscratch,LSL #16
4305                 UPDATE_ZN
4306                 ADD2MEM
4307 .endm
4308
4309
4310 .macro          Op49M1
4311                 LDRB    rscratch , [rpc], #1
4312                 EORS    reg_a, reg_a, rscratch,LSL #24
4313                 UPDATE_ZN
4314                 ADD1MEM
4315 .endm
4316
4317
4318 /**********************************************************************************************/
4319 /* STA *************************************************************************************** */
4320 .macro          Op81M1
4321                 STA8
4322                 @ TST           rstatus, #MASK_INDEX
4323                 @ ADD1CYCLENE
4324 .endm
4325 .macro          Op81M0
4326                 STA16
4327                 @ TST rstatus, #MASK_INDEX
4328                 @ ADD1CYCLENE
4329 .endm
4330
4331
4332 /**********************************************************************************************/
4333 /* BIT *************************************************************************************** */
4334 .macro          Op89M1
4335                 LDRB    rscratch , [rpc], #1
4336                 TST     reg_a, rscratch, LSL #24
4337                 UPDATE_Z
4338                 ADD1MEM
4339 .endm
4340 .macro          Op89M0
4341                 LDRB    rscratch2 , [rpc, #1]
4342                 LDRB    rscratch , [rpc], #2
4343                 ORR     rscratch, rscratch, rscratch2, LSL #8
4344                 TST     reg_a, rscratch, LSL #16
4345                 UPDATE_Z
4346                 ADD2MEM
4347 .endm
4348
4349
4350
4351
4352
4353
4354 /**********************************************************************************************/
4355 /* LDY *************************************************************************************** */
4356 .macro          OpA0X1
4357                 LDRB    rscratch , [rpc], #1
4358                 MOVS    reg_y, rscratch, LSL #24
4359                 UPDATE_ZN
4360                 ADD1MEM
4361 .endm
4362 .macro          OpA0X0
4363                 LDRB    rscratch2 , [rpc, #1]
4364                 LDRB    rscratch , [rpc], #2
4365                 ORR     rscratch, rscratch, rscratch2, LSL #8
4366                 MOVS    reg_y, rscratch, LSL #16
4367                 UPDATE_ZN
4368                 ADD2MEM
4369 .endm
4370
4371 /**********************************************************************************************/
4372 /* LDX *************************************************************************************** */
4373 .macro          OpA2X1
4374                 LDRB    rscratch , [rpc], #1
4375                 MOVS    reg_x, rscratch, LSL #24
4376                 UPDATE_ZN
4377                 ADD1MEM
4378 .endm
4379 .macro          OpA2X0
4380                 LDRB    rscratch2 , [rpc, #1]
4381                 LDRB    rscratch , [rpc], #2
4382                 ORR     rscratch, rscratch, rscratch2, LSL #8
4383                 MOVS    reg_x, rscratch, LSL #16
4384                 UPDATE_ZN
4385                 ADD2MEM
4386 .endm
4387
4388 /**********************************************************************************************/
4389 /* LDA *************************************************************************************** */
4390 .macro          OpA9M1
4391                 LDRB    rscratch , [rpc], #1
4392                 MOVS    reg_a, rscratch, LSL #24
4393                 UPDATE_ZN
4394                 ADD1MEM
4395 .endm
4396 .macro          OpA9M0
4397                 LDRB    rscratch2 , [rpc, #1]
4398                 LDRB    rscratch , [rpc], #2
4399                 ORR     rscratch, rscratch, rscratch2, LSL #8
4400                 MOVS    reg_a, rscratch, LSL #16
4401                 UPDATE_ZN
4402                 ADD2MEM
4403 .endm
4404
4405 /**********************************************************************************************/
4406 /* CMY *************************************************************************************** */
4407 .macro          OpC0X1
4408                 LDRB    rscratch    , [rpc], #1
4409                 SUBS    rscratch2   , reg_y , rscratch, LSL #24
4410                 BICCC   rstatus, rstatus, #MASK_CARRY
4411                 ORRCS   rstatus, rstatus, #MASK_CARRY
4412                 UPDATE_ZN
4413                 ADD1MEM
4414 .endm
4415 .macro          OpC0X0
4416                 LDRB    rscratch2   , [rpc, #1]
4417                 LDRB    rscratch   , [rpc], #2
4418                 ORR     rscratch, rscratch, rscratch2, LSL #8
4419                 SUBS    rscratch2   , reg_y, rscratch, LSL #16
4420                 BICCC   rstatus, rstatus, #MASK_CARRY
4421                 ORRCS   rstatus, rstatus, #MASK_CARRY
4422                 UPDATE_ZN
4423                 ADD2MEM
4424 .endm
4425
4426
4427
4428
4429
4430 /**********************************************************************************************/
4431 /* CMP *************************************************************************************** */
4432 .macro          OpC9M1
4433                 LDRB    rscratch    , [rpc], #1
4434                 SUBS    rscratch2   , reg_a , rscratch, LSL #24
4435                 BICCC   rstatus, rstatus, #MASK_CARRY
4436                 ORRCS   rstatus, rstatus, #MASK_CARRY
4437                 UPDATE_ZN
4438                 ADD1MEM
4439 .endm
4440 .macro          OpC9M0
4441                 LDRB    rscratch2   , [rpc,#1]
4442                 LDRB    rscratch   , [rpc], #2
4443                 ORR     rscratch, rscratch, rscratch2, LSL #8
4444                 SUBS    rscratch2   , reg_a, rscratch, LSL #16
4445                 BICCC   rstatus, rstatus, #MASK_CARRY
4446                 ORRCS   rstatus, rstatus, #MASK_CARRY
4447                 UPDATE_ZN
4448                 ADD2MEM
4449 .endm
4450
4451 /**********************************************************************************************/
4452 /* CMX *************************************************************************************** */
4453 .macro          OpE0X1
4454                 LDRB    rscratch    , [rpc], #1
4455                 SUBS    rscratch2   , reg_x , rscratch, LSL #24
4456                 BICCC   rstatus, rstatus, #MASK_CARRY
4457                 ORRCS   rstatus, rstatus, #MASK_CARRY
4458                 UPDATE_ZN
4459                 ADD1MEM
4460 .endm
4461 .macro          OpE0X0
4462                 LDRB    rscratch2   , [rpc,#1]
4463                 LDRB    rscratch   , [rpc], #2
4464                 ORR     rscratch, rscratch, rscratch2, LSL #8
4465                 SUBS    rscratch2   , reg_x, rscratch, LSL #16
4466                 BICCC   rstatus, rstatus, #MASK_CARRY
4467                 ORRCS   rstatus, rstatus, #MASK_CARRY
4468                 UPDATE_ZN
4469                 ADD2MEM
4470 .endm
4471
4472
4473 /****************************************************************
4474         GLOBAL
4475 ****************************************************************/
4476 .global asmMainLoop
4477 .type   asmMainLoop, function
4478
4479 @ void asmMainLoop(asm_cpu_var_t *asmcpuPtr);
4480 asmMainLoop:
4481         @ save registers
4482         STMFD           R13!,{R4-R11, LR}
4483         @ init pointer to CPUvar structure
4484         MOV             reg_cpu_var,R0
4485         @ init registers
4486         LOAD_REGS
4487         @ get cpu mode from flag and init jump table
4488         S9xFixCycles
4489
4490 mainLoop:
4491         @ APU Execute
4492         asmAPU_EXECUTE
4493
4494         @ Test Flags
4495         LDR             rscratch,[reg_cpu_var,#Flags_ofs]
4496         MOVS            rscratch,rscratch
4497         BNE             CPUFlags_set    @ If flags => check for irq/nmi/scan_keys...
4498
4499         EXEC_OP                                         @ Execute next opcode
4500
4501 CPUFlags_set:   @ Check flags (!=0)
4502                 TST     rscratch,#NMI_FLAG              @ Check NMI
4503                 BEQ     CPUFlagsNMI_FLAG_cleared
4504                 LDR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4505                 SUBS    rscratch2,rscratch2,#1
4506                 STR     rscratch2,[reg_cpu_var,#NMICycleCount_ofs]
4507                 BNE     CPUFlagsNMI_FLAG_cleared
4508                 BIC     rscratch,rscratch,#NMI_FLAG
4509                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4510                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4511                 MOVS    rscratch2,rscratch2
4512                 BEQ     NotCPUaitingForInterruptNMI
4513                 MOV     rscratch2,#0
4514                 ADD     rpc,rpc,#1
4515                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4516 NotCPUaitingForInterruptNMI:
4517                 S9xOpcode_NMI
4518                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4519 CPUFlagsNMI_FLAG_cleared:
4520                 TST     rscratch,#IRQ_PENDING_FLAG   @ Check IRQ_PENDING_FLAG
4521                 BEQ     CPUFlagsIRQ_PENDING_FLAG_cleared
4522                 LDR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4523                 MOVS    rscratch2,rscratch2
4524                 BNE     CPUIRQCycleCount_NotZero
4525                 LDRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4526                 MOVS    rscratch2,rscratch2
4527                 BEQ     NotCPUaitingForInterruptIRQ
4528                 MOV     rscratch2,#0
4529                 ADD     rpc,rpc,#1
4530                 STRB    rscratch2,[reg_cpu_var,#WaitingForInterrupt_ofs]
4531 NotCPUaitingForInterruptIRQ:
4532                 LDRB    rscratch2,[reg_cpu_var,#IRQActive_ofs]
4533                 MOVS    rscratch2,rscratch2
4534                 BEQ     CPUIRQActive_cleared
4535                 TST     rstatus,#MASK_IRQ
4536                 BNE     CPUFlagsIRQ_PENDING_FLAG_cleared
4537                 S9xOpcode_IRQ
4538                 LDR     rscratch,[reg_cpu_var,#Flags_ofs]
4539                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4540 CPUIRQActive_cleared:
4541                 BIC     rscratch,rscratch,#IRQ_PENDING_FLAG
4542                 STR     rscratch,[reg_cpu_var,#Flags_ofs]
4543                 B       CPUFlagsIRQ_PENDING_FLAG_cleared
4544 CPUIRQCycleCount_NotZero:
4545                 SUB     rscratch2,rscratch2,#1
4546                 STR     rscratch2,[reg_cpu_var,#IRQCycleCount_ofs]
4547 CPUFlagsIRQ_PENDING_FLAG_cleared:
4548
4549                 TST     rscratch,#SCAN_KEYS_FLAG   @ Check SCAN_KEYS_FLAG
4550                 BNE     endmainLoop
4551
4552         EXEC_OP @ Execute next opcode
4553
4554 endmainLoop:
4555     /*Registers.PC = CPU.PC - CPU.PCBase;
4556     S9xPackStatus ();
4557     APURegisters.PC = IAPU.PC - IAPU.RAM;
4558     S9xAPUPackStatus ();
4559
4560     if (CPU.Flags & SCAN_KEYS_FLAG)
4561     {
4562             S9xSyncSpeed ();
4563         CPU.Flags &= ~SCAN_KEYS_FLAG;
4564     }   */
4565 /********end*/
4566         SAVE_REGS
4567         LDMFD           R13!,{R4-R11, LR}
4568         BX LR
4569 .pool
4570 .size asmMainLoop, asmMainLoop-.
4571
4572 @ void test_opcode(struct asm_cpu_var *asm_var);
4573 test_opcode:
4574         @ save registers
4575         STMFD           R13!,{R4-R11,LR}
4576         @ init pointer to CPUvar structure
4577         MOV             reg_cpu_var,R0
4578         @ init registers
4579         LOAD_REGS
4580         @ get cpu mode from flag and init jump table
4581         S9xFixCycles
4582
4583         EXEC_OP
4584 .pool
4585
4586 /*****************************************************************
4587        ASM CODE
4588 *****************************************************************/
4589
4590
4591 jumptable1:             .long   Op00mod1
4592                         .long   Op01M1mod1
4593                         .long   Op02mod1
4594                         .long   Op03M1mod1
4595                         .long   Op04M1mod1
4596                         .long   Op05M1mod1
4597                         .long   Op06M1mod1
4598                         .long   Op07M1mod1
4599                         .long   Op08mod1
4600                         .long   Op09M1mod1
4601                         .long   Op0AM1mod1
4602                         .long   Op0Bmod1
4603                         .long   Op0CM1mod1
4604                         .long   Op0DM1mod1
4605                         .long   Op0EM1mod1
4606                         .long   Op0FM1mod1
4607                         .long   Op10mod1
4608                         .long   Op11M1mod1
4609                         .long   Op12M1mod1
4610                         .long   Op13M1mod1
4611                         .long   Op14M1mod1
4612                         .long   Op15M1mod1
4613                         .long   Op16M1mod1
4614                         .long   Op17M1mod1
4615                         .long   Op18mod1
4616                         .long   Op19M1mod1
4617                         .long   Op1AM1mod1
4618                         .long   Op1Bmod1
4619                         .long   Op1CM1mod1
4620                         .long   Op1DM1mod1
4621                         .long   Op1EM1mod1
4622                         .long   Op1FM1mod1
4623                         .long   Op20mod1
4624                         .long   Op21M1mod1
4625                         .long   Op22mod1
4626                         .long   Op23M1mod1
4627                         .long   Op24M1mod1
4628                         .long   Op25M1mod1
4629                         .long   Op26M1mod1
4630                         .long   Op27M1mod1
4631                         .long   Op28mod1
4632                         .long   Op29M1mod1
4633                         .long   Op2AM1mod1
4634                         .long   Op2Bmod1
4635                         .long   Op2CM1mod1
4636                         .long   Op2DM1mod1
4637                         .long   Op2EM1mod1
4638                         .long   Op2FM1mod1
4639                         .long   Op30mod1
4640                         .long   Op31M1mod1
4641                         .long   Op32M1mod1
4642                         .long   Op33M1mod1
4643                         .long   Op34M1mod1
4644                         .long   Op35M1mod1
4645                         .long   Op36M1mod1
4646                         .long   Op37M1mod1
4647                         .long   Op38mod1
4648                         .long   Op39M1mod1
4649                         .long   Op3AM1mod1
4650                         .long   Op3Bmod1
4651                         .long   Op3CM1mod1
4652                         .long   Op3DM1mod1
4653                         .long   Op3EM1mod1
4654                         .long   Op3FM1mod1
4655                         .long   Op40mod1
4656                         .long   Op41M1mod1
4657                         .long   Op42mod1
4658                         .long   Op43M1mod1
4659                         .long   Op44X1mod1
4660                         .long   Op45M1mod1
4661                         .long   Op46M1mod1
4662                         .long   Op47M1mod1
4663                         .long   Op48M1mod1
4664                         .long   Op49M1mod1
4665                         .long   Op4AM1mod1
4666                         .long   Op4Bmod1
4667                         .long   Op4Cmod1
4668                         .long   Op4DM1mod1
4669                         .long   Op4EM1mod1
4670                         .long   Op4FM1mod1
4671                         .long   Op50mod1
4672                         .long   Op51M1mod1
4673                         .long   Op52M1mod1
4674                         .long   Op53M1mod1
4675                         .long   Op54X1mod1
4676                         .long   Op55M1mod1
4677                         .long   Op56M1mod1
4678                         .long   Op57M1mod1
4679                         .long   Op58mod1
4680                         .long   Op59M1mod1
4681                         .long   Op5AX1mod1
4682                         .long   Op5Bmod1
4683                         .long   Op5Cmod1
4684                         .long   Op5DM1mod1
4685                         .long   Op5EM1mod1
4686                         .long   Op5FM1mod1
4687                         .long   Op60mod1
4688                         .long   Op61M1mod1
4689                         .long   Op62mod1
4690                         .long   Op63M1mod1
4691                         .long   Op64M1mod1
4692                         .long   Op65M1mod1
4693                         .long   Op66M1mod1
4694                         .long   Op67M1mod1
4695                         .long   Op68M1mod1
4696                         .long   Op69M1mod1
4697                         .long   Op6AM1mod1
4698                         .long   Op6Bmod1
4699                         .long   Op6Cmod1
4700                         .long   Op6DM1mod1
4701                         .long   Op6EM1mod1
4702                         .long   Op6FM1mod1
4703                         .long   Op70mod1
4704                         .long   Op71M1mod1
4705                         .long   Op72M1mod1
4706                         .long   Op73M1mod1
4707                         .long   Op74M1mod1
4708                         .long   Op75M1mod1
4709                         .long   Op76M1mod1
4710                         .long   Op77M1mod1
4711                         .long   Op78mod1
4712                         .long   Op79M1mod1
4713                         .long   Op7AX1mod1
4714                         .long   Op7Bmod1
4715                         .long   Op7Cmod1
4716                         .long   Op7DM1mod1
4717                         .long   Op7EM1mod1
4718                         .long   Op7FM1mod1
4719                         .long   Op80mod1
4720                         .long   Op81M1mod1
4721                         .long   Op82mod1
4722                         .long   Op83M1mod1
4723                         .long   Op84X1mod1
4724                         .long   Op85M1mod1
4725                         .long   Op86X1mod1
4726                         .long   Op87M1mod1
4727                         .long   Op88X1mod1
4728                         .long   Op89M1mod1
4729                         .long   Op8AM1mod1
4730                         .long   Op8Bmod1
4731                         .long   Op8CX1mod1
4732                         .long   Op8DM1mod1
4733                         .long   Op8EX1mod1
4734                         .long   Op8FM1mod1
4735                         .long   Op90mod1
4736                         .long   Op91M1mod1
4737                         .long   Op92M1mod1
4738                         .long   Op93M1mod1
4739                         .long   Op94X1mod1
4740                         .long   Op95M1mod1
4741                         .long   Op96X1mod1
4742                         .long   Op97M1mod1
4743                         .long   Op98M1mod1
4744                         .long   Op99M1mod1
4745                         .long   Op9Amod1
4746                         .long   Op9BX1mod1
4747                         .long   Op9CM1mod1
4748                         .long   Op9DM1mod1
4749                         .long   Op9EM1mod1
4750                         .long   Op9FM1mod1
4751                         .long   OpA0X1mod1
4752                         .long   OpA1M1mod1
4753                         .long   OpA2X1mod1
4754                         .long   OpA3M1mod1
4755                         .long   OpA4X1mod1
4756                         .long   OpA5M1mod1
4757                         .long   OpA6X1mod1
4758                         .long   OpA7M1mod1
4759                         .long   OpA8X1mod1
4760                         .long   OpA9M1mod1
4761                         .long   OpAAX1mod1
4762                         .long   OpABmod1
4763                         .long   OpACX1mod1
4764                         .long   OpADM1mod1
4765                         .long   OpAEX1mod1
4766                         .long   OpAFM1mod1
4767                         .long   OpB0mod1
4768                         .long   OpB1M1mod1
4769                         .long   OpB2M1mod1
4770                         .long   OpB3M1mod1
4771                         .long   OpB4X1mod1
4772                         .long   OpB5M1mod1
4773                         .long   OpB6X1mod1
4774                         .long   OpB7M1mod1
4775                         .long   OpB8mod1
4776                         .long   OpB9M1mod1
4777                         .long   OpBAX1mod1
4778                         .long   OpBBX1mod1
4779                         .long   OpBCX1mod1
4780                         .long   OpBDM1mod1
4781                         .long   OpBEX1mod1
4782                         .long   OpBFM1mod1
4783                         .long   OpC0X1mod1
4784                         .long   OpC1M1mod1
4785                         .long   OpC2mod1
4786                         .long   OpC3M1mod1
4787                         .long   OpC4X1mod1
4788                         .long   OpC5M1mod1
4789                         .long   OpC6M1mod1
4790                         .long   OpC7M1mod1
4791                         .long   OpC8X1mod1
4792                         .long   OpC9M1mod1
4793                         .long   OpCAX1mod1
4794                         .long   OpCBmod1
4795                         .long   OpCCX1mod1
4796                         .long   OpCDM1mod1
4797                         .long   OpCEM1mod1
4798                         .long   OpCFM1mod1
4799                         .long   OpD0mod1
4800                         .long   OpD1M1mod1
4801                         .long   OpD2M1mod1
4802                         .long   OpD3M1mod1
4803                         .long   OpD4mod1
4804                         .long   OpD5M1mod1
4805                         .long   OpD6M1mod1
4806                         .long   OpD7M1mod1
4807                         .long   OpD8mod1
4808                         .long   OpD9M1mod1
4809                         .long   OpDAX1mod1
4810                         .long   OpDBmod1
4811                         .long   OpDCmod1
4812                         .long   OpDDM1mod1
4813                         .long   OpDEM1mod1
4814                         .long   OpDFM1mod1
4815                         .long   OpE0X1mod1
4816                         .long   OpE1M1mod1
4817                         .long   OpE2mod1
4818                         .long   OpE3M1mod1
4819                         .long   OpE4X1mod1
4820                         .long   OpE5M1mod1
4821                         .long   OpE6M1mod1
4822                         .long   OpE7M1mod1
4823                         .long   OpE8X1mod1
4824                         .long   OpE9M1mod1
4825                         .long   OpEAmod1
4826                         .long   OpEBmod1
4827                         .long   OpECX1mod1
4828                         .long   OpEDM1mod1
4829                         .long   OpEEM1mod1
4830                         .long   OpEFM1mod1
4831                         .long   OpF0mod1
4832                         .long   OpF1M1mod1
4833                         .long   OpF2M1mod1
4834                         .long   OpF3M1mod1
4835                         .long   OpF4mod1
4836                         .long   OpF5M1mod1
4837                         .long   OpF6M1mod1
4838                         .long   OpF7M1mod1
4839                         .long   OpF8mod1
4840                         .long   OpF9M1mod1
4841                         .long   OpFAX1mod1
4842                         .long   OpFBmod1
4843                         .long   OpFCmod1
4844                         .long   OpFDM1mod1
4845                         .long   OpFEM1mod1
4846                         .long   OpFFM1mod1
4847
4848 Op00mod1:
4849 lbl00mod1:      Op00
4850                         NEXTOPCODE
4851 Op01M1mod1:
4852 lbl01mod1a:     DirectIndexedIndirect1
4853 lbl01mod1b:     ORA8
4854                         NEXTOPCODE
4855 Op02mod1:
4856 lbl02mod1:      Op02
4857                         NEXTOPCODE
4858 Op03M1mod1:
4859 lbl03mod1a:     StackasmRelative
4860 lbl03mod1b:     ORA8
4861                         NEXTOPCODE
4862 Op04M1mod1:
4863 lbl04mod1a:     Direct
4864 lbl04mod1b:     TSB8
4865                         NEXTOPCODE
4866 Op05M1mod1:
4867 lbl05mod1a:     Direct
4868 lbl05mod1b:     ORA8
4869                         NEXTOPCODE
4870 Op06M1mod1:
4871 lbl06mod1a:     Direct
4872 lbl06mod1b:     ASL8
4873                         NEXTOPCODE
4874 Op07M1mod1:
4875 lbl07mod1a:     DirectIndirectLong
4876 lbl07mod1b:     ORA8
4877                         NEXTOPCODE
4878 Op08mod1:
4879 lbl08mod1:      Op08
4880                         NEXTOPCODE
4881 Op09M1mod1:
4882 lbl09mod1:      Op09M1
4883                         NEXTOPCODE
4884 Op0AM1mod1:
4885 lbl0Amod1a:     A_ASL8
4886                         NEXTOPCODE
4887 Op0Bmod1:
4888 lbl0Bmod1:      Op0B
4889                         NEXTOPCODE
4890 Op0CM1mod1:
4891 lbl0Cmod1a:     Absolute
4892 lbl0Cmod1b:     TSB8
4893                         NEXTOPCODE
4894 Op0DM1mod1:
4895 lbl0Dmod1a:     Absolute
4896 lbl0Dmod1b:     ORA8
4897                         NEXTOPCODE
4898 Op0EM1mod1:
4899 lbl0Emod1a:     Absolute
4900 lbl0Emod1b:     ASL8
4901                         NEXTOPCODE
4902 Op0FM1mod1:
4903 lbl0Fmod1a:     AbsoluteLong
4904 lbl0Fmod1b:     ORA8
4905                         NEXTOPCODE
4906 Op10mod1:
4907 lbl10mod1:      Op10
4908                         NEXTOPCODE
4909 Op11M1mod1:
4910 lbl11mod1a:     DirectIndirectIndexed1
4911 lbl11mod1b:     ORA8
4912                         NEXTOPCODE
4913 Op12M1mod1:
4914 lbl12mod1a:     DirectIndirect
4915 lbl12mod1b:     ORA8
4916                         NEXTOPCODE
4917 Op13M1mod1:
4918 lbl13mod1a:     StackasmRelativeIndirectIndexed1
4919 lbl13mod1b:     ORA8
4920                         NEXTOPCODE
4921 Op14M1mod1:
4922 lbl14mod1a:     Direct
4923 lbl14mod1b:     TRB8
4924                         NEXTOPCODE
4925 Op15M1mod1:
4926 lbl15mod1a:     DirectIndexedX1
4927 lbl15mod1b:     ORA8
4928                         NEXTOPCODE
4929 Op16M1mod1:
4930 lbl16mod1a:     DirectIndexedX1
4931 lbl16mod1b:     ASL8
4932                         NEXTOPCODE
4933 Op17M1mod1:
4934 lbl17mod1a:     DirectIndirectIndexedLong1
4935 lbl17mod1b:     ORA8
4936                         NEXTOPCODE
4937 Op18mod1:
4938 lbl18mod1:      Op18
4939                         NEXTOPCODE
4940 Op19M1mod1:
4941 lbl19mod1a:     AbsoluteIndexedY1
4942 lbl19mod1b:     ORA8
4943                         NEXTOPCODE
4944 Op1AM1mod1:
4945 lbl1Amod1a:     A_INC8
4946                         NEXTOPCODE
4947 Op1Bmod1:
4948 lbl1Bmod1:      Op1BM1
4949                         NEXTOPCODE
4950 Op1CM1mod1:
4951 lbl1Cmod1a:     Absolute
4952 lbl1Cmod1b:     TRB8
4953                         NEXTOPCODE
4954 Op1DM1mod1:
4955 lbl1Dmod1a:     AbsoluteIndexedX1
4956 lbl1Dmod1b:     ORA8
4957                         NEXTOPCODE
4958 Op1EM1mod1:
4959 lbl1Emod1a:     AbsoluteIndexedX1
4960 lbl1Emod1b:     ASL8
4961                         NEXTOPCODE
4962 Op1FM1mod1:
4963 lbl1Fmod1a:     AbsoluteLongIndexedX1
4964 lbl1Fmod1b:     ORA8
4965                         NEXTOPCODE
4966 Op20mod1:
4967 lbl20mod1:      Op20
4968                         NEXTOPCODE
4969 Op21M1mod1:
4970 lbl21mod1a:     DirectIndexedIndirect1
4971 lbl21mod1b:     AND8
4972                         NEXTOPCODE
4973 Op22mod1:
4974 lbl22mod1:      Op22
4975                         NEXTOPCODE
4976 Op23M1mod1:
4977 lbl23mod1a:     StackasmRelative
4978 lbl23mod1b:     AND8
4979                         NEXTOPCODE
4980 Op24M1mod1:
4981 lbl24mod1a:     Direct
4982 lbl24mod1b:     BIT8
4983                         NEXTOPCODE
4984 Op25M1mod1:
4985 lbl25mod1a:     Direct
4986 lbl25mod1b:     AND8
4987                         NEXTOPCODE
4988 Op26M1mod1:
4989 lbl26mod1a:     Direct
4990 lbl26mod1b:     ROL8
4991                         NEXTOPCODE
4992 Op27M1mod1:
4993 lbl27mod1a:     DirectIndirectLong
4994 lbl27mod1b:     AND8
4995                         NEXTOPCODE
4996 Op28mod1:
4997 lbl28mod1:      Op28X1M1
4998                         NEXTOPCODE
4999 .pool
5000 Op29M1mod1:
5001 lbl29mod1:      Op29M1
5002                         NEXTOPCODE
5003 Op2AM1mod1:
5004 lbl2Amod1a:     A_ROL8
5005                         NEXTOPCODE
5006 Op2Bmod1:
5007 lbl2Bmod1:      Op2B
5008                         NEXTOPCODE
5009 Op2CM1mod1:
5010 lbl2Cmod1a:     Absolute
5011 lbl2Cmod1b:     BIT8
5012                         NEXTOPCODE
5013 Op2DM1mod1:
5014 lbl2Dmod1a:     Absolute
5015 lbl2Dmod1b:     AND8
5016                         NEXTOPCODE
5017 Op2EM1mod1:
5018 lbl2Emod1a:     Absolute
5019 lbl2Emod1b:     ROL8
5020                         NEXTOPCODE
5021 Op2FM1mod1:
5022 lbl2Fmod1a:     AbsoluteLong
5023 lbl2Fmod1b:     AND8
5024                         NEXTOPCODE
5025 Op30mod1:
5026 lbl30mod1:      Op30
5027                         NEXTOPCODE
5028 Op31M1mod1:
5029 lbl31mod1a:     DirectIndirectIndexed1
5030 lbl31mod1b:     AND8
5031                         NEXTOPCODE
5032 Op32M1mod1:
5033 lbl32mod1a:     DirectIndirect
5034 lbl32mod1b:     AND8
5035                         NEXTOPCODE
5036 Op33M1mod1:
5037 lbl33mod1a:     StackasmRelativeIndirectIndexed1
5038 lbl33mod1b:     AND8
5039                         NEXTOPCODE
5040 Op34M1mod1:
5041 lbl34mod1a:     DirectIndexedX1
5042 lbl34mod1b:     BIT8
5043                         NEXTOPCODE
5044 Op35M1mod1:
5045 lbl35mod1a:     DirectIndexedX1
5046 lbl35mod1b:     AND8
5047                         NEXTOPCODE
5048 Op36M1mod1:
5049 lbl36mod1a:     DirectIndexedX1
5050 lbl36mod1b:     ROL8
5051                         NEXTOPCODE
5052 Op37M1mod1:
5053 lbl37mod1a:     DirectIndirectIndexedLong1
5054 lbl37mod1b:     AND8
5055                         NEXTOPCODE
5056 Op38mod1:
5057 lbl38mod1:      Op38
5058                         NEXTOPCODE
5059 Op39M1mod1:
5060 lbl39mod1a:     AbsoluteIndexedY1
5061 lbl39mod1b:     AND8
5062                         NEXTOPCODE
5063 Op3AM1mod1:
5064 lbl3Amod1a:     A_DEC8
5065                         NEXTOPCODE
5066 Op3Bmod1:
5067 lbl3Bmod1:      Op3BM1
5068                         NEXTOPCODE
5069 Op3CM1mod1:
5070 lbl3Cmod1a:     AbsoluteIndexedX1
5071 lbl3Cmod1b:     BIT8
5072                         NEXTOPCODE
5073 Op3DM1mod1:
5074 lbl3Dmod1a:     AbsoluteIndexedX1
5075 lbl3Dmod1b:     AND8
5076                         NEXTOPCODE
5077 Op3EM1mod1:
5078 lbl3Emod1a:     AbsoluteIndexedX1
5079 lbl3Emod1b:     ROL8
5080                         NEXTOPCODE
5081 Op3FM1mod1:
5082 lbl3Fmod1a:     AbsoluteLongIndexedX1
5083 lbl3Fmod1b:     AND8
5084                         NEXTOPCODE
5085 Op40mod1:
5086 lbl40mod1:      Op40X1M1
5087                         NEXTOPCODE
5088 .pool
5089 Op41M1mod1:
5090 lbl41mod1a:     DirectIndexedIndirect1
5091 lbl41mod1b:     EOR8
5092                         NEXTOPCODE
5093 Op42mod1:
5094 lbl42mod1:      Op42
5095                         NEXTOPCODE
5096 Op43M1mod1:
5097 lbl43mod1a:     StackasmRelative
5098 lbl43mod1b:     EOR8
5099                         NEXTOPCODE
5100 Op44X1mod1:
5101 lbl44mod1:      Op44X1M1
5102                         NEXTOPCODE
5103 Op45M1mod1:
5104 lbl45mod1a:     Direct
5105 lbl45mod1b:     EOR8
5106                         NEXTOPCODE
5107 Op46M1mod1:
5108 lbl46mod1a:     Direct
5109 lbl46mod1b:     LSR8
5110                         NEXTOPCODE
5111 Op47M1mod1:
5112 lbl47mod1a:     DirectIndirectLong
5113 lbl47mod1b:     EOR8
5114                         NEXTOPCODE
5115 Op48M1mod1:
5116 lbl48mod1:      Op48M1
5117                         NEXTOPCODE
5118 Op49M1mod1:
5119 lbl49mod1:      Op49M1
5120                         NEXTOPCODE
5121 Op4AM1mod1:
5122 lbl4Amod1a:     A_LSR8
5123                         NEXTOPCODE
5124 Op4Bmod1:
5125 lbl4Bmod1:      Op4B
5126                         NEXTOPCODE
5127 Op4Cmod1:
5128 lbl4Cmod1:      Op4C
5129                         NEXTOPCODE
5130 Op4DM1mod1:
5131 lbl4Dmod1a:     Absolute
5132 lbl4Dmod1b:     EOR8
5133                         NEXTOPCODE
5134 Op4EM1mod1:
5135 lbl4Emod1a:     Absolute
5136 lbl4Emod1b:     LSR8
5137                         NEXTOPCODE
5138 Op4FM1mod1:
5139 lbl4Fmod1a:     AbsoluteLong
5140 lbl4Fmod1b:     EOR8
5141                         NEXTOPCODE
5142 Op50mod1:
5143 lbl50mod1:      Op50
5144                         NEXTOPCODE
5145 Op51M1mod1:
5146 lbl51mod1a:     DirectIndirectIndexed1
5147 lbl51mod1b:     EOR8
5148                         NEXTOPCODE
5149 Op52M1mod1:
5150 lbl52mod1a:     DirectIndirect
5151 lbl52mod1b:     EOR8
5152                         NEXTOPCODE
5153 Op53M1mod1:
5154 lbl53mod1a:     StackasmRelativeIndirectIndexed1
5155 lbl53mod1b:     EOR8
5156                         NEXTOPCODE
5157 Op54X1mod1:
5158 lbl54mod1:      Op54X1M1
5159                         NEXTOPCODE
5160 Op55M1mod1:
5161 lbl55mod1a:     DirectIndexedX1
5162 lbl55mod1b:     EOR8
5163                         NEXTOPCODE
5164 Op56M1mod1:
5165 lbl56mod1a:     DirectIndexedX1
5166 lbl56mod1b:     LSR8
5167                         NEXTOPCODE
5168 Op57M1mod1:
5169 lbl57mod1a:     DirectIndirectIndexedLong1
5170 lbl57mod1b:     EOR8
5171                         NEXTOPCODE
5172 Op58mod1:
5173 lbl58mod1:      Op58
5174                         NEXTOPCODE
5175 Op59M1mod1:
5176 lbl59mod1a:     AbsoluteIndexedY1
5177 lbl59mod1b:     EOR8
5178                         NEXTOPCODE
5179 Op5AX1mod1:
5180 lbl5Amod1:      Op5AX1
5181                         NEXTOPCODE
5182 Op5Bmod1:
5183 lbl5Bmod1:      Op5BM1
5184                         NEXTOPCODE
5185 Op5Cmod1:
5186 lbl5Cmod1:      Op5C
5187                         NEXTOPCODE
5188 Op5DM1mod1:
5189 lbl5Dmod1a:     AbsoluteIndexedX1
5190 lbl5Dmod1b:     EOR8
5191                         NEXTOPCODE
5192 Op5EM1mod1:
5193 lbl5Emod1a:     AbsoluteIndexedX1
5194 lbl5Emod1b:     LSR8
5195                         NEXTOPCODE
5196 Op5FM1mod1:
5197 lbl5Fmod1a:     AbsoluteLongIndexedX1
5198 lbl5Fmod1b:     EOR8
5199                         NEXTOPCODE
5200 Op60mod1:
5201 lbl60mod1:      Op60
5202                         NEXTOPCODE
5203 Op61M1mod1:
5204 lbl61mod1a:     DirectIndexedIndirect1
5205 lbl61mod1b:     ADC8
5206                         NEXTOPCODE
5207 Op62mod1:
5208 lbl62mod1:      Op62
5209                         NEXTOPCODE
5210 Op63M1mod1:
5211 lbl63mod1a:     StackasmRelative
5212 lbl63mod1b:     ADC8
5213                         NEXTOPCODE
5214 Op64M1mod1:
5215 lbl64mod1a:     Direct
5216 lbl64mod1b:     STZ8
5217                         NEXTOPCODE
5218 Op65M1mod1:
5219 lbl65mod1a:     Direct
5220 lbl65mod1b:     ADC8
5221                         NEXTOPCODE
5222 Op66M1mod1:
5223 lbl66mod1a:     Direct
5224 lbl66mod1b:     ROR8
5225                         NEXTOPCODE
5226 Op67M1mod1:
5227 lbl67mod1a:     DirectIndirectLong
5228 lbl67mod1b:     ADC8
5229                         NEXTOPCODE
5230 Op68M1mod1:
5231 lbl68mod1:      Op68M1
5232                         NEXTOPCODE
5233 Op69M1mod1:
5234 lbl69mod1a:     Immediate8
5235 lbl69mod1b:     ADC8
5236                         NEXTOPCODE
5237 Op6AM1mod1:
5238 lbl6Amod1a:     A_ROR8
5239                         NEXTOPCODE
5240 Op6Bmod1:
5241 lbl6Bmod1:      Op6B
5242                         NEXTOPCODE
5243 Op6Cmod1:
5244 lbl6Cmod1:      Op6C
5245                         NEXTOPCODE
5246 Op6DM1mod1:
5247 lbl6Dmod1a:     Absolute
5248 lbl6Dmod1b:     ADC8
5249                         NEXTOPCODE
5250 Op6EM1mod1:
5251 lbl6Emod1a:     Absolute
5252 lbl6Emod1b:     ROR8
5253                         NEXTOPCODE
5254 Op6FM1mod1:
5255 lbl6Fmod1a:     AbsoluteLong
5256 lbl6Fmod1b:     ADC8
5257                         NEXTOPCODE
5258 Op70mod1:
5259 lbl70mod1:      Op70
5260                         NEXTOPCODE
5261 Op71M1mod1:
5262 lbl71mod1a:     DirectIndirectIndexed1
5263 lbl71mod1b:     ADC8
5264                         NEXTOPCODE
5265 Op72M1mod1:
5266 lbl72mod1a:     DirectIndirect
5267 lbl72mod1b:     ADC8
5268                         NEXTOPCODE
5269 Op73M1mod1:
5270 lbl73mod1a:     StackasmRelativeIndirectIndexed1
5271 lbl73mod1b:     ADC8
5272                         NEXTOPCODE
5273
5274 Op74M1mod1:
5275 lbl74mod1a:     DirectIndexedX1
5276 lbl74mod1b:     STZ8
5277                         NEXTOPCODE
5278 Op75M1mod1:
5279 lbl75mod1a:     DirectIndexedX1
5280 lbl75mod1b:     ADC8
5281                         NEXTOPCODE
5282 Op76M1mod1:
5283 lbl76mod1a:     DirectIndexedX1
5284 lbl76mod1b:     ROR8
5285                         NEXTOPCODE
5286 Op77M1mod1:
5287 lbl77mod1a:     DirectIndirectIndexedLong1
5288 lbl77mod1b:     ADC8
5289                         NEXTOPCODE
5290 Op78mod1:
5291 lbl78mod1:      Op78
5292                         NEXTOPCODE
5293 Op79M1mod1:
5294 lbl79mod1a:     AbsoluteIndexedY1
5295 lbl79mod1b:     ADC8
5296                         NEXTOPCODE
5297 Op7AX1mod1:
5298 lbl7Amod1:      Op7AX1
5299                         NEXTOPCODE
5300 Op7Bmod1:
5301 lbl7Bmod1:      Op7BM1
5302                         NEXTOPCODE
5303 Op7Cmod1:
5304 lbl7Cmod1:      AbsoluteIndexedIndirectX1
5305                 Op7C
5306                         NEXTOPCODE
5307 Op7DM1mod1:
5308 lbl7Dmod1a:     AbsoluteIndexedX1
5309 lbl7Dmod1b:     ADC8
5310                         NEXTOPCODE
5311 Op7EM1mod1:
5312 lbl7Emod1a:     AbsoluteIndexedX1
5313 lbl7Emod1b:     ROR8
5314                         NEXTOPCODE
5315 Op7FM1mod1:
5316 lbl7Fmod1a:     AbsoluteLongIndexedX1
5317 lbl7Fmod1b:     ADC8
5318                         NEXTOPCODE
5319
5320
5321 Op80mod1:
5322 lbl80mod1:      Op80
5323                         NEXTOPCODE
5324 Op81M1mod1:
5325 lbl81mod1a:     DirectIndexedIndirect1
5326 lbl81mod1b:     Op81M1
5327                         NEXTOPCODE
5328 Op82mod1:
5329 lbl82mod1:      Op82
5330                         NEXTOPCODE
5331 Op83M1mod1:
5332 lbl83mod1a:     StackasmRelative
5333 lbl83mod1b:     STA8
5334                         NEXTOPCODE
5335 Op84X1mod1:
5336 lbl84mod1a:     Direct
5337 lbl84mod1b:     STY8
5338                         NEXTOPCODE
5339 Op85M1mod1:
5340 lbl85mod1a:     Direct
5341 lbl85mod1b:     STA8
5342                         NEXTOPCODE
5343 Op86X1mod1:
5344 lbl86mod1a:     Direct
5345 lbl86mod1b:     STX8
5346                         NEXTOPCODE
5347 Op87M1mod1:
5348 lbl87mod1a:     DirectIndirectLong
5349 lbl87mod1b:     STA8
5350                         NEXTOPCODE
5351 Op88X1mod1:
5352 lbl88mod1:      Op88X1
5353                         NEXTOPCODE
5354 Op89M1mod1:
5355 lbl89mod1:      Op89M1
5356                         NEXTOPCODE
5357 Op8AM1mod1:
5358 lbl8Amod1:      Op8AM1X1
5359                         NEXTOPCODE
5360 Op8Bmod1:
5361 lbl8Bmod1:      Op8B
5362                         NEXTOPCODE
5363 Op8CX1mod1:
5364 lbl8Cmod1a:     Absolute
5365 lbl8Cmod1b:     STY8
5366                         NEXTOPCODE
5367 Op8DM1mod1:
5368 lbl8Dmod1a:     Absolute
5369 lbl8Dmod1b:     STA8
5370                         NEXTOPCODE
5371 Op8EX1mod1:
5372 lbl8Emod1a:     Absolute
5373 lbl8Emod1b:     STX8
5374                         NEXTOPCODE
5375 Op8FM1mod1:
5376 lbl8Fmod1a:     AbsoluteLong
5377 lbl8Fmod1b:     STA8
5378                         NEXTOPCODE
5379 Op90mod1:
5380 lbl90mod1:      Op90
5381                         NEXTOPCODE
5382 Op91M1mod1:
5383 lbl91mod1a:     DirectIndirectIndexed1
5384 lbl91mod1b:     STA8
5385                         NEXTOPCODE
5386 Op92M1mod1:
5387 lbl92mod1a:     DirectIndirect
5388 lbl92mod1b:     STA8
5389                         NEXTOPCODE
5390 Op93M1mod1:
5391 lbl93mod1a:     StackasmRelativeIndirectIndexed1
5392 lbl93mod1b:     STA8
5393                         NEXTOPCODE
5394 Op94X1mod1:
5395 lbl94mod1a:     DirectIndexedX1
5396 lbl94mod1b:     STY8
5397                         NEXTOPCODE
5398 Op95M1mod1:
5399 lbl95mod1a:     DirectIndexedX1
5400 lbl95mod1b:     STA8
5401                         NEXTOPCODE
5402 Op96X1mod1:
5403 lbl96mod1a:     DirectIndexedY1
5404 lbl96mod1b:     STX8
5405                         NEXTOPCODE
5406 Op97M1mod1:
5407 lbl97mod1a:     DirectIndirectIndexedLong1
5408 lbl97mod1b:     STA8
5409                         NEXTOPCODE
5410 Op98M1mod1:
5411 lbl98mod1:      Op98M1X1
5412                         NEXTOPCODE
5413 Op99M1mod1:
5414 lbl99mod1a:     AbsoluteIndexedY1
5415 lbl99mod1b:     STA8
5416                         NEXTOPCODE
5417 Op9Amod1:
5418 lbl9Amod1:      Op9AX1
5419                         NEXTOPCODE
5420 Op9BX1mod1:
5421 lbl9Bmod1:      Op9BX1
5422                         NEXTOPCODE
5423 Op9CM1mod1:
5424 lbl9Cmod1a:     Absolute
5425 lbl9Cmod1b:     STZ8
5426                         NEXTOPCODE
5427 Op9DM1mod1:
5428 lbl9Dmod1a:     AbsoluteIndexedX1
5429 lbl9Dmod1b:     STA8
5430                         NEXTOPCODE
5431 Op9EM1mod1:
5432 lbl9Emod1:      AbsoluteIndexedX1
5433                 STZ8
5434                         NEXTOPCODE
5435 Op9FM1mod1:
5436 lbl9Fmod1a:     AbsoluteLongIndexedX1
5437 lbl9Fmod1b:     STA8
5438                         NEXTOPCODE
5439 OpA0X1mod1:
5440 lblA0mod1:      OpA0X1
5441                         NEXTOPCODE
5442 OpA1M1mod1:
5443 lblA1mod1a:     DirectIndexedIndirect1
5444 lblA1mod1b:     LDA8
5445                         NEXTOPCODE
5446 OpA2X1mod1:
5447 lblA2mod1:      OpA2X1
5448                         NEXTOPCODE
5449 OpA3M1mod1:
5450 lblA3mod1a:     StackasmRelative
5451 lblA3mod1b:     LDA8
5452                         NEXTOPCODE
5453 OpA4X1mod1:
5454 lblA4mod1a:     Direct
5455 lblA4mod1b:     LDY8
5456                         NEXTOPCODE
5457 OpA5M1mod1:
5458 lblA5mod1a:     Direct
5459 lblA5mod1b:     LDA8
5460                         NEXTOPCODE
5461 OpA6X1mod1:
5462 lblA6mod1a:     Direct
5463 lblA6mod1b:     LDX8
5464                         NEXTOPCODE
5465 OpA7M1mod1:
5466 lblA7mod1a:     DirectIndirectLong
5467 lblA7mod1b:     LDA8
5468                         NEXTOPCODE
5469 OpA8X1mod1:
5470 lblA8mod1:      OpA8X1M1
5471                         NEXTOPCODE
5472 OpA9M1mod1:
5473 lblA9mod1:      OpA9M1
5474                         NEXTOPCODE
5475 OpAAX1mod1:
5476 lblAAmod1:      OpAAX1M1
5477                         NEXTOPCODE
5478 OpABmod1:
5479 lblABmod1:      OpAB
5480                         NEXTOPCODE
5481 OpACX1mod1:
5482 lblACmod1a:     Absolute
5483 lblACmod1b:     LDY8
5484                         NEXTOPCODE
5485 OpADM1mod1:
5486 lblADmod1a:     Absolute
5487 lblADmod1b:     LDA8
5488                         NEXTOPCODE
5489 OpAEX1mod1:
5490 lblAEmod1a:     Absolute
5491 lblAEmod1b:     LDX8
5492                         NEXTOPCODE
5493 OpAFM1mod1:
5494 lblAFmod1a:     AbsoluteLong
5495 lblAFmod1b:     LDA8
5496                         NEXTOPCODE
5497 OpB0mod1:
5498 lblB0mod1:      OpB0
5499                         NEXTOPCODE
5500 OpB1M1mod1:
5501 lblB1mod1a:     DirectIndirectIndexed1
5502 lblB1mod1b:     LDA8
5503                         NEXTOPCODE
5504 OpB2M1mod1:
5505 lblB2mod1a:     DirectIndirect
5506 lblB2mod1b:     LDA8
5507                         NEXTOPCODE
5508 OpB3M1mod1:
5509 lblB3mod1a:     StackasmRelativeIndirectIndexed1
5510 lblB3mod1b:     LDA8
5511                         NEXTOPCODE
5512 OpB4X1mod1:
5513 lblB4mod1a:     DirectIndexedX1
5514 lblB4mod1b:     LDY8
5515                         NEXTOPCODE
5516 OpB5M1mod1:
5517 lblB5mod1a:     DirectIndexedX1
5518 lblB5mod1b:     LDA8
5519                         NEXTOPCODE
5520 OpB6X1mod1:
5521 lblB6mod1a:     DirectIndexedY1
5522 lblB6mod1b:     LDX8
5523                         NEXTOPCODE
5524 OpB7M1mod1:
5525 lblB7mod1a:     DirectIndirectIndexedLong1
5526 lblB7mod1b:     LDA8
5527                         NEXTOPCODE
5528 OpB8mod1:
5529 lblB8mod1:      OpB8
5530                         NEXTOPCODE
5531 OpB9M1mod1:
5532 lblB9mod1a:     AbsoluteIndexedY1
5533 lblB9mod1b:     LDA8
5534                         NEXTOPCODE
5535 OpBAX1mod1:
5536 lblBAmod1:      OpBAX1
5537                         NEXTOPCODE
5538 OpBBX1mod1:
5539 lblBBmod1:      OpBBX1
5540                         NEXTOPCODE
5541 OpBCX1mod1:
5542 lblBCmod1a:     AbsoluteIndexedX1
5543 lblBCmod1b:     LDY8
5544                         NEXTOPCODE
5545 OpBDM1mod1:
5546 lblBDmod1a:     AbsoluteIndexedX1
5547 lblBDmod1b:     LDA8
5548                         NEXTOPCODE
5549 OpBEX1mod1:
5550 lblBEmod1a:     AbsoluteIndexedY1
5551 lblBEmod1b:     LDX8
5552                         NEXTOPCODE
5553 OpBFM1mod1:
5554 lblBFmod1a:     AbsoluteLongIndexedX1
5555 lblBFmod1b:     LDA8
5556                         NEXTOPCODE
5557 OpC0X1mod1:
5558 lblC0mod1:      OpC0X1
5559                         NEXTOPCODE
5560 OpC1M1mod1:
5561 lblC1mod1a:     DirectIndexedIndirect1
5562 lblC1mod1b:     CMP8
5563                         NEXTOPCODE
5564 OpC2mod1:
5565 lblC2mod1:      OpC2
5566                         NEXTOPCODE
5567 .pool
5568 OpC3M1mod1:
5569 lblC3mod1a:     StackasmRelative
5570 lblC3mod1b:     CMP8
5571                         NEXTOPCODE
5572 OpC4X1mod1:
5573 lblC4mod1a:     Direct
5574 lblC4mod1b:     CMY8
5575                         NEXTOPCODE
5576 OpC5M1mod1:
5577 lblC5mod1a:     Direct
5578 lblC5mod1b:     CMP8
5579                         NEXTOPCODE
5580 OpC6M1mod1:
5581 lblC6mod1a:     Direct
5582 lblC6mod1b:     DEC8
5583                         NEXTOPCODE
5584 OpC7M1mod1:
5585 lblC7mod1a:     DirectIndirectLong
5586 lblC7mod1b:     CMP8
5587                         NEXTOPCODE
5588 OpC8X1mod1:
5589 lblC8mod1:      OpC8X1
5590                         NEXTOPCODE
5591 OpC9M1mod1:
5592 lblC9mod1:      OpC9M1
5593                         NEXTOPCODE
5594 OpCAX1mod1:
5595 lblCAmod1:      OpCAX1
5596                         NEXTOPCODE
5597 OpCBmod1:
5598 lblCBmod1:      OpCB
5599                         NEXTOPCODE
5600 OpCCX1mod1:
5601 lblCCmod1a:     Absolute
5602 lblCCmod1b:     CMY8
5603                         NEXTOPCODE
5604 OpCDM1mod1:
5605 lblCDmod1a:     Absolute
5606 lblCDmod1b:     CMP8
5607                         NEXTOPCODE
5608 OpCEM1mod1:
5609 lblCEmod1a:     Absolute
5610 lblCEmod1b:     DEC8
5611                         NEXTOPCODE
5612 OpCFM1mod1:
5613 lblCFmod1a:     AbsoluteLong
5614 lblCFmod1b:     CMP8
5615                         NEXTOPCODE
5616 OpD0mod1:
5617 lblD0mod1:      OpD0
5618                         NEXTOPCODE
5619 OpD1M1mod1:
5620 lblD1mod1a:     DirectIndirectIndexed1
5621 lblD1mod1b:     CMP8
5622                         NEXTOPCODE
5623 OpD2M1mod1:
5624 lblD2mod1a:     DirectIndirect
5625 lblD2mod1b:     CMP8
5626                         NEXTOPCODE
5627 OpD3M1mod1:
5628 lblD3mod1a:     StackasmRelativeIndirectIndexed1
5629 lblD3mod1b:     CMP8
5630                         NEXTOPCODE
5631 OpD4mod1:
5632 lblD4mod1:      OpD4
5633                         NEXTOPCODE
5634 OpD5M1mod1:
5635 lblD5mod1a:     DirectIndexedX1
5636 lblD5mod1b:     CMP8
5637                         NEXTOPCODE
5638 OpD6M1mod1:
5639 lblD6mod1a:     DirectIndexedX1
5640 lblD6mod1b:     DEC8
5641                         NEXTOPCODE
5642 OpD7M1mod1:
5643 lblD7mod1a:     DirectIndirectIndexedLong1
5644 lblD7mod1b:     CMP8
5645                         NEXTOPCODE
5646 OpD8mod1:
5647 lblD8mod1:      OpD8
5648                         NEXTOPCODE
5649 OpD9M1mod1:
5650 lblD9mod1a:     AbsoluteIndexedY1
5651 lblD9mod1b:     CMP8
5652                         NEXTOPCODE
5653 OpDAX1mod1:
5654 lblDAmod1:      OpDAX1
5655                         NEXTOPCODE
5656 OpDBmod1:
5657 lblDBmod1:      OpDB
5658                         NEXTOPCODE
5659 OpDCmod1:
5660 lblDCmod1:      OpDC
5661                         NEXTOPCODE
5662 OpDDM1mod1:
5663 lblDDmod1a:     AbsoluteIndexedX1
5664 lblDDmod1b:     CMP8
5665                         NEXTOPCODE
5666 OpDEM1mod1:
5667 lblDEmod1a:     AbsoluteIndexedX1
5668 lblDEmod1b:     DEC8
5669                         NEXTOPCODE
5670 OpDFM1mod1:
5671 lblDFmod1a:     AbsoluteLongIndexedX1
5672 lblDFmod1b:     CMP8
5673                         NEXTOPCODE
5674 OpE0X1mod1:
5675 lblE0mod1:      OpE0X1
5676                         NEXTOPCODE
5677 OpE1M1mod1:
5678 lblE1mod1a:     DirectIndexedIndirect1
5679 lblE1mod1b:     SBC8
5680                         NEXTOPCODE
5681 OpE2mod1:
5682 lblE2mod1:      OpE2
5683                         NEXTOPCODE
5684 .pool
5685 OpE3M1mod1:
5686 lblE3mod1a:     StackasmRelative
5687 lblE3mod1b:     SBC8
5688                         NEXTOPCODE
5689 OpE4X1mod1:
5690 lblE4mod1a:     Direct
5691 lblE4mod1b:     CMX8
5692                         NEXTOPCODE
5693 OpE5M1mod1:
5694 lblE5mod1a:     Direct
5695 lblE5mod1b:     SBC8
5696                         NEXTOPCODE
5697 OpE6M1mod1:
5698 lblE6mod1a:     Direct
5699 lblE6mod1b:     INC8
5700                         NEXTOPCODE
5701 OpE7M1mod1:
5702 lblE7mod1a:     DirectIndirectLong
5703 lblE7mod1b:     SBC8
5704                         NEXTOPCODE
5705 OpE8X1mod1:
5706 lblE8mod1:      OpE8X1
5707                         NEXTOPCODE
5708 OpE9M1mod1:
5709 lblE9mod1a:     Immediate8
5710 lblE9mod1b:     SBC8
5711                         NEXTOPCODE
5712 OpEAmod1:
5713 lblEAmod1:      OpEA
5714                         NEXTOPCODE
5715 OpEBmod1:
5716 lblEBmod1:      OpEBM1
5717                         NEXTOPCODE
5718 OpECX1mod1:
5719 lblECmod1a:     Absolute
5720 lblECmod1b:     CMX8
5721                         NEXTOPCODE
5722 OpEDM1mod1:
5723 lblEDmod1a:     Absolute
5724 lblEDmod1b:     SBC8
5725                         NEXTOPCODE
5726 OpEEM1mod1:
5727 lblEEmod1a:     Absolute
5728 lblEEmod1b:     INC8
5729                         NEXTOPCODE
5730 OpEFM1mod1:
5731 lblEFmod1a:     AbsoluteLong
5732 lblEFmod1b:     SBC8
5733                         NEXTOPCODE
5734 OpF0mod1:
5735 lblF0mod1:      OpF0
5736                         NEXTOPCODE
5737 OpF1M1mod1:
5738 lblF1mod1a:     DirectIndirectIndexed1
5739 lblF1mod1b:     SBC8
5740                         NEXTOPCODE
5741 OpF2M1mod1:
5742 lblF2mod1a:     DirectIndirect
5743 lblF2mod1b:     SBC8
5744                         NEXTOPCODE
5745 OpF3M1mod1:
5746 lblF3mod1a:     StackasmRelativeIndirectIndexed1
5747 lblF3mod1b:     SBC8
5748                         NEXTOPCODE
5749 OpF4mod1:
5750 lblF4mod1:      OpF4
5751                         NEXTOPCODE
5752 OpF5M1mod1:
5753 lblF5mod1a:     DirectIndexedX1
5754 lblF5mod1b:     SBC8
5755                         NEXTOPCODE
5756 OpF6M1mod1:
5757 lblF6mod1a:     DirectIndexedX1
5758 lblF6mod1b:     INC8
5759                         NEXTOPCODE
5760 OpF7M1mod1:
5761 lblF7mod1a:     DirectIndirectIndexedLong1
5762 lblF7mod1b:     SBC8
5763                         NEXTOPCODE
5764 OpF8mod1:
5765 lblF8mod1:      OpF8
5766                         NEXTOPCODE
5767 OpF9M1mod1:
5768 lblF9mod1a:     AbsoluteIndexedY1
5769 lblF9mod1b:     SBC8
5770                         NEXTOPCODE
5771 OpFAX1mod1:
5772 lblFAmod1:      OpFAX1
5773                         NEXTOPCODE
5774 OpFBmod1:
5775 lblFBmod1:      OpFB
5776                         NEXTOPCODE
5777 OpFCmod1:
5778 lblFCmod1:      OpFCX1
5779                         NEXTOPCODE
5780 OpFDM1mod1:
5781 lblFDmod1a:     AbsoluteIndexedX1
5782 lblFDmod1b:     SBC8
5783                         NEXTOPCODE
5784 OpFEM1mod1:
5785 lblFEmod1a:     AbsoluteIndexedX1
5786 lblFEmod1b:     INC8
5787                         NEXTOPCODE
5788 OpFFM1mod1:
5789 lblFFmod1a:     AbsoluteLongIndexedX1
5790 lblFFmod1b:     SBC8
5791                         NEXTOPCODE
5792 .pool
5793
5794
5795 jumptable2:             .long   Op00mod2
5796                         .long   Op01M1mod2
5797                         .long   Op02mod2
5798                         .long   Op03M1mod2
5799                         .long   Op04M1mod2
5800                         .long   Op05M1mod2
5801                         .long   Op06M1mod2
5802                         .long   Op07M1mod2
5803                         .long   Op08mod2
5804                         .long   Op09M1mod2
5805                         .long   Op0AM1mod2
5806                         .long   Op0Bmod2
5807                         .long   Op0CM1mod2
5808                         .long   Op0DM1mod2
5809                         .long   Op0EM1mod2
5810                         .long   Op0FM1mod2
5811                         .long   Op10mod2
5812                         .long   Op11M1mod2
5813                         .long   Op12M1mod2
5814                         .long   Op13M1mod2
5815                         .long   Op14M1mod2
5816                         .long   Op15M1mod2
5817                         .long   Op16M1mod2
5818                         .long   Op17M1mod2
5819                         .long   Op18mod2
5820                         .long   Op19M1mod2
5821                         .long   Op1AM1mod2
5822                         .long   Op1Bmod2
5823                         .long   Op1CM1mod2
5824                         .long   Op1DM1mod2
5825                         .long   Op1EM1mod2
5826                         .long   Op1FM1mod2
5827                         .long   Op20mod2
5828                         .long   Op21M1mod2
5829                         .long   Op22mod2
5830                         .long   Op23M1mod2
5831                         .long   Op24M1mod2
5832                         .long   Op25M1mod2
5833                         .long   Op26M1mod2
5834                         .long   Op27M1mod2
5835                         .long   Op28mod2
5836                         .long   Op29M1mod2
5837                         .long   Op2AM1mod2
5838                         .long   Op2Bmod2
5839                         .long   Op2CM1mod2
5840                         .long   Op2DM1mod2
5841                         .long   Op2EM1mod2
5842                         .long   Op2FM1mod2
5843                         .long   Op30mod2
5844                         .long   Op31M1mod2
5845                         .long   Op32M1mod2
5846                         .long   Op33M1mod2
5847                         .long   Op34M1mod2
5848                         .long   Op35M1mod2
5849                         .long   Op36M1mod2
5850                         .long   Op37M1mod2
5851                         .long   Op38mod2
5852                         .long   Op39M1mod2
5853                         .long   Op3AM1mod2
5854                         .long   Op3Bmod2
5855                         .long   Op3CM1mod2
5856                         .long   Op3DM1mod2
5857                         .long   Op3EM1mod2
5858                         .long   Op3FM1mod2
5859                         .long   Op40mod2
5860                         .long   Op41M1mod2
5861                         .long   Op42mod2
5862                         .long   Op43M1mod2
5863                         .long   Op44X0mod2
5864                         .long   Op45M1mod2
5865                         .long   Op46M1mod2
5866                         .long   Op47M1mod2
5867                         .long   Op48M1mod2
5868                         .long   Op49M1mod2
5869                         .long   Op4AM1mod2
5870                         .long   Op4Bmod2
5871                         .long   Op4Cmod2
5872                         .long   Op4DM1mod2
5873                         .long   Op4EM1mod2
5874                         .long   Op4FM1mod2
5875                         .long   Op50mod2
5876                         .long   Op51M1mod2
5877                         .long   Op52M1mod2
5878                         .long   Op53M1mod2
5879                         .long   Op54X0mod2
5880                         .long   Op55M1mod2
5881                         .long   Op56M1mod2
5882                         .long   Op57M1mod2
5883                         .long   Op58mod2
5884                         .long   Op59M1mod2
5885                         .long   Op5AX0mod2
5886                         .long   Op5Bmod2
5887                         .long   Op5Cmod2
5888                         .long   Op5DM1mod2
5889                         .long   Op5EM1mod2
5890                         .long   Op5FM1mod2
5891                         .long   Op60mod2
5892                         .long   Op61M1mod2
5893                         .long   Op62mod2
5894                         .long   Op63M1mod2
5895                         .long   Op64M1mod2
5896                         .long   Op65M1mod2
5897                         .long   Op66M1mod2
5898                         .long   Op67M1mod2
5899                         .long   Op68M1mod2
5900                         .long   Op69M1mod2
5901                         .long   Op6AM1mod2
5902                         .long   Op6Bmod2
5903                         .long   Op6Cmod2
5904                         .long   Op6DM1mod2
5905                         .long   Op6EM1mod2
5906                         .long   Op6FM1mod2
5907                         .long   Op70mod2
5908                         .long   Op71M1mod2
5909                         .long   Op72M1mod2
5910                         .long   Op73M1mod2
5911                         .long   Op74M1mod2
5912                         .long   Op75M1mod2
5913                         .long   Op76M1mod2
5914                         .long   Op77M1mod2
5915                         .long   Op78mod2
5916                         .long   Op79M1mod2
5917                         .long   Op7AX0mod2
5918                         .long   Op7Bmod2
5919                         .long   Op7Cmod2
5920                         .long   Op7DM1mod2
5921                         .long   Op7EM1mod2
5922                         .long   Op7FM1mod2
5923                         .long   Op80mod2
5924                         .long   Op81M1mod2
5925                         .long   Op82mod2
5926                         .long   Op83M1mod2
5927                         .long   Op84X0mod2
5928                         .long   Op85M1mod2
5929                         .long   Op86X0mod2
5930                         .long   Op87M1mod2
5931                         .long   Op88X0mod2
5932                         .long   Op89M1mod2
5933                         .long   Op8AM1mod2
5934                         .long   Op8Bmod2
5935                         .long   Op8CX0mod2
5936                         .long   Op8DM1mod2
5937                         .long   Op8EX0mod2
5938                         .long   Op8FM1mod2
5939                         .long   Op90mod2
5940                         .long   Op91M1mod2
5941                         .long   Op92M1mod2
5942                         .long   Op93M1mod2
5943                         .long   Op94X0mod2
5944                         .long   Op95M1mod2
5945                         .long   Op96X0mod2
5946                         .long   Op97M1mod2
5947                         .long   Op98M1mod2
5948                         .long   Op99M1mod2
5949                         .long   Op9Amod2
5950                         .long   Op9BX0mod2
5951                         .long   Op9CM1mod2
5952                         .long   Op9DM1mod2
5953                         .long   Op9EM1mod2
5954                         .long   Op9FM1mod2
5955                         .long   OpA0X0mod2
5956                         .long   OpA1M1mod2
5957                         .long   OpA2X0mod2
5958                         .long   OpA3M1mod2
5959                         .long   OpA4X0mod2
5960                         .long   OpA5M1mod2
5961                         .long   OpA6X0mod2
5962                         .long   OpA7M1mod2
5963                         .long   OpA8X0mod2
5964                         .long   OpA9M1mod2
5965                         .long   OpAAX0mod2
5966                         .long   OpABmod2
5967                         .long   OpACX0mod2
5968                         .long   OpADM1mod2
5969                         .long   OpAEX0mod2
5970                         .long   OpAFM1mod2
5971                         .long   OpB0mod2
5972                         .long   OpB1M1mod2
5973                         .long   OpB2M1mod2
5974                         .long   OpB3M1mod2
5975                         .long   OpB4X0mod2
5976                         .long   OpB5M1mod2
5977                         .long   OpB6X0mod2
5978                         .long   OpB7M1mod2
5979                         .long   OpB8mod2
5980                         .long   OpB9M1mod2
5981                         .long   OpBAX0mod2
5982                         .long   OpBBX0mod2
5983                         .long   OpBCX0mod2
5984                         .long   OpBDM1mod2
5985                         .long   OpBEX0mod2
5986                         .long   OpBFM1mod2
5987                         .long   OpC0X0mod2
5988                         .long   OpC1M1mod2
5989                         .long   OpC2mod2
5990                         .long   OpC3M1mod2
5991                         .long   OpC4X0mod2
5992                         .long   OpC5M1mod2
5993                         .long   OpC6M1mod2
5994                         .long   OpC7M1mod2
5995                         .long   OpC8X0mod2
5996                         .long   OpC9M1mod2
5997                         .long   OpCAX0mod2
5998                         .long   OpCBmod2
5999                         .long   OpCCX0mod2
6000                         .long   OpCDM1mod2
6001                         .long   OpCEM1mod2
6002                         .long   OpCFM1mod2
6003                         .long   OpD0mod2
6004                         .long   OpD1M1mod2
6005                         .long   OpD2M1mod2
6006                         .long   OpD3M1mod2
6007                         .long   OpD4mod2
6008                         .long   OpD5M1mod2
6009                         .long   OpD6M1mod2
6010                         .long   OpD7M1mod2
6011                         .long   OpD8mod2
6012                         .long   OpD9M1mod2
6013                         .long   OpDAX0mod2
6014                         .long   OpDBmod2
6015                         .long   OpDCmod2
6016                         .long   OpDDM1mod2
6017                         .long   OpDEM1mod2
6018                         .long   OpDFM1mod2
6019                         .long   OpE0X0mod2
6020                         .long   OpE1M1mod2
6021                         .long   OpE2mod2
6022                         .long   OpE3M1mod2
6023                         .long   OpE4X0mod2
6024                         .long   OpE5M1mod2
6025                         .long   OpE6M1mod2
6026                         .long   OpE7M1mod2
6027                         .long   OpE8X0mod2
6028                         .long   OpE9M1mod2
6029                         .long   OpEAmod2
6030                         .long   OpEBmod2
6031                         .long   OpECX0mod2
6032                         .long   OpEDM1mod2
6033                         .long   OpEEM1mod2
6034                         .long   OpEFM1mod2
6035                         .long   OpF0mod2
6036                         .long   OpF1M1mod2
6037                         .long   OpF2M1mod2
6038                         .long   OpF3M1mod2
6039                         .long   OpF4mod2
6040                         .long   OpF5M1mod2
6041                         .long   OpF6M1mod2
6042                         .long   OpF7M1mod2
6043                         .long   OpF8mod2
6044                         .long   OpF9M1mod2
6045                         .long   OpFAX0mod2
6046                         .long   OpFBmod2
6047                         .long   OpFCmod2
6048                         .long   OpFDM1mod2
6049                         .long   OpFEM1mod2
6050                         .long   OpFFM1mod2
6051 Op00mod2:
6052 lbl00mod2:      Op00
6053                         NEXTOPCODE
6054 Op01M1mod2:
6055 lbl01mod2a:     DirectIndexedIndirect0
6056 lbl01mod2b:     ORA8
6057                         NEXTOPCODE
6058 Op02mod2:
6059 lbl02mod2:      Op02
6060                         NEXTOPCODE
6061 Op03M1mod2:
6062 lbl03mod2a:     StackasmRelative
6063 lbl03mod2b:     ORA8
6064                         NEXTOPCODE
6065 Op04M1mod2:
6066 lbl04mod2a:     Direct
6067 lbl04mod2b:     TSB8
6068                         NEXTOPCODE
6069 Op05M1mod2:
6070 lbl05mod2a:     Direct
6071 lbl05mod2b:     ORA8
6072                         NEXTOPCODE
6073 Op06M1mod2:
6074 lbl06mod2a:     Direct
6075 lbl06mod2b:     ASL8
6076                         NEXTOPCODE
6077 Op07M1mod2:
6078 lbl07mod2a:     DirectIndirectLong
6079 lbl07mod2b:     ORA8
6080                         NEXTOPCODE
6081 Op08mod2:
6082 lbl08mod2:      Op08
6083                         NEXTOPCODE
6084 Op09M1mod2:
6085 lbl09mod2:      Op09M1
6086                         NEXTOPCODE
6087 Op0AM1mod2:
6088 lbl0Amod2a:     A_ASL8
6089                         NEXTOPCODE
6090 Op0Bmod2:
6091 lbl0Bmod2:      Op0B
6092                         NEXTOPCODE
6093 Op0CM1mod2:
6094 lbl0Cmod2a:     Absolute
6095 lbl0Cmod2b:     TSB8
6096                         NEXTOPCODE
6097 Op0DM1mod2:
6098 lbl0Dmod2a:     Absolute
6099 lbl0Dmod2b:     ORA8
6100                         NEXTOPCODE
6101 Op0EM1mod2:
6102 lbl0Emod2a:     Absolute
6103 lbl0Emod2b:     ASL8
6104                         NEXTOPCODE
6105 Op0FM1mod2:
6106 lbl0Fmod2a:     AbsoluteLong
6107 lbl0Fmod2b:     ORA8
6108                         NEXTOPCODE
6109 Op10mod2:
6110 lbl10mod2:      Op10
6111                         NEXTOPCODE
6112 Op11M1mod2:
6113 lbl11mod2a:     DirectIndirectIndexed0
6114 lbl11mod2b:     ORA8
6115                         NEXTOPCODE
6116 Op12M1mod2:
6117 lbl12mod2a:     DirectIndirect
6118 lbl12mod2b:     ORA8
6119                         NEXTOPCODE
6120 Op13M1mod2:
6121 lbl13mod2a:     StackasmRelativeIndirectIndexed0
6122 lbl13mod2b:     ORA8
6123                         NEXTOPCODE
6124 Op14M1mod2:
6125 lbl14mod2a:     Direct
6126 lbl14mod2b:     TRB8
6127                         NEXTOPCODE
6128 Op15M1mod2:
6129 lbl15mod2a:     DirectIndexedX0
6130 lbl15mod2b:     ORA8
6131                         NEXTOPCODE
6132 Op16M1mod2:
6133 lbl16mod2a:     DirectIndexedX0
6134 lbl16mod2b:     ASL8
6135                         NEXTOPCODE
6136 Op17M1mod2:
6137 lbl17mod2a:     DirectIndirectIndexedLong0
6138 lbl17mod2b:     ORA8
6139                         NEXTOPCODE
6140 Op18mod2:
6141 lbl18mod2:      Op18
6142                         NEXTOPCODE
6143 Op19M1mod2:
6144 lbl19mod2a:     AbsoluteIndexedY0
6145 lbl19mod2b:     ORA8
6146                         NEXTOPCODE
6147 Op1AM1mod2:
6148 lbl1Amod2a:     A_INC8
6149                         NEXTOPCODE
6150 Op1Bmod2:
6151 lbl1Bmod2:      Op1BM1
6152                         NEXTOPCODE
6153 Op1CM1mod2:
6154 lbl1Cmod2a:     Absolute
6155 lbl1Cmod2b:     TRB8
6156                         NEXTOPCODE
6157 Op1DM1mod2:
6158 lbl1Dmod2a:     AbsoluteIndexedX0
6159 lbl1Dmod2b:     ORA8
6160                         NEXTOPCODE
6161 Op1EM1mod2:
6162 lbl1Emod2a:     AbsoluteIndexedX0
6163 lbl1Emod2b:     ASL8
6164                         NEXTOPCODE
6165 Op1FM1mod2:
6166 lbl1Fmod2a:     AbsoluteLongIndexedX0
6167 lbl1Fmod2b:     ORA8
6168                         NEXTOPCODE
6169 Op20mod2:
6170 lbl20mod2:      Op20
6171                         NEXTOPCODE
6172 Op21M1mod2:
6173 lbl21mod2a:     DirectIndexedIndirect0
6174 lbl21mod2b:     AND8
6175                         NEXTOPCODE
6176 Op22mod2:
6177 lbl22mod2:      Op22
6178                         NEXTOPCODE
6179 Op23M1mod2:
6180 lbl23mod2a:     StackasmRelative
6181 lbl23mod2b:     AND8
6182                         NEXTOPCODE
6183 Op24M1mod2:
6184 lbl24mod2a:     Direct
6185 lbl24mod2b:     BIT8
6186                         NEXTOPCODE
6187 Op25M1mod2:
6188 lbl25mod2a:     Direct
6189 lbl25mod2b:     AND8
6190                         NEXTOPCODE
6191 Op26M1mod2:
6192 lbl26mod2a:     Direct
6193 lbl26mod2b:     ROL8
6194                         NEXTOPCODE
6195 Op27M1mod2:
6196 lbl27mod2a:     DirectIndirectLong
6197 lbl27mod2b:     AND8
6198                         NEXTOPCODE
6199 Op28mod2:
6200 lbl28mod2:      Op28X0M1
6201                         NEXTOPCODE
6202 .pool
6203 Op29M1mod2:
6204 lbl29mod2:      Op29M1
6205                         NEXTOPCODE
6206 Op2AM1mod2:
6207 lbl2Amod2a:     A_ROL8
6208                         NEXTOPCODE
6209 Op2Bmod2:
6210 lbl2Bmod2:      Op2B
6211                         NEXTOPCODE
6212 Op2CM1mod2:
6213 lbl2Cmod2a:     Absolute
6214 lbl2Cmod2b:     BIT8
6215                         NEXTOPCODE
6216 Op2DM1mod2:
6217 lbl2Dmod2a:     Absolute
6218 lbl2Dmod2b:     AND8
6219                         NEXTOPCODE
6220 Op2EM1mod2:
6221 lbl2Emod2a:     Absolute
6222 lbl2Emod2b:     ROL8
6223                         NEXTOPCODE
6224 Op2FM1mod2:
6225 lbl2Fmod2a:     AbsoluteLong
6226 lbl2Fmod2b:     AND8
6227                         NEXTOPCODE
6228 Op30mod2:
6229 lbl30mod2:      Op30
6230                         NEXTOPCODE
6231 Op31M1mod2:
6232 lbl31mod2a:     DirectIndirectIndexed0
6233 lbl31mod2b:     AND8
6234                         NEXTOPCODE
6235 Op32M1mod2:
6236 lbl32mod2a:     DirectIndirect
6237 lbl32mod2b:     AND8
6238                         NEXTOPCODE
6239 Op33M1mod2:
6240 lbl33mod2a:     StackasmRelativeIndirectIndexed0
6241 lbl33mod2b:     AND8
6242                         NEXTOPCODE
6243 Op34M1mod2:
6244 lbl34mod2a:     DirectIndexedX0
6245 lbl34mod2b:     BIT8
6246                         NEXTOPCODE
6247 Op35M1mod2:
6248 lbl35mod2a:     DirectIndexedX0
6249 lbl35mod2b:     AND8
6250                         NEXTOPCODE
6251 Op36M1mod2:
6252 lbl36mod2a:     DirectIndexedX0
6253 lbl36mod2b:     ROL8
6254                         NEXTOPCODE
6255 Op37M1mod2:
6256 lbl37mod2a:     DirectIndirectIndexedLong0
6257 lbl37mod2b:     AND8
6258                         NEXTOPCODE
6259 Op38mod2:
6260 lbl38mod2:      Op38
6261                         NEXTOPCODE
6262 Op39M1mod2:
6263 lbl39mod2a:     AbsoluteIndexedY0
6264 lbl39mod2b:     AND8
6265                         NEXTOPCODE
6266 Op3AM1mod2:
6267 lbl3Amod2a:     A_DEC8
6268                         NEXTOPCODE
6269 Op3Bmod2:
6270 lbl3Bmod2:      Op3BM1
6271                         NEXTOPCODE
6272 Op3CM1mod2:
6273 lbl3Cmod2a:     AbsoluteIndexedX0
6274 lbl3Cmod2b:     BIT8
6275                         NEXTOPCODE
6276 Op3DM1mod2:
6277 lbl3Dmod2a:     AbsoluteIndexedX0
6278 lbl3Dmod2b:     AND8
6279                         NEXTOPCODE
6280 Op3EM1mod2:
6281 lbl3Emod2a:     AbsoluteIndexedX0
6282 lbl3Emod2b:     ROL8
6283                         NEXTOPCODE
6284 Op3FM1mod2:
6285 lbl3Fmod2a:     AbsoluteLongIndexedX0
6286 lbl3Fmod2b:     AND8
6287                         NEXTOPCODE
6288 Op40mod2:
6289 lbl40mod2:      Op40X0M1
6290                         NEXTOPCODE
6291 .pool
6292 Op41M1mod2:
6293 lbl41mod2a:     DirectIndexedIndirect0
6294 lbl41mod2b:     EOR8
6295                         NEXTOPCODE
6296 Op42mod2:
6297 lbl42mod2:      Op42
6298                         NEXTOPCODE
6299 Op43M1mod2:
6300 lbl43mod2a:     StackasmRelative
6301 lbl43mod2b:     EOR8
6302                         NEXTOPCODE
6303 Op44X0mod2:
6304 lbl44mod2:      Op44X0M1
6305                         NEXTOPCODE
6306 Op45M1mod2:
6307 lbl45mod2a:     Direct
6308 lbl45mod2b:     EOR8
6309                         NEXTOPCODE
6310 Op46M1mod2:
6311 lbl46mod2a:     Direct
6312 lbl46mod2b:     LSR8
6313                         NEXTOPCODE
6314 Op47M1mod2:
6315 lbl47mod2a:     DirectIndirectLong
6316 lbl47mod2b:     EOR8
6317                         NEXTOPCODE
6318 Op48M1mod2:
6319 lbl48mod2:      Op48M1
6320                         NEXTOPCODE
6321 Op49M1mod2:
6322 lbl49mod2:      Op49M1
6323                         NEXTOPCODE
6324 Op4AM1mod2:
6325 lbl4Amod2a:     A_LSR8
6326                         NEXTOPCODE
6327 Op4Bmod2:
6328 lbl4Bmod2:      Op4B
6329                         NEXTOPCODE
6330 Op4Cmod2:
6331 lbl4Cmod2:      Op4C
6332                         NEXTOPCODE
6333 Op4DM1mod2:
6334 lbl4Dmod2a:     Absolute
6335 lbl4Dmod2b:     EOR8
6336                         NEXTOPCODE
6337 Op4EM1mod2:
6338 lbl4Emod2a:     Absolute
6339 lbl4Emod2b:     LSR8
6340                         NEXTOPCODE
6341 Op4FM1mod2:
6342 lbl4Fmod2a:     AbsoluteLong
6343 lbl4Fmod2b:     EOR8
6344                         NEXTOPCODE
6345 Op50mod2:
6346 lbl50mod2:      Op50
6347                         NEXTOPCODE
6348 Op51M1mod2:
6349 lbl51mod2a:     DirectIndirectIndexed0
6350 lbl51mod2b:     EOR8
6351                         NEXTOPCODE
6352 Op52M1mod2:
6353 lbl52mod2a:     DirectIndirect
6354 lbl52mod2b:     EOR8
6355                         NEXTOPCODE
6356 Op53M1mod2:
6357 lbl53mod2a:     StackasmRelativeIndirectIndexed0
6358 lbl53mod2b:     EOR8
6359                         NEXTOPCODE
6360 Op54X0mod2:
6361 lbl54mod2:      Op54X0M1
6362                         NEXTOPCODE
6363 Op55M1mod2:
6364 lbl55mod2a:     DirectIndexedX0
6365 lbl55mod2b:     EOR8
6366                         NEXTOPCODE
6367 Op56M1mod2:
6368 lbl56mod2a:     DirectIndexedX0
6369 lbl56mod2b:     LSR8
6370                         NEXTOPCODE
6371 Op57M1mod2:
6372 lbl57mod2a:     DirectIndirectIndexedLong0
6373 lbl57mod2b:     EOR8
6374                         NEXTOPCODE
6375 Op58mod2:
6376 lbl58mod2:      Op58
6377                         NEXTOPCODE
6378 Op59M1mod2:
6379 lbl59mod2a:     AbsoluteIndexedY0
6380 lbl59mod2b:     EOR8
6381                         NEXTOPCODE
6382 Op5AX0mod2:
6383 lbl5Amod2:      Op5AX0
6384                         NEXTOPCODE
6385 Op5Bmod2:
6386 lbl5Bmod2:      Op5BM1
6387                         NEXTOPCODE
6388 Op5Cmod2:
6389 lbl5Cmod2:      Op5C
6390                         NEXTOPCODE
6391 Op5DM1mod2:
6392 lbl5Dmod2a:     AbsoluteIndexedX0
6393 lbl5Dmod2b:     EOR8
6394                         NEXTOPCODE
6395 Op5EM1mod2:
6396 lbl5Emod2a:     AbsoluteIndexedX0
6397 lbl5Emod2b:     LSR8
6398                         NEXTOPCODE
6399 Op5FM1mod2:
6400 lbl5Fmod2a:     AbsoluteLongIndexedX0
6401 lbl5Fmod2b:     EOR8
6402                         NEXTOPCODE
6403 Op60mod2:
6404 lbl60mod2:      Op60
6405                         NEXTOPCODE
6406 Op61M1mod2:
6407 lbl61mod2a:     DirectIndexedIndirect0
6408 lbl61mod2b:     ADC8
6409                         NEXTOPCODE
6410 Op62mod2:
6411 lbl62mod2:      Op62
6412                         NEXTOPCODE
6413 Op63M1mod2:
6414 lbl63mod2a:     StackasmRelative
6415 lbl63mod2b:     ADC8
6416                         NEXTOPCODE
6417 Op64M1mod2:
6418 lbl64mod2a:     Direct
6419 lbl64mod2b:     STZ8
6420                         NEXTOPCODE
6421 Op65M1mod2:
6422 lbl65mod2a:     Direct
6423 lbl65mod2b:     ADC8
6424                         NEXTOPCODE
6425 Op66M1mod2:
6426 lbl66mod2a:     Direct
6427 lbl66mod2b:     ROR8
6428                         NEXTOPCODE
6429 Op67M1mod2:
6430 lbl67mod2a:     DirectIndirectLong
6431 lbl67mod2b:     ADC8
6432                         NEXTOPCODE
6433 Op68M1mod2:
6434 lbl68mod2:      Op68M1
6435                         NEXTOPCODE
6436 Op69M1mod2:
6437 lbl69mod2a:     Immediate8
6438 lbl69mod2b:     ADC8
6439                         NEXTOPCODE
6440 Op6AM1mod2:
6441 lbl6Amod2a:     A_ROR8
6442                         NEXTOPCODE
6443 Op6Bmod2:
6444 lbl6Bmod2:      Op6B
6445                         NEXTOPCODE
6446 Op6Cmod2:
6447 lbl6Cmod2:      Op6C
6448                         NEXTOPCODE
6449 Op6DM1mod2:
6450 lbl6Dmod2a:     Absolute
6451 lbl6Dmod2b:     ADC8
6452                         NEXTOPCODE
6453 Op6EM1mod2:
6454 lbl6Emod2a:     Absolute
6455 lbl6Emod2b:     ROR8
6456                         NEXTOPCODE
6457 Op6FM1mod2:
6458 lbl6Fmod2a:     AbsoluteLong
6459 lbl6Fmod2b:     ADC8
6460                         NEXTOPCODE
6461 Op70mod2:
6462 lbl70mod2:      Op70
6463                         NEXTOPCODE
6464 Op71M1mod2:
6465 lbl71mod2a:     DirectIndirectIndexed0
6466 lbl71mod2b:     ADC8
6467                         NEXTOPCODE
6468 Op72M1mod2:
6469 lbl72mod2a:     DirectIndirect
6470 lbl72mod2b:     ADC8
6471                         NEXTOPCODE
6472 Op73M1mod2:
6473 lbl73mod2a:     StackasmRelativeIndirectIndexed0
6474 lbl73mod2b:     ADC8
6475                         NEXTOPCODE
6476 Op74M1mod2:
6477 lbl74mod2a:     DirectIndexedX0
6478 lbl74mod2b:     STZ8
6479                         NEXTOPCODE
6480 Op75M1mod2:
6481 lbl75mod2a:     DirectIndexedX0
6482 lbl75mod2b:     ADC8
6483                         NEXTOPCODE
6484 Op76M1mod2:
6485 lbl76mod2a:     DirectIndexedX0
6486 lbl76mod2b:     ROR8
6487                         NEXTOPCODE
6488 Op77M1mod2:
6489 lbl77mod2a:     DirectIndirectIndexedLong0
6490 lbl77mod2b:     ADC8
6491                         NEXTOPCODE
6492 Op78mod2:
6493 lbl78mod2:      Op78
6494                         NEXTOPCODE
6495 Op79M1mod2:
6496 lbl79mod2a:     AbsoluteIndexedY0
6497 lbl79mod2b:     ADC8
6498                         NEXTOPCODE
6499 Op7AX0mod2:
6500 lbl7Amod2:      Op7AX0
6501                         NEXTOPCODE
6502 Op7Bmod2:
6503 lbl7Bmod2:      Op7BM1
6504                         NEXTOPCODE
6505 Op7Cmod2:
6506 lbl7Cmod2:      AbsoluteIndexedIndirectX0
6507                 Op7C
6508                         NEXTOPCODE
6509 Op7DM1mod2:
6510 lbl7Dmod2a:     AbsoluteIndexedX0
6511 lbl7Dmod2b:     ADC8
6512                         NEXTOPCODE
6513 Op7EM1mod2:
6514 lbl7Emod2a:     AbsoluteIndexedX0
6515 lbl7Emod2b:     ROR8
6516                         NEXTOPCODE
6517 Op7FM1mod2:
6518 lbl7Fmod2a:     AbsoluteLongIndexedX0
6519 lbl7Fmod2b:     ADC8
6520                         NEXTOPCODE
6521
6522
6523 Op80mod2:
6524 lbl80mod2:      Op80
6525                         NEXTOPCODE
6526 Op81M1mod2:
6527 lbl81mod2a:     DirectIndexedIndirect0
6528 lbl81mod2b:     Op81M1
6529                         NEXTOPCODE
6530 Op82mod2:
6531 lbl82mod2:      Op82
6532                         NEXTOPCODE
6533 Op83M1mod2:
6534 lbl83mod2a:     StackasmRelative
6535 lbl83mod2b:     STA8
6536                         NEXTOPCODE
6537 Op84X0mod2:
6538 lbl84mod2a:     Direct
6539 lbl84mod2b:     STY16
6540                         NEXTOPCODE
6541 Op85M1mod2:
6542 lbl85mod2a:     Direct
6543 lbl85mod2b:     STA8
6544                         NEXTOPCODE
6545 Op86X0mod2:
6546 lbl86mod2a:     Direct
6547 lbl86mod2b:     STX16
6548                         NEXTOPCODE
6549 Op87M1mod2:
6550 lbl87mod2a:     DirectIndirectLong
6551 lbl87mod2b:     STA8
6552                         NEXTOPCODE
6553 Op88X0mod2:
6554 lbl88mod2:      Op88X0
6555                         NEXTOPCODE
6556 Op89M1mod2:
6557 lbl89mod2:      Op89M1
6558                         NEXTOPCODE
6559 Op8AM1mod2:
6560 lbl8Amod2:      Op8AM1X0
6561                         NEXTOPCODE
6562 Op8Bmod2:
6563 lbl8Bmod2:      Op8B
6564                         NEXTOPCODE
6565 Op8CX0mod2:
6566 lbl8Cmod2a:     Absolute
6567 lbl8Cmod2b:     STY16
6568                         NEXTOPCODE
6569 Op8DM1mod2:
6570 lbl8Dmod2a:     Absolute
6571 lbl8Dmod2b:     STA8
6572                         NEXTOPCODE
6573 Op8EX0mod2:
6574 lbl8Emod2a:     Absolute
6575 lbl8Emod2b:     STX16
6576                         NEXTOPCODE
6577 Op8FM1mod2:
6578 lbl8Fmod2a:     AbsoluteLong
6579 lbl8Fmod2b:     STA8
6580                         NEXTOPCODE
6581 Op90mod2:
6582 lbl90mod2:      Op90
6583                         NEXTOPCODE
6584 Op91M1mod2:
6585 lbl91mod2a:     DirectIndirectIndexed0
6586 lbl91mod2b:     STA8
6587                         NEXTOPCODE
6588 Op92M1mod2:
6589 lbl92mod2a:     DirectIndirect
6590 lbl92mod2b:     STA8
6591                         NEXTOPCODE
6592 Op93M1mod2:
6593 lbl93mod2a:     StackasmRelativeIndirectIndexed0
6594 lbl93mod2b:     STA8
6595                         NEXTOPCODE
6596 Op94X0mod2:
6597 lbl94mod2a:     DirectIndexedX0
6598 lbl94mod2b:     STY16
6599                         NEXTOPCODE
6600 Op95M1mod2:
6601 lbl95mod2a:     DirectIndexedX0
6602 lbl95mod2b:     STA8
6603                         NEXTOPCODE
6604 Op96X0mod2:
6605 lbl96mod2a:     DirectIndexedY0
6606 lbl96mod2b:     STX16
6607                         NEXTOPCODE
6608 Op97M1mod2:
6609 lbl97mod2a:     DirectIndirectIndexedLong0
6610 lbl97mod2b:     STA8
6611                         NEXTOPCODE
6612 Op98M1mod2:
6613 lbl98mod2:      Op98M1X0
6614                         NEXTOPCODE
6615 Op99M1mod2:
6616 lbl99mod2a:     AbsoluteIndexedY0
6617 lbl99mod2b:     STA8
6618                         NEXTOPCODE
6619 Op9Amod2:
6620 lbl9Amod2:      Op9AX0
6621                         NEXTOPCODE
6622 Op9BX0mod2:
6623 lbl9Bmod2:      Op9BX0
6624                         NEXTOPCODE
6625 Op9CM1mod2:
6626 lbl9Cmod2a:     Absolute
6627 lbl9Cmod2b:     STZ8
6628                         NEXTOPCODE
6629 Op9DM1mod2:
6630 lbl9Dmod2a:     AbsoluteIndexedX0
6631 lbl9Dmod2b:     STA8
6632                         NEXTOPCODE
6633 Op9EM1mod2:
6634 lbl9Emod2:      AbsoluteIndexedX0
6635                 STZ8
6636                         NEXTOPCODE
6637 Op9FM1mod2:
6638 lbl9Fmod2a:     AbsoluteLongIndexedX0
6639 lbl9Fmod2b:     STA8
6640                         NEXTOPCODE
6641 OpA0X0mod2:
6642 lblA0mod2:      OpA0X0
6643                         NEXTOPCODE
6644 OpA1M1mod2:
6645 lblA1mod2a:     DirectIndexedIndirect0
6646 lblA1mod2b:     LDA8
6647                         NEXTOPCODE
6648 OpA2X0mod2:
6649 lblA2mod2:      OpA2X0
6650                         NEXTOPCODE
6651 OpA3M1mod2:
6652 lblA3mod2a:     StackasmRelative
6653 lblA3mod2b:     LDA8
6654                         NEXTOPCODE
6655 OpA4X0mod2:
6656 lblA4mod2a:     Direct
6657 lblA4mod2b:     LDY16
6658                         NEXTOPCODE
6659 OpA5M1mod2:
6660 lblA5mod2a:     Direct
6661 lblA5mod2b:     LDA8
6662                         NEXTOPCODE
6663 OpA6X0mod2:
6664 lblA6mod2a:     Direct
6665 lblA6mod2b:     LDX16
6666                         NEXTOPCODE
6667 OpA7M1mod2:
6668 lblA7mod2a:     DirectIndirectLong
6669 lblA7mod2b:     LDA8
6670                         NEXTOPCODE
6671 OpA8X0mod2:
6672 lblA8mod2:      OpA8X0M1
6673                         NEXTOPCODE
6674 OpA9M1mod2:
6675 lblA9mod2:      OpA9M1
6676                         NEXTOPCODE
6677 OpAAX0mod2:
6678 lblAAmod2:      OpAAX0M1
6679                         NEXTOPCODE
6680 OpABmod2:
6681 lblABmod2:      OpAB
6682                         NEXTOPCODE
6683 OpACX0mod2:
6684 lblACmod2a:     Absolute
6685 lblACmod2b:     LDY16
6686                         NEXTOPCODE
6687 OpADM1mod2:
6688 lblADmod2a:     Absolute
6689 lblADmod2b:     LDA8
6690                         NEXTOPCODE
6691 OpAEX0mod2:
6692 lblAEmod2a:     Absolute
6693 lblAEmod2b:     LDX16
6694                         NEXTOPCODE
6695 OpAFM1mod2:
6696 lblAFmod2a:     AbsoluteLong
6697 lblAFmod2b:     LDA8
6698                         NEXTOPCODE
6699 OpB0mod2:
6700 lblB0mod2:      OpB0
6701                         NEXTOPCODE
6702 OpB1M1mod2:
6703 lblB1mod2a:     DirectIndirectIndexed0
6704 lblB1mod2b:     LDA8
6705                         NEXTOPCODE
6706 OpB2M1mod2:
6707 lblB2mod2a:     DirectIndirect
6708 lblB2mod2b:     LDA8
6709                         NEXTOPCODE
6710 OpB3M1mod2:
6711 lblB3mod2a:     StackasmRelativeIndirectIndexed0
6712 lblB3mod2b:     LDA8
6713                         NEXTOPCODE
6714 OpB4X0mod2:
6715 lblB4mod2a:     DirectIndexedX0
6716 lblB4mod2b:     LDY16
6717                         NEXTOPCODE
6718 OpB5M1mod2:
6719 lblB5mod2a:     DirectIndexedX0
6720 lblB5mod2b:     LDA8
6721                         NEXTOPCODE
6722 OpB6X0mod2:
6723 lblB6mod2a:     DirectIndexedY0
6724 lblB6mod2b:     LDX16
6725                         NEXTOPCODE
6726 OpB7M1mod2:
6727 lblB7mod2a:     DirectIndirectIndexedLong0
6728 lblB7mod2b:     LDA8
6729                         NEXTOPCODE
6730 OpB8mod2:
6731 lblB8mod2:      OpB8
6732                         NEXTOPCODE
6733 OpB9M1mod2:
6734 lblB9mod2a:     AbsoluteIndexedY0
6735 lblB9mod2b:     LDA8
6736                         NEXTOPCODE
6737 OpBAX0mod2:
6738 lblBAmod2:      OpBAX0
6739                         NEXTOPCODE
6740 OpBBX0mod2:
6741 lblBBmod2:      OpBBX0
6742                         NEXTOPCODE
6743 OpBCX0mod2:
6744 lblBCmod2a:     AbsoluteIndexedX0
6745 lblBCmod2b:     LDY16
6746                         NEXTOPCODE
6747 OpBDM1mod2:
6748 lblBDmod2a:     AbsoluteIndexedX0
6749 lblBDmod2b:     LDA8
6750                         NEXTOPCODE
6751 OpBEX0mod2:
6752 lblBEmod2a:     AbsoluteIndexedY0
6753 lblBEmod2b:     LDX16
6754                         NEXTOPCODE
6755 OpBFM1mod2:
6756 lblBFmod2a:     AbsoluteLongIndexedX0
6757 lblBFmod2b:     LDA8
6758                         NEXTOPCODE
6759 OpC0X0mod2:
6760 lblC0mod2:      OpC0X0
6761                         NEXTOPCODE
6762 OpC1M1mod2:
6763 lblC1mod2a:     DirectIndexedIndirect0
6764 lblC1mod2b:     CMP8
6765                         NEXTOPCODE
6766 OpC2mod2:
6767 lblC2mod2:      OpC2
6768                         NEXTOPCODE
6769 .pool
6770 OpC3M1mod2:
6771 lblC3mod2a:     StackasmRelative
6772 lblC3mod2b:     CMP8
6773                         NEXTOPCODE
6774 OpC4X0mod2:
6775 lblC4mod2a:     Direct
6776 lblC4mod2b:     CMY16
6777                         NEXTOPCODE
6778 OpC5M1mod2:
6779 lblC5mod2a:     Direct
6780 lblC5mod2b:     CMP8
6781                         NEXTOPCODE
6782 OpC6M1mod2:
6783 lblC6mod2a:     Direct
6784 lblC6mod2b:     DEC8
6785                         NEXTOPCODE
6786 OpC7M1mod2:
6787 lblC7mod2a:     DirectIndirectLong
6788 lblC7mod2b:     CMP8
6789                         NEXTOPCODE
6790 OpC8X0mod2:
6791 lblC8mod2:      OpC8X0
6792                         NEXTOPCODE
6793 OpC9M1mod2:
6794 lblC9mod2:      OpC9M1
6795                         NEXTOPCODE
6796 OpCAX0mod2:
6797 lblCAmod2:      OpCAX0
6798                         NEXTOPCODE
6799 OpCBmod2:
6800 lblCBmod2:      OpCB
6801                         NEXTOPCODE
6802 OpCCX0mod2:
6803 lblCCmod2a:     Absolute
6804 lblCCmod2b:     CMY16
6805                         NEXTOPCODE
6806 OpCDM1mod2:
6807 lblCDmod2a:     Absolute
6808 lblCDmod2b:     CMP8
6809                         NEXTOPCODE
6810 OpCEM1mod2:
6811 lblCEmod2a:     Absolute
6812 lblCEmod2b:     DEC8
6813                         NEXTOPCODE
6814 OpCFM1mod2:
6815 lblCFmod2a:     AbsoluteLong
6816 lblCFmod2b:     CMP8
6817                         NEXTOPCODE
6818 OpD0mod2:
6819 lblD0mod2:      OpD0
6820                         NEXTOPCODE
6821 OpD1M1mod2:
6822 lblD1mod2a:     DirectIndirectIndexed0
6823 lblD1mod2b:     CMP8
6824                         NEXTOPCODE
6825 OpD2M1mod2:
6826 lblD2mod2a:     DirectIndirect
6827 lblD2mod2b:     CMP8
6828                         NEXTOPCODE
6829 OpD3M1mod2:
6830 lblD3mod2a:     StackasmRelativeIndirectIndexed0
6831 lblD3mod2b:     CMP8
6832                         NEXTOPCODE
6833 OpD4mod2:
6834 lblD4mod2:      OpD4
6835                         NEXTOPCODE
6836 OpD5M1mod2:
6837 lblD5mod2a:     DirectIndexedX0
6838 lblD5mod2b:     CMP8
6839                         NEXTOPCODE
6840 OpD6M1mod2:
6841 lblD6mod2a:     DirectIndexedX0
6842 lblD6mod2b:     DEC8
6843                         NEXTOPCODE
6844 OpD7M1mod2:
6845 lblD7mod2a:     DirectIndirectIndexedLong0
6846 lblD7mod2b:     CMP8
6847                         NEXTOPCODE
6848 OpD8mod2:
6849 lblD8mod2:      OpD8
6850                         NEXTOPCODE
6851 OpD9M1mod2:
6852 lblD9mod2a:     AbsoluteIndexedY0
6853 lblD9mod2b:     CMP8
6854                         NEXTOPCODE
6855 OpDAX0mod2:
6856 lblDAmod2:      OpDAX0
6857                         NEXTOPCODE
6858 OpDBmod2:
6859 lblDBmod2:      OpDB
6860                         NEXTOPCODE
6861 OpDCmod2:
6862 lblDCmod2:      OpDC
6863                         NEXTOPCODE
6864 OpDDM1mod2:
6865 lblDDmod2a:     AbsoluteIndexedX0
6866 lblDDmod2b:     CMP8
6867                         NEXTOPCODE
6868 OpDEM1mod2:
6869 lblDEmod2a:     AbsoluteIndexedX0
6870 lblDEmod2b:     DEC8
6871                         NEXTOPCODE
6872 OpDFM1mod2:
6873 lblDFmod2a:     AbsoluteLongIndexedX0
6874 lblDFmod2b:     CMP8
6875                         NEXTOPCODE
6876 OpE0X0mod2:
6877 lblE0mod2:      OpE0X0
6878                         NEXTOPCODE
6879 OpE1M1mod2:
6880 lblE1mod2a:     DirectIndexedIndirect0
6881 lblE1mod2b:     SBC8
6882                         NEXTOPCODE
6883 OpE2mod2:
6884 lblE2mod2:      OpE2
6885                         NEXTOPCODE
6886 .pool
6887 OpE3M1mod2:
6888 lblE3mod2a:     StackasmRelative
6889 lblE3mod2b:     SBC8
6890                         NEXTOPCODE
6891 OpE4X0mod2:
6892 lblE4mod2a:     Direct
6893 lblE4mod2b:     CMX16
6894                         NEXTOPCODE
6895 OpE5M1mod2:
6896 lblE5mod2a:     Direct
6897 lblE5mod2b:     SBC8
6898                         NEXTOPCODE
6899 OpE6M1mod2:
6900 lblE6mod2a:     Direct
6901 lblE6mod2b:     INC8
6902                         NEXTOPCODE
6903 OpE7M1mod2:
6904 lblE7mod2a:     DirectIndirectLong
6905 lblE7mod2b:     SBC8
6906                         NEXTOPCODE
6907 OpE8X0mod2:
6908 lblE8mod2:      OpE8X0
6909                         NEXTOPCODE
6910 OpE9M1mod2:
6911 lblE9mod2a:     Immediate8
6912 lblE9mod2b:     SBC8
6913                         NEXTOPCODE
6914 OpEAmod2:
6915 lblEAmod2:      OpEA
6916                         NEXTOPCODE
6917 OpEBmod2:
6918 lblEBmod2:      OpEBM1
6919                         NEXTOPCODE
6920 OpECX0mod2:
6921 lblECmod2a:     Absolute
6922 lblECmod2b:     CMX16
6923                         NEXTOPCODE
6924 OpEDM1mod2:
6925 lblEDmod2a:     Absolute
6926 lblEDmod2b:     SBC8
6927                         NEXTOPCODE
6928 OpEEM1mod2:
6929 lblEEmod2a:     Absolute
6930 lblEEmod2b:     INC8
6931                         NEXTOPCODE
6932 OpEFM1mod2:
6933 lblEFmod2a:     AbsoluteLong
6934 lblEFmod2b:     SBC8
6935                         NEXTOPCODE
6936 OpF0mod2:
6937 lblF0mod2:      OpF0
6938                         NEXTOPCODE
6939 OpF1M1mod2:
6940 lblF1mod2a:     DirectIndirectIndexed0
6941 lblF1mod2b:     SBC8
6942                         NEXTOPCODE
6943 OpF2M1mod2:
6944 lblF2mod2a:     DirectIndirect
6945 lblF2mod2b:     SBC8
6946                         NEXTOPCODE
6947 OpF3M1mod2:
6948 lblF3mod2a:     StackasmRelativeIndirectIndexed0
6949 lblF3mod2b:     SBC8
6950                         NEXTOPCODE
6951 OpF4mod2:
6952 lblF4mod2:      OpF4
6953                         NEXTOPCODE
6954 OpF5M1mod2:
6955 lblF5mod2a:     DirectIndexedX0
6956 lblF5mod2b:     SBC8
6957                         NEXTOPCODE
6958 OpF6M1mod2:
6959 lblF6mod2a:     DirectIndexedX0
6960 lblF6mod2b:     INC8
6961                         NEXTOPCODE
6962 OpF7M1mod2:
6963 lblF7mod2a:     DirectIndirectIndexedLong0
6964 lblF7mod2b:     SBC8
6965                         NEXTOPCODE
6966 OpF8mod2:
6967 lblF8mod2:      OpF8
6968                         NEXTOPCODE
6969 OpF9M1mod2:
6970 lblF9mod2a:     AbsoluteIndexedY0
6971 lblF9mod2b:     SBC8
6972                         NEXTOPCODE
6973 OpFAX0mod2:
6974 lblFAmod2:      OpFAX0
6975                         NEXTOPCODE
6976 OpFBmod2:
6977 lblFBmod2:      OpFB
6978                         NEXTOPCODE
6979 OpFCmod2:
6980 lblFCmod2:      OpFCX0
6981                         NEXTOPCODE
6982 OpFDM1mod2:
6983 lblFDmod2a:     AbsoluteIndexedX0
6984 lblFDmod2b:     SBC8
6985                         NEXTOPCODE
6986 OpFEM1mod2:
6987 lblFEmod2a:     AbsoluteIndexedX0
6988 lblFEmod2b:     INC8
6989                         NEXTOPCODE
6990 OpFFM1mod2:
6991 lblFFmod2a:     AbsoluteLongIndexedX0
6992 lblFFmod2b:     SBC8
6993                         NEXTOPCODE
6994
6995 .pool
6996
6997
6998 jumptable3:             .long   Op00mod3
6999                         .long   Op01M0mod3
7000                         .long   Op02mod3
7001                         .long   Op03M0mod3
7002                         .long   Op04M0mod3
7003                         .long   Op05M0mod3
7004                         .long   Op06M0mod3
7005                         .long   Op07M0mod3
7006                         .long   Op08mod3
7007                         .long   Op09M0mod3
7008                         .long   Op0AM0mod3
7009                         .long   Op0Bmod3
7010                         .long   Op0CM0mod3
7011                         .long   Op0DM0mod3
7012                         .long   Op0EM0mod3
7013                         .long   Op0FM0mod3
7014                         .long   Op10mod3
7015                         .long   Op11M0mod3
7016                         .long   Op12M0mod3
7017                         .long   Op13M0mod3
7018                         .long   Op14M0mod3
7019                         .long   Op15M0mod3
7020                         .long   Op16M0mod3
7021                         .long   Op17M0mod3
7022                         .long   Op18mod3
7023                         .long   Op19M0mod3
7024                         .long   Op1AM0mod3
7025                         .long   Op1Bmod3
7026                         .long   Op1CM0mod3
7027                         .long   Op1DM0mod3
7028                         .long   Op1EM0mod3
7029                         .long   Op1FM0mod3
7030                         .long   Op20mod3
7031                         .long   Op21M0mod3
7032                         .long   Op22mod3
7033                         .long   Op23M0mod3
7034                         .long   Op24M0mod3
7035                         .long   Op25M0mod3
7036                         .long   Op26M0mod3
7037                         .long   Op27M0mod3
7038                         .long   Op28mod3
7039                         .long   Op29M0mod3
7040                         .long   Op2AM0mod3
7041                         .long   Op2Bmod3
7042                         .long   Op2CM0mod3
7043                         .long   Op2DM0mod3
7044                         .long   Op2EM0mod3
7045                         .long   Op2FM0mod3
7046                         .long   Op30mod3
7047                         .long   Op31M0mod3
7048                         .long   Op32M0mod3
7049                         .long   Op33M0mod3
7050                         .long   Op34M0mod3
7051                         .long   Op35M0mod3
7052                         .long   Op36M0mod3
7053                         .long   Op37M0mod3
7054                         .long   Op38mod3
7055                         .long   Op39M0mod3
7056                         .long   Op3AM0mod3
7057                         .long   Op3Bmod3
7058                         .long   Op3CM0mod3
7059                         .long   Op3DM0mod3
7060                         .long   Op3EM0mod3
7061                         .long   Op3FM0mod3
7062                         .long   Op40mod3
7063                         .long   Op41M0mod3
7064                         .long   Op42mod3
7065                         .long   Op43M0mod3
7066                         .long   Op44X0mod3
7067                         .long   Op45M0mod3
7068                         .long   Op46M0mod3
7069                         .long   Op47M0mod3
7070                         .long   Op48M0mod3
7071                         .long   Op49M0mod3
7072                         .long   Op4AM0mod3
7073                         .long   Op4Bmod3
7074                         .long   Op4Cmod3
7075                         .long   Op4DM0mod3
7076                         .long   Op4EM0mod3
7077                         .long   Op4FM0mod3
7078                         .long   Op50mod3
7079                         .long   Op51M0mod3
7080                         .long   Op52M0mod3
7081                         .long   Op53M0mod3
7082                         .long   Op54X0mod3
7083                         .long   Op55M0mod3
7084                         .long   Op56M0mod3
7085                         .long   Op57M0mod3
7086                         .long   Op58mod3
7087                         .long   Op59M0mod3
7088                         .long   Op5AX0mod3
7089                         .long   Op5Bmod3
7090                         .long   Op5Cmod3
7091                         .long   Op5DM0mod3
7092                         .long   Op5EM0mod3
7093                         .long   Op5FM0mod3
7094                         .long   Op60mod3
7095                         .long   Op61M0mod3
7096                         .long   Op62mod3
7097                         .long   Op63M0mod3
7098                         .long   Op64M0mod3
7099                         .long   Op65M0mod3
7100                         .long   Op66M0mod3
7101                         .long   Op67M0mod3
7102                         .long   Op68M0mod3
7103                         .long   Op69M0mod3
7104                         .long   Op6AM0mod3
7105                         .long   Op6Bmod3
7106                         .long   Op6Cmod3
7107                         .long   Op6DM0mod3
7108                         .long   Op6EM0mod3
7109                         .long   Op6FM0mod3
7110                         .long   Op70mod3
7111                         .long   Op71M0mod3
7112                         .long   Op72M0mod3
7113                         .long   Op73M0mod3
7114                         .long   Op74M0mod3
7115                         .long   Op75M0mod3
7116                         .long   Op76M0mod3
7117                         .long   Op77M0mod3
7118                         .long   Op78mod3
7119                         .long   Op79M0mod3
7120                         .long   Op7AX0mod3
7121                         .long   Op7Bmod3
7122                         .long   Op7Cmod3
7123                         .long   Op7DM0mod3
7124                         .long   Op7EM0mod3
7125                         .long   Op7FM0mod3
7126                         .long   Op80mod3
7127                         .long   Op81M0mod3
7128                         .long   Op82mod3
7129                         .long   Op83M0mod3
7130                         .long   Op84X0mod3
7131                         .long   Op85M0mod3
7132                         .long   Op86X0mod3
7133                         .long   Op87M0mod3
7134                         .long   Op88X0mod3
7135                         .long   Op89M0mod3
7136                         .long   Op8AM0mod3
7137                         .long   Op8Bmod3
7138                         .long   Op8CX0mod3
7139                         .long   Op8DM0mod3
7140                         .long   Op8EX0mod3
7141                         .long   Op8FM0mod3
7142                         .long   Op90mod3
7143                         .long   Op91M0mod3
7144                         .long   Op92M0mod3
7145                         .long   Op93M0mod3
7146                         .long   Op94X0mod3
7147                         .long   Op95M0mod3
7148                         .long   Op96X0mod3
7149                         .long   Op97M0mod3
7150                         .long   Op98M0mod3
7151                         .long   Op99M0mod3
7152                         .long   Op9Amod3
7153                         .long   Op9BX0mod3
7154                         .long   Op9CM0mod3
7155                         .long   Op9DM0mod3
7156                         .long   Op9EM0mod3
7157                         .long   Op9FM0mod3
7158                         .long   OpA0X0mod3
7159                         .long   OpA1M0mod3
7160                         .long   OpA2X0mod3
7161                         .long   OpA3M0mod3
7162                         .long   OpA4X0mod3
7163                         .long   OpA5M0mod3
7164                         .long   OpA6X0mod3
7165                         .long   OpA7M0mod3
7166                         .long   OpA8X0mod3
7167                         .long   OpA9M0mod3
7168                         .long   OpAAX0mod3
7169                         .long   OpABmod3
7170                         .long   OpACX0mod3
7171                         .long   OpADM0mod3
7172                         .long   OpAEX0mod3
7173                         .long   OpAFM0mod3
7174                         .long   OpB0mod3
7175                         .long   OpB1M0mod3
7176                         .long   OpB2M0mod3
7177                         .long   OpB3M0mod3
7178                         .long   OpB4X0mod3
7179                         .long   OpB5M0mod3
7180                         .long   OpB6X0mod3
7181                         .long   OpB7M0mod3
7182                         .long   OpB8mod3
7183                         .long   OpB9M0mod3
7184                         .long   OpBAX0mod3
7185                         .long   OpBBX0mod3
7186                         .long   OpBCX0mod3
7187                         .long   OpBDM0mod3
7188                         .long   OpBEX0mod3
7189                         .long   OpBFM0mod3
7190                         .long   OpC0X0mod3
7191                         .long   OpC1M0mod3
7192                         .long   OpC2mod3
7193                         .long   OpC3M0mod3
7194                         .long   OpC4X0mod3
7195                         .long   OpC5M0mod3
7196                         .long   OpC6M0mod3
7197                         .long   OpC7M0mod3
7198                         .long   OpC8X0mod3
7199                         .long   OpC9M0mod3
7200                         .long   OpCAX0mod3
7201                         .long   OpCBmod3
7202                         .long   OpCCX0mod3
7203                         .long   OpCDM0mod3
7204                         .long   OpCEM0mod3
7205                         .long   OpCFM0mod3
7206                         .long   OpD0mod3
7207                         .long   OpD1M0mod3
7208                         .long   OpD2M0mod3
7209                         .long   OpD3M0mod3
7210                         .long   OpD4mod3
7211                         .long   OpD5M0mod3
7212                         .long   OpD6M0mod3
7213                         .long   OpD7M0mod3
7214                         .long   OpD8mod3
7215                         .long   OpD9M0mod3
7216                         .long   OpDAX0mod3
7217                         .long   OpDBmod3
7218                         .long   OpDCmod3
7219                         .long   OpDDM0mod3
7220                         .long   OpDEM0mod3
7221                         .long   OpDFM0mod3
7222                         .long   OpE0X0mod3
7223                         .long   OpE1M0mod3
7224                         .long   OpE2mod3
7225                         .long   OpE3M0mod3
7226                         .long   OpE4X0mod3
7227                         .long   OpE5M0mod3
7228                         .long   OpE6M0mod3
7229                         .long   OpE7M0mod3
7230                         .long   OpE8X0mod3
7231                         .long   OpE9M0mod3
7232                         .long   OpEAmod3
7233                         .long   OpEBmod3
7234                         .long   OpECX0mod3
7235                         .long   OpEDM0mod3
7236                         .long   OpEEM0mod3
7237                         .long   OpEFM0mod3
7238                         .long   OpF0mod3
7239                         .long   OpF1M0mod3
7240                         .long   OpF2M0mod3
7241                         .long   OpF3M0mod3
7242                         .long   OpF4mod3
7243                         .long   OpF5M0mod3
7244                         .long   OpF6M0mod3
7245                         .long   OpF7M0mod3
7246                         .long   OpF8mod3
7247                         .long   OpF9M0mod3
7248                         .long   OpFAX0mod3
7249                         .long   OpFBmod3
7250                         .long   OpFCmod3
7251                         .long   OpFDM0mod3
7252                         .long   OpFEM0mod3
7253                         .long   OpFFM0mod3
7254 Op00mod3:
7255 lbl00mod3:      Op00
7256                         NEXTOPCODE
7257 Op01M0mod3:
7258 lbl01mod3a:     DirectIndexedIndirect0
7259 lbl01mod3b:     ORA16
7260                         NEXTOPCODE
7261 Op02mod3:
7262 lbl02mod3:      Op02
7263                         NEXTOPCODE
7264 Op03M0mod3:
7265 lbl03mod3a:     StackasmRelative
7266 lbl03mod3b:     ORA16
7267                         NEXTOPCODE
7268 Op04M0mod3:
7269 lbl04mod3a:     Direct
7270 lbl04mod3b:     TSB16
7271                         NEXTOPCODE
7272 Op05M0mod3:
7273 lbl05mod3a:     Direct
7274 lbl05mod3b:     ORA16
7275                         NEXTOPCODE
7276 Op06M0mod3:
7277 lbl06mod3a:     Direct
7278 lbl06mod3b:     ASL16
7279                         NEXTOPCODE
7280 Op07M0mod3:
7281 lbl07mod3a:     DirectIndirectLong
7282 lbl07mod3b:     ORA16
7283                         NEXTOPCODE
7284 Op08mod3:
7285 lbl08mod3:      Op08
7286                         NEXTOPCODE
7287 Op09M0mod3:
7288 lbl09mod3:      Op09M0
7289                         NEXTOPCODE
7290 Op0AM0mod3:
7291 lbl0Amod3a:     A_ASL16
7292                         NEXTOPCODE
7293 Op0Bmod3:
7294 lbl0Bmod3:      Op0B
7295                         NEXTOPCODE
7296 Op0CM0mod3:
7297 lbl0Cmod3a:     Absolute
7298 lbl0Cmod3b:     TSB16
7299                         NEXTOPCODE
7300 Op0DM0mod3:
7301 lbl0Dmod3a:     Absolute
7302 lbl0Dmod3b:     ORA16
7303                         NEXTOPCODE
7304 Op0EM0mod3:
7305 lbl0Emod3a:     Absolute
7306 lbl0Emod3b:     ASL16
7307                         NEXTOPCODE
7308 Op0FM0mod3:
7309 lbl0Fmod3a:     AbsoluteLong
7310 lbl0Fmod3b:     ORA16
7311                         NEXTOPCODE
7312 Op10mod3:
7313 lbl10mod3:      Op10
7314                         NEXTOPCODE
7315 Op11M0mod3:
7316 lbl11mod3a:     DirectIndirectIndexed0
7317 lbl11mod3b:     ORA16
7318                         NEXTOPCODE
7319 Op12M0mod3:
7320 lbl12mod3a:     DirectIndirect
7321 lbl12mod3b:     ORA16
7322                         NEXTOPCODE
7323 Op13M0mod3:
7324 lbl13mod3a:     StackasmRelativeIndirectIndexed0
7325 lbl13mod3b:     ORA16
7326                         NEXTOPCODE
7327 Op14M0mod3:
7328 lbl14mod3a:     Direct
7329 lbl14mod3b:     TRB16
7330                         NEXTOPCODE
7331 Op15M0mod3:
7332 lbl15mod3a:     DirectIndexedX0
7333 lbl15mod3b:     ORA16
7334                         NEXTOPCODE
7335 Op16M0mod3:
7336 lbl16mod3a:     DirectIndexedX0
7337 lbl16mod3b:     ASL16
7338                         NEXTOPCODE
7339 Op17M0mod3:
7340 lbl17mod3a:     DirectIndirectIndexedLong0
7341 lbl17mod3b:     ORA16
7342                         NEXTOPCODE
7343 Op18mod3:
7344 lbl18mod3:      Op18
7345                         NEXTOPCODE
7346 Op19M0mod3:
7347 lbl19mod3a:     AbsoluteIndexedY0
7348 lbl19mod3b:     ORA16
7349                         NEXTOPCODE
7350 Op1AM0mod3:
7351 lbl1Amod3a:     A_INC16
7352                         NEXTOPCODE
7353 Op1Bmod3:
7354 lbl1Bmod3:      Op1BM0
7355                         NEXTOPCODE
7356 Op1CM0mod3:
7357 lbl1Cmod3a:     Absolute
7358 lbl1Cmod3b:     TRB16
7359                         NEXTOPCODE
7360 Op1DM0mod3:
7361 lbl1Dmod3a:     AbsoluteIndexedX0
7362 lbl1Dmod3b:     ORA16
7363                         NEXTOPCODE
7364 Op1EM0mod3:
7365 lbl1Emod3a:     AbsoluteIndexedX0
7366 lbl1Emod3b:     ASL16
7367                         NEXTOPCODE
7368 Op1FM0mod3:
7369 lbl1Fmod3a:     AbsoluteLongIndexedX0
7370 lbl1Fmod3b:     ORA16
7371                         NEXTOPCODE
7372 Op20mod3:
7373 lbl20mod3:      Op20
7374                         NEXTOPCODE
7375 Op21M0mod3:
7376 lbl21mod3a:     DirectIndexedIndirect0
7377 lbl21mod3b:     AND16
7378                         NEXTOPCODE
7379 Op22mod3:
7380 lbl22mod3:      Op22
7381                         NEXTOPCODE
7382 Op23M0mod3:
7383 lbl23mod3a:     StackasmRelative
7384 lbl23mod3b:     AND16
7385                         NEXTOPCODE
7386 Op24M0mod3:
7387 lbl24mod3a:     Direct
7388 lbl24mod3b:     BIT16
7389                         NEXTOPCODE
7390 Op25M0mod3:
7391 lbl25mod3a:     Direct
7392 lbl25mod3b:     AND16
7393                         NEXTOPCODE
7394 Op26M0mod3:
7395 lbl26mod3a:     Direct
7396 lbl26mod3b:     ROL16
7397                         NEXTOPCODE
7398 Op27M0mod3:
7399 lbl27mod3a:     DirectIndirectLong
7400 lbl27mod3b:     AND16
7401                         NEXTOPCODE
7402 Op28mod3:
7403 lbl28mod3:      Op28X0M0
7404                         NEXTOPCODE
7405 .pool
7406 Op29M0mod3:
7407 lbl29mod3:      Op29M0
7408                         NEXTOPCODE
7409 Op2AM0mod3:
7410 lbl2Amod3a:     A_ROL16
7411                         NEXTOPCODE
7412 Op2Bmod3:
7413 lbl2Bmod3:      Op2B
7414                         NEXTOPCODE
7415 Op2CM0mod3:
7416 lbl2Cmod3a:     Absolute
7417 lbl2Cmod3b:     BIT16
7418                         NEXTOPCODE
7419 Op2DM0mod3:
7420 lbl2Dmod3a:     Absolute
7421 lbl2Dmod3b:     AND16
7422                         NEXTOPCODE
7423 Op2EM0mod3:
7424 lbl2Emod3a:     Absolute
7425 lbl2Emod3b:     ROL16
7426                         NEXTOPCODE
7427 Op2FM0mod3:
7428 lbl2Fmod3a:     AbsoluteLong
7429 lbl2Fmod3b:     AND16
7430                         NEXTOPCODE
7431 Op30mod3:
7432 lbl30mod3:      Op30
7433                         NEXTOPCODE
7434 Op31M0mod3:
7435 lbl31mod3a:     DirectIndirectIndexed0
7436 lbl31mod3b:     AND16
7437                         NEXTOPCODE
7438 Op32M0mod3:
7439 lbl32mod3a:     DirectIndirect
7440 lbl32mod3b:     AND16
7441                         NEXTOPCODE
7442 Op33M0mod3:
7443 lbl33mod3a:     StackasmRelativeIndirectIndexed0
7444 lbl33mod3b:     AND16
7445                         NEXTOPCODE
7446 Op34M0mod3:
7447 lbl34mod3a:     DirectIndexedX0
7448 lbl34mod3b:     BIT16
7449                         NEXTOPCODE
7450 Op35M0mod3:
7451 lbl35mod3a:     DirectIndexedX0
7452 lbl35mod3b:     AND16
7453                         NEXTOPCODE
7454 Op36M0mod3:
7455 lbl36mod3a:     DirectIndexedX0
7456 lbl36mod3b:     ROL16
7457                         NEXTOPCODE
7458 Op37M0mod3:
7459 lbl37mod3a:     DirectIndirectIndexedLong0
7460 lbl37mod3b:     AND16
7461                         NEXTOPCODE
7462 Op38mod3:
7463 lbl38mod3:      Op38
7464                         NEXTOPCODE
7465 Op39M0mod3:
7466 lbl39mod3a:     AbsoluteIndexedY0
7467 lbl39mod3b:     AND16
7468                         NEXTOPCODE
7469 Op3AM0mod3:
7470 lbl3Amod3a:     A_DEC16
7471                         NEXTOPCODE
7472 Op3Bmod3:
7473 lbl3Bmod3:      Op3BM0
7474                         NEXTOPCODE
7475 Op3CM0mod3:
7476 lbl3Cmod3a:     AbsoluteIndexedX0
7477 lbl3Cmod3b:     BIT16
7478                         NEXTOPCODE
7479 Op3DM0mod3:
7480 lbl3Dmod3a:     AbsoluteIndexedX0
7481 lbl3Dmod3b:     AND16
7482                         NEXTOPCODE
7483 Op3EM0mod3:
7484 lbl3Emod3a:     AbsoluteIndexedX0
7485 lbl3Emod3b:     ROL16
7486                         NEXTOPCODE
7487 Op3FM0mod3:
7488 lbl3Fmod3a:     AbsoluteLongIndexedX0
7489 lbl3Fmod3b:     AND16
7490                         NEXTOPCODE
7491 Op40mod3:
7492 lbl40mod3:      Op40X0M0
7493                         NEXTOPCODE
7494 .pool
7495 Op41M0mod3:
7496 lbl41mod3a:     DirectIndexedIndirect0
7497 lbl41mod3b:     EOR16
7498                         NEXTOPCODE
7499 Op42mod3:
7500 lbl42mod3:      Op42
7501                         NEXTOPCODE
7502 Op43M0mod3:
7503 lbl43mod3a:     StackasmRelative
7504 lbl43mod3b:     EOR16
7505                         NEXTOPCODE
7506 Op44X0mod3:
7507 lbl44mod3:      Op44X0M0
7508                         NEXTOPCODE
7509 Op45M0mod3:
7510 lbl45mod3a:     Direct
7511 lbl45mod3b:     EOR16
7512                         NEXTOPCODE
7513 Op46M0mod3:
7514 lbl46mod3a:     Direct
7515 lbl46mod3b:     LSR16
7516                         NEXTOPCODE
7517 Op47M0mod3:
7518 lbl47mod3a:     DirectIndirectLong
7519 lbl47mod3b:     EOR16
7520                         NEXTOPCODE
7521 Op48M0mod3:
7522 lbl48mod3:      Op48M0
7523                         NEXTOPCODE
7524 Op49M0mod3:
7525 lbl49mod3:      Op49M0
7526                         NEXTOPCODE
7527 Op4AM0mod3:
7528 lbl4Amod3a:     A_LSR16
7529                         NEXTOPCODE
7530 Op4Bmod3:
7531 lbl4Bmod3:      Op4B
7532                         NEXTOPCODE
7533 Op4Cmod3:
7534 lbl4Cmod3:      Op4C
7535                         NEXTOPCODE
7536 Op4DM0mod3:
7537 lbl4Dmod3a:     Absolute
7538 lbl4Dmod3b:     EOR16
7539                         NEXTOPCODE
7540 Op4EM0mod3:
7541 lbl4Emod3a:     Absolute
7542 lbl4Emod3b:     LSR16
7543                         NEXTOPCODE
7544 Op4FM0mod3:
7545 lbl4Fmod3a:     AbsoluteLong
7546 lbl4Fmod3b:     EOR16
7547                         NEXTOPCODE
7548 Op50mod3:
7549 lbl50mod3:      Op50
7550                         NEXTOPCODE
7551 Op51M0mod3:
7552 lbl51mod3a:     DirectIndirectIndexed0
7553 lbl51mod3b:     EOR16
7554                         NEXTOPCODE
7555 Op52M0mod3:
7556 lbl52mod3a:     DirectIndirect
7557 lbl52mod3b:     EOR16
7558                         NEXTOPCODE
7559 Op53M0mod3:
7560 lbl53mod3a:     StackasmRelativeIndirectIndexed0
7561 lbl53mod3b:     EOR16
7562                         NEXTOPCODE
7563 Op54X0mod3:
7564 lbl54mod3:      Op54X0M0
7565                         NEXTOPCODE
7566 Op55M0mod3:
7567 lbl55mod3a:     DirectIndexedX0
7568 lbl55mod3b:     EOR16
7569                         NEXTOPCODE
7570 Op56M0mod3:
7571 lbl56mod3a:     DirectIndexedX0
7572 lbl56mod3b:     LSR16
7573                         NEXTOPCODE
7574 Op57M0mod3:
7575 lbl57mod3a:     DirectIndirectIndexedLong0
7576 lbl57mod3b:     EOR16
7577                         NEXTOPCODE
7578 Op58mod3:
7579 lbl58mod3:      Op58
7580                         NEXTOPCODE
7581 Op59M0mod3:
7582 lbl59mod3a:     AbsoluteIndexedY0
7583 lbl59mod3b:     EOR16
7584                         NEXTOPCODE
7585 Op5AX0mod3:
7586 lbl5Amod3:      Op5AX0
7587                         NEXTOPCODE
7588 Op5Bmod3:
7589 lbl5Bmod3:      Op5BM0
7590                         NEXTOPCODE
7591 Op5Cmod3:
7592 lbl5Cmod3:      Op5C
7593                         NEXTOPCODE
7594 Op5DM0mod3:
7595 lbl5Dmod3a:     AbsoluteIndexedX0
7596 lbl5Dmod3b:     EOR16
7597                         NEXTOPCODE
7598 Op5EM0mod3:
7599 lbl5Emod3a:     AbsoluteIndexedX0
7600 lbl5Emod3b:     LSR16
7601                         NEXTOPCODE
7602 Op5FM0mod3:
7603 lbl5Fmod3a:     AbsoluteLongIndexedX0
7604 lbl5Fmod3b:     EOR16
7605                         NEXTOPCODE
7606 Op60mod3:
7607 lbl60mod3:      Op60
7608                         NEXTOPCODE
7609 Op61M0mod3:
7610 lbl61mod3a:     DirectIndexedIndirect0
7611 lbl61mod3b:     ADC16
7612                         NEXTOPCODE
7613 Op62mod3:
7614 lbl62mod3:      Op62
7615                         NEXTOPCODE
7616 Op63M0mod3:
7617 lbl63mod3a:     StackasmRelative
7618 lbl63mod3b:     ADC16
7619                         NEXTOPCODE
7620 .pool
7621 Op64M0mod3:
7622 lbl64mod3a:     Direct
7623 lbl64mod3b:     STZ16
7624                         NEXTOPCODE
7625 Op65M0mod3:
7626 lbl65mod3a:     Direct
7627 lbl65mod3b:     ADC16
7628                         NEXTOPCODE
7629 .pool
7630 Op66M0mod3:
7631 lbl66mod3a:     Direct
7632 lbl66mod3b:     ROR16
7633                         NEXTOPCODE
7634 Op67M0mod3:
7635 lbl67mod3a:     DirectIndirectLong
7636 lbl67mod3b:     ADC16
7637                         NEXTOPCODE
7638 .pool
7639 Op68M0mod3:
7640 lbl68mod3:      Op68M0
7641                         NEXTOPCODE
7642 Op69M0mod3:
7643 lbl69mod3a:     Immediate16
7644 lbl69mod3b:     ADC16
7645                         NEXTOPCODE
7646 .pool
7647 Op6AM0mod3:
7648 lbl6Amod3a:     A_ROR16
7649                         NEXTOPCODE
7650 Op6Bmod3:
7651 lbl6Bmod3:      Op6B
7652                         NEXTOPCODE
7653 Op6Cmod3:
7654 lbl6Cmod3:      Op6C
7655                         NEXTOPCODE
7656 Op6DM0mod3:
7657 lbl6Dmod3a:     Absolute
7658 lbl6Dmod3b:     ADC16
7659                         NEXTOPCODE
7660 Op6EM0mod3:
7661 lbl6Emod3a:     Absolute
7662 lbl6Emod3b:     ROR16
7663                         NEXTOPCODE
7664 Op6FM0mod3:
7665 lbl6Fmod3a:     AbsoluteLong
7666 lbl6Fmod3b:     ADC16
7667                         NEXTOPCODE
7668 Op70mod3:
7669 lbl70mod3:      Op70
7670                         NEXTOPCODE
7671 Op71M0mod3:
7672 lbl71mod3a:     DirectIndirectIndexed0
7673 lbl71mod3b:     ADC16
7674                         NEXTOPCODE
7675 Op72M0mod3:
7676 lbl72mod3a:     DirectIndirect
7677 lbl72mod3b:     ADC16
7678                         NEXTOPCODE
7679 Op73M0mod3:
7680 lbl73mod3a:     StackasmRelativeIndirectIndexed0
7681 lbl73mod3b:     ADC16
7682                         NEXTOPCODE
7683 .pool
7684 Op74M0mod3:
7685 lbl74mod3a:     DirectIndexedX0
7686 lbl74mod3b:     STZ16
7687                         NEXTOPCODE
7688 Op75M0mod3:
7689 lbl75mod3a:     DirectIndexedX0
7690 lbl75mod3b:     ADC16
7691                         NEXTOPCODE
7692 .pool
7693 Op76M0mod3:
7694 lbl76mod3a:     DirectIndexedX0
7695 lbl76mod3b:     ROR16
7696                         NEXTOPCODE
7697 Op77M0mod3:
7698 lbl77mod3a:     DirectIndirectIndexedLong0
7699 lbl77mod3b:     ADC16
7700                         NEXTOPCODE
7701 Op78mod3:
7702 lbl78mod3:      Op78
7703                         NEXTOPCODE
7704 Op79M0mod3:
7705 lbl79mod3a:     AbsoluteIndexedY0
7706 lbl79mod3b:     ADC16
7707                         NEXTOPCODE
7708 Op7AX0mod3:
7709 lbl7Amod3:      Op7AX0
7710                         NEXTOPCODE
7711 Op7Bmod3:
7712 lbl7Bmod3:      Op7BM0
7713                         NEXTOPCODE
7714 Op7Cmod3:
7715 lbl7Cmod3:      AbsoluteIndexedIndirectX0
7716                 Op7C
7717                         NEXTOPCODE
7718 Op7DM0mod3:
7719 lbl7Dmod3a:     AbsoluteIndexedX0
7720 lbl7Dmod3b:     ADC16
7721                         NEXTOPCODE
7722 Op7EM0mod3:
7723 lbl7Emod3a:     AbsoluteIndexedX0
7724 lbl7Emod3b:     ROR16
7725                         NEXTOPCODE
7726 Op7FM0mod3:
7727 lbl7Fmod3a:     AbsoluteLongIndexedX0
7728 lbl7Fmod3b:     ADC16
7729                         NEXTOPCODE
7730 .pool
7731 Op80mod3:
7732 lbl80mod3:      Op80
7733                         NEXTOPCODE
7734 Op81M0mod3:
7735 lbl81mod3a:     DirectIndexedIndirect0
7736 lbl81mod3b:     Op81M0
7737                         NEXTOPCODE
7738 Op82mod3:
7739 lbl82mod3:      Op82
7740                         NEXTOPCODE
7741 Op83M0mod3:
7742 lbl83mod3a:     StackasmRelative
7743 lbl83mod3b:     STA16
7744                         NEXTOPCODE
7745 Op84X0mod3:
7746 lbl84mod3a:     Direct
7747 lbl84mod3b:     STY16
7748                         NEXTOPCODE
7749 Op85M0mod3:
7750 lbl85mod3a:     Direct
7751 lbl85mod3b:     STA16
7752                         NEXTOPCODE
7753 Op86X0mod3:
7754 lbl86mod3a:     Direct
7755 lbl86mod3b:     STX16
7756                         NEXTOPCODE
7757 Op87M0mod3:
7758 lbl87mod3a:     DirectIndirectLong
7759 lbl87mod3b:     STA16
7760                         NEXTOPCODE
7761 Op88X0mod3:
7762 lbl88mod3:      Op88X0
7763                         NEXTOPCODE
7764 Op89M0mod3:
7765 lbl89mod3:      Op89M0
7766                         NEXTOPCODE
7767 Op8AM0mod3:
7768 lbl8Amod3:      Op8AM0X0
7769                         NEXTOPCODE
7770 Op8Bmod3:
7771 lbl8Bmod3:      Op8B
7772                         NEXTOPCODE
7773 Op8CX0mod3:
7774 lbl8Cmod3a:     Absolute
7775 lbl8Cmod3b:     STY16
7776                         NEXTOPCODE
7777 Op8DM0mod3:
7778 lbl8Dmod3a:     Absolute
7779 lbl8Dmod3b:     STA16
7780                         NEXTOPCODE
7781 Op8EX0mod3:
7782 lbl8Emod3a:     Absolute
7783 lbl8Emod3b:     STX16
7784                         NEXTOPCODE
7785 Op8FM0mod3:
7786 lbl8Fmod3a:     AbsoluteLong
7787 lbl8Fmod3b:     STA16
7788                         NEXTOPCODE
7789 Op90mod3:
7790 lbl90mod3:      Op90
7791                         NEXTOPCODE
7792 Op91M0mod3:
7793 lbl91mod3a:     DirectIndirectIndexed0
7794 lbl91mod3b:     STA16
7795                         NEXTOPCODE
7796 Op92M0mod3:
7797 lbl92mod3a:     DirectIndirect
7798 lbl92mod3b:     STA16
7799                         NEXTOPCODE
7800 Op93M0mod3:
7801 lbl93mod3a:     StackasmRelativeIndirectIndexed0
7802 lbl93mod3b:     STA16
7803                         NEXTOPCODE
7804 Op94X0mod3:
7805 lbl94mod3a:     DirectIndexedX0
7806 lbl94mod3b:     STY16
7807                         NEXTOPCODE
7808 Op95M0mod3:
7809 lbl95mod3a:     DirectIndexedX0
7810 lbl95mod3b:     STA16
7811                         NEXTOPCODE
7812 Op96X0mod3:
7813 lbl96mod3a:     DirectIndexedY0
7814 lbl96mod3b:     STX16
7815                         NEXTOPCODE
7816 Op97M0mod3:
7817 lbl97mod3a:     DirectIndirectIndexedLong0
7818 lbl97mod3b:     STA16
7819                         NEXTOPCODE
7820 Op98M0mod3:
7821 lbl98mod3:      Op98M0X0
7822                         NEXTOPCODE
7823 Op99M0mod3:
7824 lbl99mod3a:     AbsoluteIndexedY0
7825 lbl99mod3b:     STA16
7826                         NEXTOPCODE
7827 Op9Amod3:
7828 lbl9Amod3:      Op9AX0
7829                         NEXTOPCODE
7830 Op9BX0mod3:
7831 lbl9Bmod3:      Op9BX0
7832                         NEXTOPCODE
7833 Op9CM0mod3:
7834 lbl9Cmod3a:     Absolute
7835 lbl9Cmod3b:     STZ16
7836                         NEXTOPCODE
7837 Op9DM0mod3:
7838 lbl9Dmod3a:     AbsoluteIndexedX0
7839 lbl9Dmod3b:     STA16
7840                         NEXTOPCODE
7841 Op9EM0mod3:
7842 lbl9Emod3:      AbsoluteIndexedX0
7843                 STZ16
7844                         NEXTOPCODE
7845 Op9FM0mod3:
7846 lbl9Fmod3a:     AbsoluteLongIndexedX0
7847 lbl9Fmod3b:     STA16
7848                         NEXTOPCODE
7849 OpA0X0mod3:
7850 lblA0mod3:      OpA0X0
7851                         NEXTOPCODE
7852 OpA1M0mod3:
7853 lblA1mod3a:     DirectIndexedIndirect0
7854 lblA1mod3b:     LDA16
7855                         NEXTOPCODE
7856 OpA2X0mod3:
7857 lblA2mod3:      OpA2X0
7858                         NEXTOPCODE
7859 OpA3M0mod3:
7860 lblA3mod3a:     StackasmRelative
7861 lblA3mod3b:     LDA16
7862                         NEXTOPCODE
7863 OpA4X0mod3:
7864 lblA4mod3a:     Direct
7865 lblA4mod3b:     LDY16
7866                         NEXTOPCODE
7867 OpA5M0mod3:
7868 lblA5mod3a:     Direct
7869 lblA5mod3b:     LDA16
7870                         NEXTOPCODE
7871 OpA6X0mod3:
7872 lblA6mod3a:     Direct
7873 lblA6mod3b:     LDX16
7874                         NEXTOPCODE
7875 OpA7M0mod3:
7876 lblA7mod3a:     DirectIndirectLong
7877 lblA7mod3b:     LDA16
7878                         NEXTOPCODE
7879 OpA8X0mod3:
7880 lblA8mod3:      OpA8X0M0
7881                         NEXTOPCODE
7882 OpA9M0mod3:
7883 lblA9mod3:      OpA9M0
7884                         NEXTOPCODE
7885 OpAAX0mod3:
7886 lblAAmod3:      OpAAX0M0
7887                         NEXTOPCODE
7888 OpABmod3:
7889 lblABmod3:      OpAB
7890                         NEXTOPCODE
7891 OpACX0mod3:
7892 lblACmod3a:     Absolute
7893 lblACmod3b:     LDY16
7894                         NEXTOPCODE
7895 OpADM0mod3:
7896 lblADmod3a:     Absolute
7897 lblADmod3b:     LDA16
7898                         NEXTOPCODE
7899 OpAEX0mod3:
7900 lblAEmod3a:     Absolute
7901 lblAEmod3b:     LDX16
7902                         NEXTOPCODE
7903 OpAFM0mod3:
7904 lblAFmod3a:     AbsoluteLong
7905 lblAFmod3b:     LDA16
7906                         NEXTOPCODE
7907 OpB0mod3:
7908 lblB0mod3:      OpB0
7909                         NEXTOPCODE
7910 OpB1M0mod3:
7911 lblB1mod3a:     DirectIndirectIndexed0
7912 lblB1mod3b:     LDA16
7913                         NEXTOPCODE
7914 OpB2M0mod3:
7915 lblB2mod3a:     DirectIndirect
7916 lblB2mod3b:     LDA16
7917                         NEXTOPCODE
7918 OpB3M0mod3:
7919 lblB3mod3a:     StackasmRelativeIndirectIndexed0
7920 lblB3mod3b:     LDA16
7921                         NEXTOPCODE
7922 OpB4X0mod3:
7923 lblB4mod3a:     DirectIndexedX0
7924 lblB4mod3b:     LDY16
7925                         NEXTOPCODE
7926 OpB5M0mod3:
7927 lblB5mod3a:     DirectIndexedX0
7928 lblB5mod3b:     LDA16
7929                         NEXTOPCODE
7930 OpB6X0mod3:
7931 lblB6mod3a:     DirectIndexedY0
7932 lblB6mod3b:     LDX16
7933                         NEXTOPCODE
7934 OpB7M0mod3:
7935 lblB7mod3a:     DirectIndirectIndexedLong0
7936 lblB7mod3b:     LDA16
7937                         NEXTOPCODE
7938 OpB8mod3:
7939 lblB8mod3:      OpB8
7940                         NEXTOPCODE
7941 OpB9M0mod3:
7942 lblB9mod3a:     AbsoluteIndexedY0
7943 lblB9mod3b:     LDA16
7944                         NEXTOPCODE
7945 OpBAX0mod3:
7946 lblBAmod3:      OpBAX0
7947                         NEXTOPCODE
7948 OpBBX0mod3:
7949 lblBBmod3:      OpBBX0
7950                         NEXTOPCODE
7951 OpBCX0mod3:
7952 lblBCmod3a:     AbsoluteIndexedX0
7953 lblBCmod3b:     LDY16
7954                         NEXTOPCODE
7955 OpBDM0mod3:
7956 lblBDmod3a:     AbsoluteIndexedX0
7957 lblBDmod3b:     LDA16
7958                         NEXTOPCODE
7959 OpBEX0mod3:
7960 lblBEmod3a:     AbsoluteIndexedY0
7961 lblBEmod3b:     LDX16
7962                         NEXTOPCODE
7963 OpBFM0mod3:
7964 lblBFmod3a:     AbsoluteLongIndexedX0
7965 lblBFmod3b:     LDA16
7966                         NEXTOPCODE
7967 OpC0X0mod3:
7968 lblC0mod3:      OpC0X0
7969                         NEXTOPCODE
7970 OpC1M0mod3:
7971 lblC1mod3a:     DirectIndexedIndirect0
7972 lblC1mod3b:     CMP16
7973                         NEXTOPCODE
7974 OpC2mod3:
7975 lblC2mod3:      OpC2
7976                         NEXTOPCODE
7977 .pool
7978 OpC3M0mod3:
7979 lblC3mod3a:     StackasmRelative
7980 lblC3mod3b:     CMP16
7981                         NEXTOPCODE
7982 OpC4X0mod3:
7983 lblC4mod3a:     Direct
7984 lblC4mod3b:     CMY16
7985                         NEXTOPCODE
7986 OpC5M0mod3:
7987 lblC5mod3a:     Direct
7988 lblC5mod3b:     CMP16
7989                         NEXTOPCODE
7990 OpC6M0mod3:
7991 lblC6mod3a:     Direct
7992 lblC6mod3b:     DEC16
7993                         NEXTOPCODE
7994 OpC7M0mod3:
7995 lblC7mod3a:     DirectIndirectLong
7996 lblC7mod3b:     CMP16
7997                         NEXTOPCODE
7998 OpC8X0mod3:
7999 lblC8mod3:      OpC8X0
8000                         NEXTOPCODE
8001 OpC9M0mod3:
8002 lblC9mod3:      OpC9M0
8003                         NEXTOPCODE
8004 OpCAX0mod3:
8005 lblCAmod3:      OpCAX0
8006                         NEXTOPCODE
8007 OpCBmod3:
8008 lblCBmod3:      OpCB
8009                         NEXTOPCODE
8010 OpCCX0mod3:
8011 lblCCmod3a:     Absolute
8012 lblCCmod3b:     CMY16
8013                         NEXTOPCODE
8014 OpCDM0mod3:
8015 lblCDmod3a:     Absolute
8016 lblCDmod3b:     CMP16
8017                         NEXTOPCODE
8018 OpCEM0mod3:
8019 lblCEmod3a:     Absolute
8020 lblCEmod3b:     DEC16
8021                         NEXTOPCODE
8022 OpCFM0mod3:
8023 lblCFmod3a:     AbsoluteLong
8024 lblCFmod3b:     CMP16
8025                         NEXTOPCODE
8026 OpD0mod3:
8027 lblD0mod3:      OpD0
8028                         NEXTOPCODE
8029 OpD1M0mod3:
8030 lblD1mod3a:     DirectIndirectIndexed0
8031 lblD1mod3b:     CMP16
8032                         NEXTOPCODE
8033 OpD2M0mod3:
8034 lblD2mod3a:     DirectIndirect
8035 lblD2mod3b:     CMP16
8036                         NEXTOPCODE
8037 OpD3M0mod3:
8038 lblD3mod3a:     StackasmRelativeIndirectIndexed0
8039 lblD3mod3b:     CMP16
8040                         NEXTOPCODE
8041 OpD4mod3:
8042 lblD4mod3:      OpD4
8043                         NEXTOPCODE
8044 OpD5M0mod3:
8045 lblD5mod3a:     DirectIndexedX0
8046 lblD5mod3b:     CMP16
8047                         NEXTOPCODE
8048 OpD6M0mod3:
8049 lblD6mod3a:     DirectIndexedX0
8050 lblD6mod3b:     DEC16
8051                         NEXTOPCODE
8052 OpD7M0mod3:
8053 lblD7mod3a:     DirectIndirectIndexedLong0
8054 lblD7mod3b:     CMP16
8055                         NEXTOPCODE
8056 OpD8mod3:
8057 lblD8mod3:      OpD8
8058                         NEXTOPCODE
8059 OpD9M0mod3:
8060 lblD9mod3a:     AbsoluteIndexedY0
8061 lblD9mod3b:     CMP16
8062                         NEXTOPCODE
8063 OpDAX0mod3:
8064 lblDAmod3:      OpDAX0
8065                         NEXTOPCODE
8066 OpDBmod3:
8067 lblDBmod3:      OpDB
8068                         NEXTOPCODE
8069 OpDCmod3:
8070 lblDCmod3:      OpDC
8071                         NEXTOPCODE
8072 OpDDM0mod3:
8073 lblDDmod3a:     AbsoluteIndexedX0
8074 lblDDmod3b:     CMP16
8075                         NEXTOPCODE
8076 OpDEM0mod3:
8077 lblDEmod3a:     AbsoluteIndexedX0
8078 lblDEmod3b:     DEC16
8079                         NEXTOPCODE
8080 OpDFM0mod3:
8081 lblDFmod3a:     AbsoluteLongIndexedX0
8082 lblDFmod3b:     CMP16
8083                         NEXTOPCODE
8084 OpE0X0mod3:
8085 lblE0mod3:      OpE0X0
8086                         NEXTOPCODE
8087 OpE1M0mod3:
8088 lblE1mod3a:     DirectIndexedIndirect0
8089 lblE1mod3b:     SBC16
8090                         NEXTOPCODE
8091 OpE2mod3:
8092 lblE2mod3:      OpE2
8093                         NEXTOPCODE
8094 .pool
8095 OpE3M0mod3:
8096 lblE3mod3a:     StackasmRelative
8097 lblE3mod3b:     SBC16
8098                         NEXTOPCODE
8099 OpE4X0mod3:
8100 lblE4mod3a:     Direct
8101 lblE4mod3b:     CMX16
8102                         NEXTOPCODE
8103 OpE5M0mod3:
8104 lblE5mod3a:     Direct
8105 lblE5mod3b:     SBC16
8106                         NEXTOPCODE
8107 OpE6M0mod3:
8108 lblE6mod3a:     Direct
8109 lblE6mod3b:     INC16
8110                         NEXTOPCODE
8111 OpE7M0mod3:
8112 lblE7mod3a:     DirectIndirectLong
8113 lblE7mod3b:     SBC16
8114                         NEXTOPCODE
8115 OpE8X0mod3:
8116 lblE8mod3:      OpE8X0
8117                         NEXTOPCODE
8118 OpE9M0mod3:
8119 lblE9mod3a:     Immediate16
8120 lblE9mod3b:     SBC16
8121                         NEXTOPCODE
8122 OpEAmod3:
8123 lblEAmod3:      OpEA
8124                         NEXTOPCODE
8125 OpEBmod3:
8126 lblEBmod3:      OpEBM0
8127                         NEXTOPCODE
8128 OpECX0mod3:
8129 lblECmod3a:     Absolute
8130 lblECmod3b:     CMX16
8131                         NEXTOPCODE
8132 OpEDM0mod3:
8133 lblEDmod3a:     Absolute
8134 lblEDmod3b:     SBC16
8135                         NEXTOPCODE
8136 OpEEM0mod3:
8137 lblEEmod3a:     Absolute
8138 lblEEmod3b:     INC16
8139                         NEXTOPCODE
8140 OpEFM0mod3:
8141 lblEFmod3a:     AbsoluteLong
8142 lblEFmod3b:     SBC16
8143                         NEXTOPCODE
8144 OpF0mod3:
8145 lblF0mod3:      OpF0
8146                         NEXTOPCODE
8147 OpF1M0mod3:
8148 lblF1mod3a:     DirectIndirectIndexed0
8149 lblF1mod3b:     SBC16
8150                         NEXTOPCODE
8151 OpF2M0mod3:
8152 lblF2mod3a:     DirectIndirect
8153 lblF2mod3b:     SBC16
8154                         NEXTOPCODE
8155 OpF3M0mod3:
8156 lblF3mod3a:     StackasmRelativeIndirectIndexed0
8157 lblF3mod3b:     SBC16
8158                         NEXTOPCODE
8159 OpF4mod3:
8160 lblF4mod3:      OpF4
8161                         NEXTOPCODE
8162 OpF5M0mod3:
8163 lblF5mod3a:     DirectIndexedX0
8164 lblF5mod3b:     SBC16
8165                         NEXTOPCODE
8166 OpF6M0mod3:
8167 lblF6mod3a:     DirectIndexedX0
8168 lblF6mod3b:     INC16
8169                         NEXTOPCODE
8170 OpF7M0mod3:
8171 lblF7mod3a:     DirectIndirectIndexedLong0
8172 lblF7mod3b:     SBC16
8173                         NEXTOPCODE
8174 OpF8mod3:
8175 lblF8mod3:      OpF8
8176                         NEXTOPCODE
8177 OpF9M0mod3:
8178 lblF9mod3a:     AbsoluteIndexedY0
8179 lblF9mod3b:     SBC16
8180                         NEXTOPCODE
8181 OpFAX0mod3:
8182 lblFAmod3:      OpFAX0
8183                         NEXTOPCODE
8184 OpFBmod3:
8185 lblFBmod3:      OpFB
8186                         NEXTOPCODE
8187 OpFCmod3:
8188 lblFCmod3:      OpFCX0
8189                         NEXTOPCODE
8190 OpFDM0mod3:
8191 lblFDmod3a:     AbsoluteIndexedX0
8192 lblFDmod3b:     SBC16
8193                         NEXTOPCODE
8194 OpFEM0mod3:
8195 lblFEmod3a:     AbsoluteIndexedX0
8196 lblFEmod3b:     INC16
8197                         NEXTOPCODE
8198 OpFFM0mod3:
8199 lblFFmod3a:     AbsoluteLongIndexedX0
8200 lblFFmod3b:     SBC16
8201                         NEXTOPCODE
8202 .pool
8203
8204 jumptable4:             .long   Op00mod4
8205                         .long   Op01M0mod4
8206                         .long   Op02mod4
8207                         .long   Op03M0mod4
8208                         .long   Op04M0mod4
8209                         .long   Op05M0mod4
8210                         .long   Op06M0mod4
8211                         .long   Op07M0mod4
8212                         .long   Op08mod4
8213                         .long   Op09M0mod4
8214                         .long   Op0AM0mod4
8215                         .long   Op0Bmod4
8216                         .long   Op0CM0mod4
8217                         .long   Op0DM0mod4
8218                         .long   Op0EM0mod4
8219                         .long   Op0FM0mod4
8220                         .long   Op10mod4
8221                         .long   Op11M0mod4
8222                         .long   Op12M0mod4
8223                         .long   Op13M0mod4
8224                         .long   Op14M0mod4
8225                         .long   Op15M0mod4
8226                         .long   Op16M0mod4
8227                         .long   Op17M0mod4
8228                         .long   Op18mod4
8229                         .long   Op19M0mod4
8230                         .long   Op1AM0mod4
8231                         .long   Op1Bmod4
8232                         .long   Op1CM0mod4
8233                         .long   Op1DM0mod4
8234                         .long   Op1EM0mod4
8235                         .long   Op1FM0mod4
8236                         .long   Op20mod4
8237                         .long   Op21M0mod4
8238                         .long   Op22mod4
8239                         .long   Op23M0mod4
8240                         .long   Op24M0mod4
8241                         .long   Op25M0mod4
8242                         .long   Op26M0mod4
8243                         .long   Op27M0mod4
8244                         .long   Op28mod4
8245                         .long   Op29M0mod4
8246                         .long   Op2AM0mod4
8247                         .long   Op2Bmod4
8248                         .long   Op2CM0mod4
8249                         .long   Op2DM0mod4
8250                         .long   Op2EM0mod4
8251                         .long   Op2FM0mod4
8252                         .long   Op30mod4
8253                         .long   Op31M0mod4
8254                         .long   Op32M0mod4
8255                         .long   Op33M0mod4
8256                         .long   Op34M0mod4
8257                         .long   Op35M0mod4
8258                         .long   Op36M0mod4
8259                         .long   Op37M0mod4
8260                         .long   Op38mod4
8261                         .long   Op39M0mod4
8262                         .long   Op3AM0mod4
8263                         .long   Op3Bmod4
8264                         .long   Op3CM0mod4
8265                         .long   Op3DM0mod4
8266                         .long   Op3EM0mod4
8267                         .long   Op3FM0mod4
8268                         .long   Op40mod4
8269                         .long   Op41M0mod4
8270                         .long   Op42mod4
8271                         .long   Op43M0mod4
8272                         .long   Op44X1mod4
8273                         .long   Op45M0mod4
8274                         .long   Op46M0mod4
8275                         .long   Op47M0mod4
8276                         .long   Op48M0mod4
8277                         .long   Op49M0mod4
8278                         .long   Op4AM0mod4
8279                         .long   Op4Bmod4
8280                         .long   Op4Cmod4
8281                         .long   Op4DM0mod4
8282                         .long   Op4EM0mod4
8283                         .long   Op4FM0mod4
8284                         .long   Op50mod4
8285                         .long   Op51M0mod4
8286                         .long   Op52M0mod4
8287                         .long   Op53M0mod4
8288                         .long   Op54X1mod4
8289                         .long   Op55M0mod4
8290                         .long   Op56M0mod4
8291                         .long   Op57M0mod4
8292                         .long   Op58mod4
8293                         .long   Op59M0mod4
8294                         .long   Op5AX1mod4
8295                         .long   Op5Bmod4
8296                         .long   Op5Cmod4
8297                         .long   Op5DM0mod4
8298                         .long   Op5EM0mod4
8299                         .long   Op5FM0mod4
8300                         .long   Op60mod4
8301                         .long   Op61M0mod4
8302                         .long   Op62mod4
8303                         .long   Op63M0mod4
8304                         .long   Op64M0mod4
8305                         .long   Op65M0mod4
8306                         .long   Op66M0mod4
8307                         .long   Op67M0mod4
8308                         .long   Op68M0mod4
8309                         .long   Op69M0mod4
8310                         .long   Op6AM0mod4
8311                         .long   Op6Bmod4
8312                         .long   Op6Cmod4
8313                         .long   Op6DM0mod4
8314                         .long   Op6EM0mod4
8315                         .long   Op6FM0mod4
8316                         .long   Op70mod4
8317                         .long   Op71M0mod4
8318                         .long   Op72M0mod4
8319                         .long   Op73M0mod4
8320                         .long   Op74M0mod4
8321                         .long   Op75M0mod4
8322                         .long   Op76M0mod4
8323                         .long   Op77M0mod4
8324                         .long   Op78mod4
8325                         .long   Op79M0mod4
8326                         .long   Op7AX1mod4
8327                         .long   Op7Bmod4
8328                         .long   Op7Cmod4
8329                         .long   Op7DM0mod4
8330                         .long   Op7EM0mod4
8331                         .long   Op7FM0mod4
8332                         .long   Op80mod4
8333                         .long   Op81M0mod4
8334                         .long   Op82mod4
8335                         .long   Op83M0mod4
8336                         .long   Op84X1mod4
8337                         .long   Op85M0mod4
8338                         .long   Op86X1mod4
8339                         .long   Op87M0mod4
8340                         .long   Op88X1mod4
8341                         .long   Op89M0mod4
8342                         .long   Op8AM0mod4
8343                         .long   Op8Bmod4
8344                         .long   Op8CX1mod4
8345                         .long   Op8DM0mod4
8346                         .long   Op8EX1mod4
8347                         .long   Op8FM0mod4
8348                         .long   Op90mod4
8349                         .long   Op91M0mod4
8350                         .long   Op92M0mod4
8351                         .long   Op93M0mod4
8352                         .long   Op94X1mod4
8353                         .long   Op95M0mod4
8354                         .long   Op96X1mod4
8355                         .long   Op97M0mod4
8356                         .long   Op98M0mod4
8357                         .long   Op99M0mod4
8358                         .long   Op9Amod4
8359                         .long   Op9BX1mod4
8360                         .long   Op9CM0mod4
8361                         .long   Op9DM0mod4
8362                         .long   Op9EM0mod4
8363                         .long   Op9FM0mod4
8364                         .long   OpA0X1mod4
8365                         .long   OpA1M0mod4
8366                         .long   OpA2X1mod4
8367                         .long   OpA3M0mod4
8368                         .long   OpA4X1mod4
8369                         .long   OpA5M0mod4
8370                         .long   OpA6X1mod4
8371                         .long   OpA7M0mod4
8372                         .long   OpA8X1mod4
8373                         .long   OpA9M0mod4
8374                         .long   OpAAX1mod4
8375                         .long   OpABmod4
8376                         .long   OpACX1mod4
8377                         .long   OpADM0mod4
8378                         .long   OpAEX1mod4
8379                         .long   OpAFM0mod4
8380                         .long   OpB0mod4
8381                         .long   OpB1M0mod4
8382                         .long   OpB2M0mod4
8383                         .long   OpB3M0mod4
8384                         .long   OpB4X1mod4
8385                         .long   OpB5M0mod4
8386                         .long   OpB6X1mod4
8387                         .long   OpB7M0mod4
8388                         .long   OpB8mod4
8389                         .long   OpB9M0mod4
8390                         .long   OpBAX1mod4
8391                         .long   OpBBX1mod4
8392                         .long   OpBCX1mod4
8393                         .long   OpBDM0mod4
8394                         .long   OpBEX1mod4
8395                         .long   OpBFM0mod4
8396                         .long   OpC0X1mod4
8397                         .long   OpC1M0mod4
8398                         .long   OpC2mod4
8399                         .long   OpC3M0mod4
8400                         .long   OpC4X1mod4
8401                         .long   OpC5M0mod4
8402                         .long   OpC6M0mod4
8403                         .long   OpC7M0mod4
8404                         .long   OpC8X1mod4
8405                         .long   OpC9M0mod4
8406                         .long   OpCAX1mod4
8407                         .long   OpCBmod4
8408                         .long   OpCCX1mod4
8409                         .long   OpCDM0mod4
8410                         .long   OpCEM0mod4
8411                         .long   OpCFM0mod4
8412                         .long   OpD0mod4
8413                         .long   OpD1M0mod4
8414                         .long   OpD2M0mod4
8415                         .long   OpD3M0mod4
8416                         .long   OpD4mod4
8417                         .long   OpD5M0mod4
8418                         .long   OpD6M0mod4
8419                         .long   OpD7M0mod4
8420                         .long   OpD8mod4
8421                         .long   OpD9M0mod4
8422                         .long   OpDAX1mod4
8423                         .long   OpDBmod4
8424                         .long   OpDCmod4
8425                         .long   OpDDM0mod4
8426                         .long   OpDEM0mod4
8427                         .long   OpDFM0mod4
8428                         .long   OpE0X1mod4
8429                         .long   OpE1M0mod4
8430                         .long   OpE2mod4
8431                         .long   OpE3M0mod4
8432                         .long   OpE4X1mod4
8433                         .long   OpE5M0mod4
8434                         .long   OpE6M0mod4
8435                         .long   OpE7M0mod4
8436                         .long   OpE8X1mod4
8437                         .long   OpE9M0mod4
8438                         .long   OpEAmod4
8439                         .long   OpEBmod4
8440                         .long   OpECX1mod4
8441                         .long   OpEDM0mod4
8442                         .long   OpEEM0mod4
8443                         .long   OpEFM0mod4
8444                         .long   OpF0mod4
8445                         .long   OpF1M0mod4
8446                         .long   OpF2M0mod4
8447                         .long   OpF3M0mod4
8448                         .long   OpF4mod4
8449                         .long   OpF5M0mod4
8450                         .long   OpF6M0mod4
8451                         .long   OpF7M0mod4
8452                         .long   OpF8mod4
8453                         .long   OpF9M0mod4
8454                         .long   OpFAX1mod4
8455                         .long   OpFBmod4
8456                         .long   OpFCmod4
8457                         .long   OpFDM0mod4
8458                         .long   OpFEM0mod4
8459                         .long   OpFFM0mod4
8460 Op00mod4:
8461 lbl00mod4:      Op00
8462                         NEXTOPCODE
8463 Op01M0mod4:
8464 lbl01mod4a:     DirectIndexedIndirect1
8465 lbl01mod4b:     ORA16
8466                         NEXTOPCODE
8467 Op02mod4:
8468 lbl02mod4:      Op02
8469                         NEXTOPCODE
8470 Op03M0mod4:
8471 lbl03mod4a:     StackasmRelative
8472 lbl03mod4b:     ORA16
8473                         NEXTOPCODE
8474 Op04M0mod4:
8475 lbl04mod4a:     Direct
8476 lbl04mod4b:     TSB16
8477                         NEXTOPCODE
8478 Op05M0mod4:
8479 lbl05mod4a:     Direct
8480 lbl05mod4b:     ORA16
8481                         NEXTOPCODE
8482 Op06M0mod4:
8483 lbl06mod4a:     Direct
8484 lbl06mod4b:     ASL16
8485                         NEXTOPCODE
8486 Op07M0mod4:
8487 lbl07mod4a:     DirectIndirectLong
8488 lbl07mod4b:     ORA16
8489                         NEXTOPCODE
8490 Op08mod4:
8491 lbl08mod4:      Op08
8492                         NEXTOPCODE
8493 Op09M0mod4:
8494 lbl09mod4:      Op09M0
8495                         NEXTOPCODE
8496 Op0AM0mod4:
8497 lbl0Amod4a:     A_ASL16
8498                         NEXTOPCODE
8499 Op0Bmod4:
8500 lbl0Bmod4:      Op0B
8501                         NEXTOPCODE
8502 Op0CM0mod4:
8503 lbl0Cmod4a:     Absolute
8504 lbl0Cmod4b:     TSB16
8505                         NEXTOPCODE
8506 Op0DM0mod4:
8507 lbl0Dmod4a:     Absolute
8508 lbl0Dmod4b:     ORA16
8509                         NEXTOPCODE
8510 Op0EM0mod4:
8511 lbl0Emod4a:     Absolute
8512 lbl0Emod4b:     ASL16
8513                         NEXTOPCODE
8514 Op0FM0mod4:
8515 lbl0Fmod4a:     AbsoluteLong
8516 lbl0Fmod4b:     ORA16
8517                         NEXTOPCODE
8518 Op10mod4:
8519 lbl10mod4:      Op10
8520                         NEXTOPCODE
8521 Op11M0mod4:
8522 lbl11mod4a:     DirectIndirectIndexed1
8523 lbl11mod4b:     ORA16
8524                         NEXTOPCODE
8525 Op12M0mod4:
8526 lbl12mod4a:     DirectIndirect
8527 lbl12mod4b:     ORA16
8528                         NEXTOPCODE
8529 Op13M0mod4:
8530 lbl13mod4a:     StackasmRelativeIndirectIndexed1
8531 lbl13mod4b:     ORA16
8532                         NEXTOPCODE
8533 Op14M0mod4:
8534 lbl14mod4a:     Direct
8535 lbl14mod4b:     TRB16
8536                         NEXTOPCODE
8537 Op15M0mod4:
8538 lbl15mod4a:     DirectIndexedX1
8539 lbl15mod4b:     ORA16
8540                         NEXTOPCODE
8541 Op16M0mod4:
8542 lbl16mod4a:     DirectIndexedX1
8543 lbl16mod4b:     ASL16
8544                         NEXTOPCODE
8545 Op17M0mod4:
8546 lbl17mod4a:     DirectIndirectIndexedLong1
8547 lbl17mod4b:     ORA16
8548                         NEXTOPCODE
8549 Op18mod4:
8550 lbl18mod4:      Op18
8551                         NEXTOPCODE
8552 Op19M0mod4:
8553 lbl19mod4a:     AbsoluteIndexedY1
8554 lbl19mod4b:     ORA16
8555                         NEXTOPCODE
8556 Op1AM0mod4:
8557 lbl1Amod4a:     A_INC16
8558                         NEXTOPCODE
8559 Op1Bmod4:
8560 lbl1Bmod4:      Op1BM0
8561                         NEXTOPCODE
8562 Op1CM0mod4:
8563 lbl1Cmod4a:     Absolute
8564 lbl1Cmod4b:     TRB16
8565                         NEXTOPCODE
8566 Op1DM0mod4:
8567 lbl1Dmod4a:     AbsoluteIndexedX1
8568 lbl1Dmod4b:     ORA16
8569                         NEXTOPCODE
8570 Op1EM0mod4:
8571 lbl1Emod4a:     AbsoluteIndexedX1
8572 lbl1Emod4b:     ASL16
8573                         NEXTOPCODE
8574 Op1FM0mod4:
8575 lbl1Fmod4a:     AbsoluteLongIndexedX1
8576 lbl1Fmod4b:     ORA16
8577                         NEXTOPCODE
8578 Op20mod4:
8579 lbl20mod4:      Op20
8580                         NEXTOPCODE
8581 Op21M0mod4:
8582 lbl21mod4a:     DirectIndexedIndirect1
8583 lbl21mod4b:     AND16
8584                         NEXTOPCODE
8585 Op22mod4:
8586 lbl22mod4:      Op22
8587                         NEXTOPCODE
8588 Op23M0mod4:
8589 lbl23mod4a:     StackasmRelative
8590 lbl23mod4b:     AND16
8591                         NEXTOPCODE
8592 Op24M0mod4:
8593 lbl24mod4a:     Direct
8594 lbl24mod4b:     BIT16
8595                         NEXTOPCODE
8596 Op25M0mod4:
8597 lbl25mod4a:     Direct
8598 lbl25mod4b:     AND16
8599                         NEXTOPCODE
8600 Op26M0mod4:
8601 lbl26mod4a:     Direct
8602 lbl26mod4b:     ROL16
8603                         NEXTOPCODE
8604 Op27M0mod4:
8605 lbl27mod4a:     DirectIndirectLong
8606 lbl27mod4b:     AND16
8607                         NEXTOPCODE
8608 Op28mod4:
8609 lbl28mod4:      Op28X1M0
8610                         NEXTOPCODE
8611 .pool
8612 Op29M0mod4:
8613 lbl29mod4:      Op29M0
8614                         NEXTOPCODE
8615 Op2AM0mod4:
8616 lbl2Amod4a:     A_ROL16
8617                         NEXTOPCODE
8618 Op2Bmod4:
8619 lbl2Bmod4:      Op2B
8620                         NEXTOPCODE
8621 Op2CM0mod4:
8622 lbl2Cmod4a:     Absolute
8623 lbl2Cmod4b:     BIT16
8624                         NEXTOPCODE
8625 Op2DM0mod4:
8626 lbl2Dmod4a:     Absolute
8627 lbl2Dmod4b:     AND16
8628                         NEXTOPCODE
8629 Op2EM0mod4:
8630 lbl2Emod4a:     Absolute
8631 lbl2Emod4b:     ROL16
8632                         NEXTOPCODE
8633 Op2FM0mod4:
8634 lbl2Fmod4a:     AbsoluteLong
8635 lbl2Fmod4b:     AND16
8636                         NEXTOPCODE
8637 Op30mod4:
8638 lbl30mod4:      Op30
8639                         NEXTOPCODE
8640 Op31M0mod4:
8641 lbl31mod4a:     DirectIndirectIndexed1
8642 lbl31mod4b:     AND16
8643                         NEXTOPCODE
8644 Op32M0mod4:
8645 lbl32mod4a:     DirectIndirect
8646 lbl32mod4b:     AND16
8647                         NEXTOPCODE
8648 Op33M0mod4:
8649 lbl33mod4a:     StackasmRelativeIndirectIndexed1
8650 lbl33mod4b:     AND16
8651                         NEXTOPCODE
8652 Op34M0mod4:
8653 lbl34mod4a:     DirectIndexedX1
8654 lbl34mod4b:     BIT16
8655                         NEXTOPCODE
8656 Op35M0mod4:
8657 lbl35mod4a:     DirectIndexedX1
8658 lbl35mod4b:     AND16
8659                         NEXTOPCODE
8660 Op36M0mod4:
8661 lbl36mod4a:     DirectIndexedX1
8662 lbl36mod4b:     ROL16
8663                         NEXTOPCODE
8664 Op37M0mod4:
8665 lbl37mod4a:     DirectIndirectIndexedLong1
8666 lbl37mod4b:     AND16
8667                         NEXTOPCODE
8668 Op38mod4:
8669 lbl38mod4:      Op38
8670                         NEXTOPCODE
8671 Op39M0mod4:
8672 lbl39mod4a:     AbsoluteIndexedY1
8673 lbl39mod4b:     AND16
8674                         NEXTOPCODE
8675 Op3AM0mod4:
8676 lbl3Amod4a:     A_DEC16
8677                         NEXTOPCODE
8678 Op3Bmod4:
8679 lbl3Bmod4:      Op3BM0
8680                         NEXTOPCODE
8681 Op3CM0mod4:
8682 lbl3Cmod4a:     AbsoluteIndexedX1
8683 lbl3Cmod4b:     BIT16
8684                         NEXTOPCODE
8685 Op3DM0mod4:
8686 lbl3Dmod4a:     AbsoluteIndexedX1
8687 lbl3Dmod4b:     AND16
8688                         NEXTOPCODE
8689 Op3EM0mod4:
8690 lbl3Emod4a:     AbsoluteIndexedX1
8691 lbl3Emod4b:     ROL16
8692                         NEXTOPCODE
8693 Op3FM0mod4:
8694 lbl3Fmod4a:     AbsoluteLongIndexedX1
8695 lbl3Fmod4b:     AND16
8696                         NEXTOPCODE
8697 Op40mod4:
8698 lbl40mod4:      Op40X1M0
8699                         NEXTOPCODE
8700 .pool
8701 Op41M0mod4:
8702 lbl41mod4a:     DirectIndexedIndirect1
8703 lbl41mod4b:     EOR16
8704                         NEXTOPCODE
8705 Op42mod4:
8706 lbl42mod4:      Op42
8707                         NEXTOPCODE
8708 Op43M0mod4:
8709 lbl43mod4a:     StackasmRelative
8710 lbl43mod4b:     EOR16
8711                         NEXTOPCODE
8712 Op44X1mod4:
8713 lbl44mod4:      Op44X1M0
8714                         NEXTOPCODE
8715 Op45M0mod4:
8716 lbl45mod4a:     Direct
8717 lbl45mod4b:     EOR16
8718                         NEXTOPCODE
8719 Op46M0mod4:
8720 lbl46mod4a:     Direct
8721 lbl46mod4b:     LSR16
8722                         NEXTOPCODE
8723 Op47M0mod4:
8724 lbl47mod4a:     DirectIndirectLong
8725 lbl47mod4b:     EOR16
8726                         NEXTOPCODE
8727 Op48M0mod4:
8728 lbl48mod4:      Op48M0
8729                         NEXTOPCODE
8730 Op49M0mod4:
8731 lbl49mod4:      Op49M0
8732                         NEXTOPCODE
8733 Op4AM0mod4:
8734 lbl4Amod4a:     A_LSR16
8735                         NEXTOPCODE
8736 Op4Bmod4:
8737 lbl4Bmod4:      Op4B
8738                         NEXTOPCODE
8739 Op4Cmod4:
8740 lbl4Cmod4:      Op4C
8741                         NEXTOPCODE
8742 Op4DM0mod4:
8743 lbl4Dmod4a:     Absolute
8744 lbl4Dmod4b:     EOR16
8745                         NEXTOPCODE
8746 Op4EM0mod4:
8747 lbl4Emod4a:     Absolute
8748 lbl4Emod4b:     LSR16
8749                         NEXTOPCODE
8750 Op4FM0mod4:
8751 lbl4Fmod4a:     AbsoluteLong
8752 lbl4Fmod4b:     EOR16
8753                         NEXTOPCODE
8754 Op50mod4:
8755 lbl50mod4:      Op50
8756                         NEXTOPCODE
8757 Op51M0mod4:
8758 lbl51mod4a:     DirectIndirectIndexed1
8759 lbl51mod4b:     EOR16
8760                         NEXTOPCODE
8761 Op52M0mod4:
8762 lbl52mod4a:     DirectIndirect
8763 lbl52mod4b:     EOR16
8764                         NEXTOPCODE
8765 Op53M0mod4:
8766 lbl53mod4a:     StackasmRelativeIndirectIndexed1
8767 lbl53mod4b:     EOR16
8768                         NEXTOPCODE
8769 Op54X1mod4:
8770 lbl54mod4:      Op54X1M0
8771                         NEXTOPCODE
8772 Op55M0mod4:
8773 lbl55mod4a:     DirectIndexedX1
8774 lbl55mod4b:     EOR16
8775                         NEXTOPCODE
8776 Op56M0mod4:
8777 lbl56mod4a:     DirectIndexedX1
8778 lbl56mod4b:     LSR16
8779                         NEXTOPCODE
8780 Op57M0mod4:
8781 lbl57mod4a:     DirectIndirectIndexedLong1
8782 lbl57mod4b:     EOR16
8783                         NEXTOPCODE
8784 Op58mod4:
8785 lbl58mod4:      Op58
8786                         NEXTOPCODE
8787 Op59M0mod4:
8788 lbl59mod4a:     AbsoluteIndexedY1
8789 lbl59mod4b:     EOR16
8790                         NEXTOPCODE
8791 Op5AX1mod4:
8792 lbl5Amod4:      Op5AX1
8793                         NEXTOPCODE
8794 Op5Bmod4:
8795 lbl5Bmod4:      Op5BM0
8796                         NEXTOPCODE
8797 Op5Cmod4:
8798 lbl5Cmod4:      Op5C
8799                         NEXTOPCODE
8800 Op5DM0mod4:
8801 lbl5Dmod4a:     AbsoluteIndexedX1
8802 lbl5Dmod4b:     EOR16
8803                         NEXTOPCODE
8804 Op5EM0mod4:
8805 lbl5Emod4a:     AbsoluteIndexedX1
8806 lbl5Emod4b:     LSR16
8807                         NEXTOPCODE
8808 Op5FM0mod4:
8809 lbl5Fmod4a:     AbsoluteLongIndexedX1
8810 lbl5Fmod4b:     EOR16
8811                         NEXTOPCODE
8812 Op60mod4:
8813 lbl60mod4:      Op60
8814                         NEXTOPCODE
8815 Op61M0mod4:
8816 lbl61mod4a:     DirectIndexedIndirect1
8817 lbl61mod4b:     ADC16
8818                         NEXTOPCODE
8819 Op62mod4:
8820 lbl62mod4:      Op62
8821                         NEXTOPCODE
8822 Op63M0mod4:
8823 lbl63mod4a:     StackasmRelative
8824 lbl63mod4b:     ADC16
8825                         NEXTOPCODE
8826 .pool
8827 Op64M0mod4:
8828 lbl64mod4a:     Direct
8829 lbl64mod4b:     STZ16
8830                         NEXTOPCODE
8831 Op65M0mod4:
8832 lbl65mod4a:     Direct
8833 lbl65mod4b:     ADC16
8834                         NEXTOPCODE
8835 .pool
8836 Op66M0mod4:
8837 lbl66mod4a:     Direct
8838 lbl66mod4b:     ROR16
8839                         NEXTOPCODE
8840 Op67M0mod4:
8841 lbl67mod4a:     DirectIndirectLong
8842 lbl67mod4b:     ADC16
8843                         NEXTOPCODE
8844 .pool
8845 Op68M0mod4:
8846 lbl68mod4:      Op68M0
8847                         NEXTOPCODE
8848 Op69M0mod4:
8849 lbl69mod4a:     Immediate16
8850 lbl69mod4b:     ADC16
8851                         NEXTOPCODE
8852 .pool
8853 Op6AM0mod4:
8854 lbl6Amod4a:     A_ROR16
8855                         NEXTOPCODE
8856 Op6Bmod4:
8857 lbl6Bmod4:      Op6B
8858                         NEXTOPCODE
8859 Op6Cmod4:
8860 lbl6Cmod4:      Op6C
8861                         NEXTOPCODE
8862 Op6DM0mod4:
8863 lbl6Dmod4a:     Absolute
8864 lbl6Dmod4b:     ADC16
8865                         NEXTOPCODE
8866 Op6EM0mod4:
8867 lbl6Emod4a:     Absolute
8868 lbl6Emod4b:     ROR16
8869                         NEXTOPCODE
8870 Op6FM0mod4:
8871 lbl6Fmod4a:     AbsoluteLong
8872 lbl6Fmod4b:     ADC16
8873                         NEXTOPCODE
8874 Op70mod4:
8875 lbl70mod4:      Op70
8876                         NEXTOPCODE
8877 Op71M0mod4:
8878 lbl71mod4a:     DirectIndirectIndexed1
8879 lbl71mod4b:     ADC16
8880                         NEXTOPCODE
8881 Op72M0mod4:
8882 lbl72mod4a:     DirectIndirect
8883 lbl72mod4b:     ADC16
8884                         NEXTOPCODE
8885 Op73M0mod4:
8886 lbl73mod4a:     StackasmRelativeIndirectIndexed1
8887 lbl73mod4b:     ADC16
8888                         NEXTOPCODE
8889 .pool
8890 Op74M0mod4:
8891 lbl74mod4a:     DirectIndexedX1
8892 lbl74mod4b:     STZ16
8893                         NEXTOPCODE
8894 Op75M0mod4:
8895 lbl75mod4a:     DirectIndexedX1
8896 lbl75mod4b:     ADC16
8897                         NEXTOPCODE
8898 .pool
8899 Op76M0mod4:
8900 lbl76mod4a:     DirectIndexedX1
8901 lbl76mod4b:     ROR16
8902                         NEXTOPCODE
8903 Op77M0mod4:
8904 lbl77mod4a:     DirectIndirectIndexedLong1
8905 lbl77mod4b:     ADC16
8906                         NEXTOPCODE
8907 Op78mod4:
8908 lbl78mod4:      Op78
8909                         NEXTOPCODE
8910 Op79M0mod4:
8911 lbl79mod4a:     AbsoluteIndexedY1
8912 lbl79mod4b:     ADC16
8913                         NEXTOPCODE
8914 Op7AX1mod4:
8915 lbl7Amod4:      Op7AX1
8916                         NEXTOPCODE
8917 Op7Bmod4:
8918 lbl7Bmod4:      Op7BM0
8919                         NEXTOPCODE
8920 Op7Cmod4:
8921 lbl7Cmod4:      AbsoluteIndexedIndirectX1
8922                 Op7C
8923                         NEXTOPCODE
8924 Op7DM0mod4:
8925 lbl7Dmod4a:     AbsoluteIndexedX1
8926 lbl7Dmod4b:     ADC16
8927                         NEXTOPCODE
8928 Op7EM0mod4:
8929 lbl7Emod4a:     AbsoluteIndexedX1
8930 lbl7Emod4b:     ROR16
8931                         NEXTOPCODE
8932 Op7FM0mod4:
8933 lbl7Fmod4a:     AbsoluteLongIndexedX1
8934 lbl7Fmod4b:     ADC16
8935                         NEXTOPCODE
8936 .pool
8937 Op80mod4:
8938 lbl80mod4:      Op80
8939                         NEXTOPCODE
8940 Op81M0mod4:
8941 lbl81mod4a:     DirectIndexedIndirect1
8942 lbl81mod4b:     Op81M0
8943                         NEXTOPCODE
8944 Op82mod4:
8945 lbl82mod4:      Op82
8946                         NEXTOPCODE
8947 Op83M0mod4:
8948 lbl83mod4a:     StackasmRelative
8949 lbl83mod4b:     STA16
8950                         NEXTOPCODE
8951 Op84X1mod4:
8952 lbl84mod4a:     Direct
8953 lbl84mod4b:     STY8
8954                         NEXTOPCODE
8955 Op85M0mod4:
8956 lbl85mod4a:     Direct
8957 lbl85mod4b:     STA16
8958                         NEXTOPCODE
8959 Op86X1mod4:
8960 lbl86mod4a:     Direct
8961 lbl86mod4b:     STX8
8962                         NEXTOPCODE
8963 Op87M0mod4:
8964 lbl87mod4a:     DirectIndirectLong
8965 lbl87mod4b:     STA16
8966                         NEXTOPCODE
8967 Op88X1mod4:
8968 lbl88mod4:      Op88X1
8969                         NEXTOPCODE
8970 Op89M0mod4:
8971 lbl89mod4:      Op89M0
8972                         NEXTOPCODE
8973 Op8AM0mod4:
8974 lbl8Amod4:      Op8AM0X1
8975                         NEXTOPCODE
8976 Op8Bmod4:
8977 lbl8Bmod4:      Op8B
8978                         NEXTOPCODE
8979 Op8CX1mod4:
8980 lbl8Cmod4a:     Absolute
8981 lbl8Cmod4b:     STY8
8982                         NEXTOPCODE
8983 Op8DM0mod4:
8984 lbl8Dmod4a:     Absolute
8985 lbl8Dmod4b:     STA16
8986                         NEXTOPCODE
8987 Op8EX1mod4:
8988 lbl8Emod4a:     Absolute
8989 lbl8Emod4b:     STX8
8990                         NEXTOPCODE
8991 Op8FM0mod4:
8992 lbl8Fmod4a:     AbsoluteLong
8993 lbl8Fmod4b:     STA16
8994                         NEXTOPCODE
8995 Op90mod4:
8996 lbl90mod4:      Op90
8997                         NEXTOPCODE
8998 Op91M0mod4:
8999 lbl91mod4a:     DirectIndirectIndexed1
9000 lbl91mod4b:     STA16
9001                         NEXTOPCODE
9002 Op92M0mod4:
9003 lbl92mod4a:     DirectIndirect
9004 lbl92mod4b:     STA16
9005                         NEXTOPCODE
9006 Op93M0mod4:
9007 lbl93mod4a:     StackasmRelativeIndirectIndexed1
9008 lbl93mod4b:     STA16
9009                         NEXTOPCODE
9010 Op94X1mod4:
9011 lbl94mod4a:     DirectIndexedX1
9012 lbl94mod4b:     STY8
9013                         NEXTOPCODE
9014 Op95M0mod4:
9015 lbl95mod4a:     DirectIndexedX1
9016 lbl95mod4b:     STA16
9017                         NEXTOPCODE
9018 Op96X1mod4:
9019 lbl96mod4a:     DirectIndexedY1
9020 lbl96mod4b:     STX8
9021                         NEXTOPCODE
9022 Op97M0mod4:
9023 lbl97mod4a:     DirectIndirectIndexedLong1
9024 lbl97mod4b:     STA16
9025                         NEXTOPCODE
9026 Op98M0mod4:
9027 lbl98mod4:      Op98M0X1
9028                         NEXTOPCODE
9029 Op99M0mod4:
9030 lbl99mod4a:     AbsoluteIndexedY1
9031 lbl99mod4b:     STA16
9032                         NEXTOPCODE
9033 Op9Amod4:
9034 lbl9Amod4:      Op9AX1
9035                         NEXTOPCODE
9036 Op9BX1mod4:
9037 lbl9Bmod4:      Op9BX1
9038                         NEXTOPCODE
9039 Op9CM0mod4:
9040 lbl9Cmod4a:     Absolute
9041 lbl9Cmod4b:     STZ16
9042                         NEXTOPCODE
9043 Op9DM0mod4:
9044 lbl9Dmod4a:     AbsoluteIndexedX1
9045 lbl9Dmod4b:     STA16
9046                         NEXTOPCODE
9047 Op9EM0mod4:
9048 lbl9Emod4:      AbsoluteIndexedX1
9049                 STZ16
9050                         NEXTOPCODE
9051 Op9FM0mod4:
9052 lbl9Fmod4a:     AbsoluteLongIndexedX1
9053 lbl9Fmod4b:     STA16
9054                         NEXTOPCODE
9055 OpA0X1mod4:
9056 lblA0mod4:      OpA0X1
9057                         NEXTOPCODE
9058 OpA1M0mod4:
9059 lblA1mod4a:     DirectIndexedIndirect1
9060 lblA1mod4b:     LDA16
9061                         NEXTOPCODE
9062 OpA2X1mod4:
9063 lblA2mod4:      OpA2X1
9064                         NEXTOPCODE
9065 OpA3M0mod4:
9066 lblA3mod4a:     StackasmRelative
9067 lblA3mod4b:     LDA16
9068                         NEXTOPCODE
9069 OpA4X1mod4:
9070 lblA4mod4a:     Direct
9071 lblA4mod4b:     LDY8
9072                         NEXTOPCODE
9073 OpA5M0mod4:
9074 lblA5mod4a:     Direct
9075 lblA5mod4b:     LDA16
9076                         NEXTOPCODE
9077 OpA6X1mod4:
9078 lblA6mod4a:     Direct
9079 lblA6mod4b:     LDX8
9080                         NEXTOPCODE
9081 OpA7M0mod4:
9082 lblA7mod4a:     DirectIndirectLong
9083 lblA7mod4b:     LDA16
9084                         NEXTOPCODE
9085 OpA8X1mod4:
9086 lblA8mod4:      OpA8X1M0
9087                         NEXTOPCODE
9088 OpA9M0mod4:
9089 lblA9mod4:      OpA9M0
9090                         NEXTOPCODE
9091 OpAAX1mod4:
9092 lblAAmod4:      OpAAX1M0
9093                         NEXTOPCODE
9094 OpABmod4:
9095 lblABmod4:      OpAB
9096                         NEXTOPCODE
9097 OpACX1mod4:
9098 lblACmod4a:     Absolute
9099 lblACmod4b:     LDY8
9100                         NEXTOPCODE
9101 OpADM0mod4:
9102 lblADmod4a:     Absolute
9103 lblADmod4b:     LDA16
9104                         NEXTOPCODE
9105 OpAEX1mod4:
9106 lblAEmod4a:     Absolute
9107 lblAEmod4b:     LDX8
9108                         NEXTOPCODE
9109 OpAFM0mod4:
9110 lblAFmod4a:     AbsoluteLong
9111 lblAFmod4b:     LDA16
9112                         NEXTOPCODE
9113 OpB0mod4:
9114 lblB0mod4:      OpB0
9115                         NEXTOPCODE
9116 OpB1M0mod4:
9117 lblB1mod4a:     DirectIndirectIndexed1
9118 lblB1mod4b:     LDA16
9119                         NEXTOPCODE
9120 OpB2M0mod4:
9121 lblB2mod4a:     DirectIndirect
9122 lblB2mod4b:     LDA16
9123                         NEXTOPCODE
9124 OpB3M0mod4:
9125 lblB3mod4a:     StackasmRelativeIndirectIndexed1
9126 lblB3mod4b:     LDA16
9127                         NEXTOPCODE
9128 OpB4X1mod4:
9129 lblB4mod4a:     DirectIndexedX1
9130 lblB4mod4b:     LDY8
9131                         NEXTOPCODE
9132 OpB5M0mod4:
9133 lblB5mod4a:     DirectIndexedX1
9134 lblB5mod4b:     LDA16
9135                         NEXTOPCODE
9136 OpB6X1mod4:
9137 lblB6mod4a:     DirectIndexedY1
9138 lblB6mod4b:     LDX8
9139                         NEXTOPCODE
9140 OpB7M0mod4:
9141 lblB7mod4a:     DirectIndirectIndexedLong1
9142 lblB7mod4b:     LDA16
9143                         NEXTOPCODE
9144 OpB8mod4:
9145 lblB8mod4:      OpB8
9146                         NEXTOPCODE
9147 OpB9M0mod4:
9148 lblB9mod4a:     AbsoluteIndexedY1
9149 lblB9mod4b:     LDA16
9150                         NEXTOPCODE
9151 OpBAX1mod4:
9152 lblBAmod4:      OpBAX1
9153                         NEXTOPCODE
9154 OpBBX1mod4:
9155 lblBBmod4:      OpBBX1
9156                         NEXTOPCODE
9157 OpBCX1mod4:
9158 lblBCmod4a:     AbsoluteIndexedX1
9159 lblBCmod4b:     LDY8
9160                         NEXTOPCODE
9161 OpBDM0mod4:
9162 lblBDmod4a:     AbsoluteIndexedX1
9163 lblBDmod4b:     LDA16
9164                         NEXTOPCODE
9165 OpBEX1mod4:
9166 lblBEmod4a:     AbsoluteIndexedY1
9167 lblBEmod4b:     LDX8
9168                         NEXTOPCODE
9169 OpBFM0mod4:
9170 lblBFmod4a:     AbsoluteLongIndexedX1
9171 lblBFmod4b:     LDA16
9172                         NEXTOPCODE
9173 OpC0X1mod4:
9174 lblC0mod4:      OpC0X1
9175                         NEXTOPCODE
9176 OpC1M0mod4:
9177 lblC1mod4a:     DirectIndexedIndirect1
9178 lblC1mod4b:     CMP16
9179                         NEXTOPCODE
9180 OpC2mod4:
9181 lblC2mod4:      OpC2
9182                         NEXTOPCODE
9183 .pool
9184 OpC3M0mod4:
9185 lblC3mod4a:     StackasmRelative
9186 lblC3mod4b:     CMP16
9187                         NEXTOPCODE
9188 OpC4X1mod4:
9189 lblC4mod4a:     Direct
9190 lblC4mod4b:     CMY8
9191                         NEXTOPCODE
9192 OpC5M0mod4:
9193 lblC5mod4a:     Direct
9194 lblC5mod4b:     CMP16
9195                         NEXTOPCODE
9196 OpC6M0mod4:
9197 lblC6mod4a:     Direct
9198 lblC6mod4b:     DEC16
9199                         NEXTOPCODE
9200 OpC7M0mod4:
9201 lblC7mod4a:     DirectIndirectLong
9202 lblC7mod4b:     CMP16
9203                         NEXTOPCODE
9204 OpC8X1mod4:
9205 lblC8mod4:      OpC8X1
9206                         NEXTOPCODE
9207 OpC9M0mod4:
9208 lblC9mod4:      OpC9M0
9209                         NEXTOPCODE
9210 OpCAX1mod4:
9211 lblCAmod4:      OpCAX1
9212                         NEXTOPCODE
9213 OpCBmod4:
9214 lblCBmod4:      OpCB
9215                         NEXTOPCODE
9216 OpCCX1mod4:
9217 lblCCmod4a:     Absolute
9218 lblCCmod4b:     CMY8
9219                         NEXTOPCODE
9220 OpCDM0mod4:
9221 lblCDmod4a:     Absolute
9222 lblCDmod4b:     CMP16
9223                         NEXTOPCODE
9224 OpCEM0mod4:
9225 lblCEmod4a:     Absolute
9226 lblCEmod4b:     DEC16
9227                         NEXTOPCODE
9228 OpCFM0mod4:
9229 lblCFmod4a:     AbsoluteLong
9230 lblCFmod4b:     CMP16
9231                         NEXTOPCODE
9232 OpD0mod4:
9233 lblD0mod4:      OpD0
9234                         NEXTOPCODE
9235 OpD1M0mod4:
9236 lblD1mod4a:     DirectIndirectIndexed1
9237 lblD1mod4b:     CMP16
9238                         NEXTOPCODE
9239 OpD2M0mod4:
9240 lblD2mod4a:     DirectIndirect
9241 lblD2mod4b:     CMP16
9242                         NEXTOPCODE
9243 OpD3M0mod4:
9244 lblD3mod4a:     StackasmRelativeIndirectIndexed1
9245 lblD3mod4b:     CMP16
9246                         NEXTOPCODE
9247 OpD4mod4:
9248 lblD4mod4:      OpD4
9249                         NEXTOPCODE
9250 OpD5M0mod4:
9251 lblD5mod4a:     DirectIndexedX1
9252 lblD5mod4b:     CMP16
9253                         NEXTOPCODE
9254 OpD6M0mod4:
9255 lblD6mod4a:     DirectIndexedX1
9256 lblD6mod4b:     DEC16
9257                         NEXTOPCODE
9258 OpD7M0mod4:
9259 lblD7mod4a:     DirectIndirectIndexedLong1
9260 lblD7mod4b:     CMP16
9261                         NEXTOPCODE
9262 OpD8mod4:
9263 lblD8mod4:      OpD8
9264                         NEXTOPCODE
9265 OpD9M0mod4:
9266 lblD9mod4a:     AbsoluteIndexedY1
9267 lblD9mod4b:     CMP16
9268                         NEXTOPCODE
9269 OpDAX1mod4:
9270 lblDAmod4:      OpDAX1
9271                         NEXTOPCODE
9272 OpDBmod4:
9273 lblDBmod4:      OpDB
9274                         NEXTOPCODE
9275 OpDCmod4:
9276 lblDCmod4:      OpDC
9277                         NEXTOPCODE
9278 OpDDM0mod4:
9279 lblDDmod4a:     AbsoluteIndexedX1
9280 lblDDmod4b:     CMP16
9281                         NEXTOPCODE
9282 OpDEM0mod4:
9283 lblDEmod4a:     AbsoluteIndexedX1
9284 lblDEmod4b:     DEC16
9285                         NEXTOPCODE
9286 OpDFM0mod4:
9287 lblDFmod4a:     AbsoluteLongIndexedX1
9288 lblDFmod4b:     CMP16
9289                         NEXTOPCODE
9290 OpE0X1mod4:
9291 lblE0mod4:      OpE0X1
9292                         NEXTOPCODE
9293 OpE1M0mod4:
9294 lblE1mod4a:     DirectIndexedIndirect1
9295 lblE1mod4b:     SBC16
9296                         NEXTOPCODE
9297 OpE2mod4:
9298 lblE2mod4:      OpE2
9299                         NEXTOPCODE
9300 .pool
9301 OpE3M0mod4:
9302 lblE3mod4a:     StackasmRelative
9303 lblE3mod4b:     SBC16
9304                         NEXTOPCODE
9305 OpE4X1mod4:
9306 lblE4mod4a:     Direct
9307 lblE4mod4b:     CMX8
9308                         NEXTOPCODE
9309 OpE5M0mod4:
9310 lblE5mod4a:     Direct
9311 lblE5mod4b:     SBC16
9312                         NEXTOPCODE
9313 OpE6M0mod4:
9314 lblE6mod4a:     Direct
9315 lblE6mod4b:     INC16
9316                         NEXTOPCODE
9317 OpE7M0mod4:
9318 lblE7mod4a:     DirectIndirectLong
9319 lblE7mod4b:     SBC16
9320                         NEXTOPCODE
9321 OpE8X1mod4:
9322 lblE8mod4:      OpE8X1
9323                         NEXTOPCODE
9324 OpE9M0mod4:
9325 lblE9mod4a:     Immediate16
9326 lblE9mod4b:     SBC16
9327                         NEXTOPCODE
9328 OpEAmod4:
9329 lblEAmod4:      OpEA
9330                         NEXTOPCODE
9331 OpEBmod4:
9332 lblEBmod4:      OpEBM0
9333                         NEXTOPCODE
9334 OpECX1mod4:
9335 lblECmod4a:     Absolute
9336 lblECmod4b:     CMX8
9337                         NEXTOPCODE
9338 OpEDM0mod4:
9339 lblEDmod4a:     Absolute
9340 lblEDmod4b:     SBC16
9341                         NEXTOPCODE
9342 OpEEM0mod4:
9343 lblEEmod4a:     Absolute
9344 lblEEmod4b:     INC16
9345                         NEXTOPCODE
9346 OpEFM0mod4:
9347 lblEFmod4a:     AbsoluteLong
9348 lblEFmod4b:     SBC16
9349                         NEXTOPCODE
9350 OpF0mod4:
9351 lblF0mod4:      OpF0
9352                         NEXTOPCODE
9353 OpF1M0mod4:
9354 lblF1mod4a:     DirectIndirectIndexed1
9355 lblF1mod4b:     SBC16
9356                         NEXTOPCODE
9357 OpF2M0mod4:
9358 lblF2mod4a:     DirectIndirect
9359 lblF2mod4b:     SBC16
9360                         NEXTOPCODE
9361 OpF3M0mod4:
9362 lblF3mod4a:     StackasmRelativeIndirectIndexed1
9363 lblF3mod4b:     SBC16
9364                         NEXTOPCODE
9365 OpF4mod4:
9366 lblF4mod4:      OpF4
9367                         NEXTOPCODE
9368 OpF5M0mod4:
9369 lblF5mod4a:     DirectIndexedX1
9370 lblF5mod4b:     SBC16
9371                         NEXTOPCODE
9372 OpF6M0mod4:
9373 lblF6mod4a:     DirectIndexedX1
9374 lblF6mod4b:     INC16
9375                         NEXTOPCODE
9376 OpF7M0mod4:
9377 lblF7mod4a:     DirectIndirectIndexedLong1
9378 lblF7mod4b:     SBC16
9379                         NEXTOPCODE
9380 OpF8mod4:
9381 lblF8mod4:      OpF8
9382                         NEXTOPCODE
9383 OpF9M0mod4:
9384 lblF9mod4a:     AbsoluteIndexedY1
9385 lblF9mod4b:     SBC16
9386                         NEXTOPCODE
9387 OpFAX1mod4:
9388 lblFAmod4:      OpFAX1
9389                         NEXTOPCODE
9390 OpFBmod4:
9391 lblFBmod4:      OpFB
9392                         NEXTOPCODE
9393 OpFCmod4:
9394 lblFCmod4:      OpFCX1
9395                         NEXTOPCODE
9396 OpFDM0mod4:
9397 lblFDmod4a:     AbsoluteIndexedX1
9398 lblFDmod4b:     SBC16
9399                         NEXTOPCODE
9400 OpFEM0mod4:
9401 lblFEmod4a:     AbsoluteIndexedX1
9402 lblFEmod4b:     INC16
9403                         NEXTOPCODE
9404 OpFFM0mod4:
9405 lblFFmod4a:     AbsoluteLongIndexedX1
9406 lblFFmod4b:     SBC16
9407                         NEXTOPCODE
9408
9409
9410                         .pool
9411