2 * vm86 linux syscall support
4 * Copyright (c) 2003 Fabrice Bellard
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #define set_flags(X,new,mask) \
32 ((X) = ((X) & ~(mask)) | ((new) & (mask)))
34 #define SAFE_MASK (0xDD5)
35 #define RETURN_MASK (0xDFF)
37 static inline int is_revectored(int nr, struct target_revectored_struct *bitmap)
39 return (tswap32(bitmap->__map[nr >> 5]) >> (nr & 0x1f)) & 1;
42 static inline void vm_putw(uint8_t *segptr, unsigned int reg16, unsigned int val)
44 *(uint16_t *)(segptr + (reg16 & 0xffff)) = tswap16(val);
47 static inline void vm_putl(uint8_t *segptr, unsigned int reg16, unsigned int val)
49 *(uint32_t *)(segptr + (reg16 & 0xffff)) = tswap32(val);
52 static inline unsigned int vm_getw(uint8_t *segptr, unsigned int reg16)
54 return tswap16(*(uint16_t *)(segptr + (reg16 & 0xffff)));
57 static inline unsigned int vm_getl(uint8_t *segptr, unsigned int reg16)
59 return tswap32(*(uint16_t *)(segptr + (reg16 & 0xffff)));
62 void save_v86_state(CPUX86State *env)
64 TaskState *ts = env->opaque;
66 /* put the VM86 registers in the userspace register structure */
67 ts->target_v86->regs.eax = tswap32(env->regs[R_EAX]);
68 ts->target_v86->regs.ebx = tswap32(env->regs[R_EBX]);
69 ts->target_v86->regs.ecx = tswap32(env->regs[R_ECX]);
70 ts->target_v86->regs.edx = tswap32(env->regs[R_EDX]);
71 ts->target_v86->regs.esi = tswap32(env->regs[R_ESI]);
72 ts->target_v86->regs.edi = tswap32(env->regs[R_EDI]);
73 ts->target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
74 ts->target_v86->regs.esp = tswap32(env->regs[R_ESP]);
75 ts->target_v86->regs.eip = tswap32(env->eip);
76 ts->target_v86->regs.cs = tswap16(env->segs[R_CS]);
77 ts->target_v86->regs.ss = tswap16(env->segs[R_SS]);
78 ts->target_v86->regs.ds = tswap16(env->segs[R_DS]);
79 ts->target_v86->regs.es = tswap16(env->segs[R_ES]);
80 ts->target_v86->regs.fs = tswap16(env->segs[R_FS]);
81 ts->target_v86->regs.gs = tswap16(env->segs[R_GS]);
82 set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
83 ts->target_v86->regs.eflags = tswap32(env->eflags);
85 fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
86 env->eflags, env->segs[R_CS], env->eip);
89 /* restore 32 bit registers */
90 env->regs[R_EAX] = ts->vm86_saved_regs.eax;
91 env->regs[R_EBX] = ts->vm86_saved_regs.ebx;
92 env->regs[R_ECX] = ts->vm86_saved_regs.ecx;
93 env->regs[R_EDX] = ts->vm86_saved_regs.edx;
94 env->regs[R_ESI] = ts->vm86_saved_regs.esi;
95 env->regs[R_EDI] = ts->vm86_saved_regs.edi;
96 env->regs[R_EBP] = ts->vm86_saved_regs.ebp;
97 env->regs[R_ESP] = ts->vm86_saved_regs.esp;
98 env->eflags = ts->vm86_saved_regs.eflags;
99 env->eip = ts->vm86_saved_regs.eip;
101 cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs);
102 cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss);
103 cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds);
104 cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es);
105 cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs);
106 cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs);
109 /* return from vm86 mode to 32 bit. The vm86() syscall will return
111 static inline void return_to_32bit(CPUX86State *env, int retval)
114 fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);
117 env->regs[R_EAX] = retval;
120 static inline int set_IF(CPUX86State *env)
122 TaskState *ts = env->opaque;
124 ts->v86flags |= VIF_MASK;
125 if (ts->v86flags & VIP_MASK) {
126 return_to_32bit(env, TARGET_VM86_STI);
132 static inline void clear_IF(CPUX86State *env)
134 TaskState *ts = env->opaque;
136 ts->v86flags &= ~VIF_MASK;
139 static inline void clear_TF(CPUX86State *env)
141 env->eflags &= ~TF_MASK;
144 static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
146 TaskState *ts = env->opaque;
148 set_flags(ts->v86flags, eflags, ts->v86mask);
149 set_flags(env->eflags, eflags, SAFE_MASK);
150 if (eflags & IF_MASK)
155 static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
157 TaskState *ts = env->opaque;
159 set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
160 set_flags(env->eflags, flags, SAFE_MASK);
166 static inline unsigned int get_vflags(CPUX86State *env)
168 TaskState *ts = env->opaque;
171 flags = env->eflags & RETURN_MASK;
172 if (ts->v86flags & VIF_MASK)
174 return flags | (ts->v86flags & ts->v86mask);
177 #define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff)
179 /* handle VM86 interrupt (NOTE: the CPU core currently does not
180 support TSS interrupt revectoring, so this code is always executed) */
181 static void do_int(CPUX86State *env, int intno)
183 TaskState *ts = env->opaque;
184 uint32_t *int_ptr, segoffs;
189 if (intno == 0xe6 && (env->regs[R_EAX] & 0xffff) == 0x00c0)
193 if (env->segs[R_CS] == TARGET_BIOSSEG)
195 if (is_revectored(intno, &ts->target_v86->int_revectored))
197 if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff,
198 &ts->target_v86->int21_revectored))
200 int_ptr = (uint32_t *)(intno << 2);
201 segoffs = tswap32(*int_ptr);
202 if ((segoffs >> 16) == TARGET_BIOSSEG)
204 #if defined(DEBUG_VM86)
205 fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
206 intno, segoffs >> 16, segoffs & 0xffff);
209 ssp = (uint8_t *)(env->segs[R_SS] << 4);
210 sp = env->regs[R_ESP] & 0xffff;
211 vm_putw(ssp, sp - 2, get_vflags(env));
212 vm_putw(ssp, sp - 4, env->segs[R_CS]);
213 vm_putw(ssp, sp - 6, env->eip);
214 ADD16(env->regs[R_ESP], -6);
215 /* goto interrupt handler */
216 env->eip = segoffs & 0xffff;
217 cpu_x86_load_seg(env, R_CS, segoffs >> 16);
222 #if defined(DEBUG_VM86)
223 fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);
225 return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
228 void handle_vm86_trap(CPUX86State *env, int trapno)
230 if (trapno == 1 || trapno == 3) {
231 return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
237 #define CHECK_IF_IN_TRAP(disp) \
238 if ((tswap32(ts->target_v86->vm86plus.flags) & TARGET_vm86dbg_active) && \
239 (tswap32(ts->target_v86->vm86plus.flags) & TARGET_vm86dbg_TFpendig)) \
240 vm_putw(ssp,sp + disp,vm_getw(ssp,sp + disp) | TF_MASK)
242 #define VM86_FAULT_RETURN \
243 if ((tswap32(ts->target_v86->vm86plus.flags) & TARGET_force_return_for_pic) && \
244 (ts->v86flags & (IF_MASK | VIF_MASK))) \
245 return_to_32bit(env, TARGET_VM86_PICRETURN); \
248 void handle_vm86_fault(CPUX86State *env)
250 TaskState *ts = env->opaque;
251 uint8_t *csp, *pc, *ssp;
254 csp = (uint8_t *)(env->segs[R_CS] << 4);
255 ip = env->eip & 0xffff;
258 ssp = (uint8_t *)(env->segs[R_SS] << 4);
259 sp = env->regs[R_ESP] & 0xffff;
261 #if defined(DEBUG_VM86)
262 fprintf(logfile, "VM86 exception %04x:%08x %02x %02x\n",
263 env->segs[R_CS], env->eip, pc[0], pc[1]);
270 case 0x9c: /* pushfd */
272 ADD16(env->regs[R_ESP], -4);
273 vm_putl(ssp, sp - 4, get_vflags(env));
276 case 0x9d: /* popfd */
278 ADD16(env->regs[R_ESP], 4);
280 if (set_vflags_long(vm_getl(ssp, sp), env))
284 case 0xcf: /* iretd */
285 ADD16(env->regs[R_ESP], 12);
286 env->eip = vm_getl(ssp, sp) & 0xffff;
287 cpu_x86_load_seg(env, R_CS, vm_getl(ssp, sp + 4) & 0xffff);
289 if (set_vflags_long(vm_getl(ssp, sp + 8), env))
297 case 0x9c: /* pushf */
299 ADD16(env->regs[R_ESP], -2);
300 vm_putw(ssp, sp - 2, get_vflags(env));
303 case 0x9d: /* popf */
305 ADD16(env->regs[R_ESP], 2);
307 if (set_vflags_short(vm_getw(ssp, sp), env))
316 case 0xcf: /* iret */
317 ADD16(env->regs[R_ESP], 6);
318 env->eip = vm_getw(ssp, sp);
319 cpu_x86_load_seg(env, R_CS, vm_getw(ssp, sp + 2));
321 if (set_vflags_short(vm_getw(ssp, sp + 4), env))
338 /* real VM86 GPF exception */
339 return_to_32bit(env, TARGET_VM86_UNKNOWN);
344 int do_vm86(CPUX86State *env, long subfunction,
345 struct target_vm86plus_struct * target_v86)
347 TaskState *ts = env->opaque;
350 switch (subfunction) {
351 case TARGET_VM86_REQUEST_IRQ:
352 case TARGET_VM86_FREE_IRQ:
353 case TARGET_VM86_GET_IRQ_BITS:
354 case TARGET_VM86_GET_AND_RESET_IRQ:
355 gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
358 case TARGET_VM86_PLUS_INSTALL_CHECK:
359 /* NOTE: on old vm86 stuff this will return the error
360 from verify_area(), because the subfunction is
361 interpreted as (invalid) address to vm86_struct.
362 So the installation check works.
368 ts->target_v86 = target_v86;
369 /* save current CPU regs */
370 ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */
371 ts->vm86_saved_regs.ebx = env->regs[R_EBX];
372 ts->vm86_saved_regs.ecx = env->regs[R_ECX];
373 ts->vm86_saved_regs.edx = env->regs[R_EDX];
374 ts->vm86_saved_regs.esi = env->regs[R_ESI];
375 ts->vm86_saved_regs.edi = env->regs[R_EDI];
376 ts->vm86_saved_regs.ebp = env->regs[R_EBP];
377 ts->vm86_saved_regs.esp = env->regs[R_ESP];
378 ts->vm86_saved_regs.eflags = env->eflags;
379 ts->vm86_saved_regs.eip = env->eip;
380 ts->vm86_saved_regs.cs = env->segs[R_CS];
381 ts->vm86_saved_regs.ss = env->segs[R_SS];
382 ts->vm86_saved_regs.ds = env->segs[R_DS];
383 ts->vm86_saved_regs.es = env->segs[R_ES];
384 ts->vm86_saved_regs.fs = env->segs[R_FS];
385 ts->vm86_saved_regs.gs = env->segs[R_GS];
387 /* build vm86 CPU state */
388 ts->v86flags = tswap32(target_v86->regs.eflags);
389 env->eflags = (env->eflags & ~SAFE_MASK) |
390 (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK;
391 ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK;
393 env->regs[R_EBX] = tswap32(target_v86->regs.ebx);
394 env->regs[R_ECX] = tswap32(target_v86->regs.ecx);
395 env->regs[R_EDX] = tswap32(target_v86->regs.edx);
396 env->regs[R_ESI] = tswap32(target_v86->regs.esi);
397 env->regs[R_EDI] = tswap32(target_v86->regs.edi);
398 env->regs[R_EBP] = tswap32(target_v86->regs.ebp);
399 env->regs[R_ESP] = tswap32(target_v86->regs.esp);
400 env->eip = tswap32(target_v86->regs.eip);
401 cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs));
402 cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss));
403 cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds));
404 cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es));
405 cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs));
406 cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs));
407 ret = tswap32(target_v86->regs.eax); /* eax will be restored at
408 the end of the syscall */
410 fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n", env->segs[R_CS], env->eip);
412 /* now the virtual CPU is ready for vm86 execution ! */