4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 //#define DEBUG_VGA_MEM
29 //#define DEBUG_VGA_REG
31 //#define DEBUG_BOCHS_VBE
33 /* force some bits to zero */
34 const uint8_t sr_mask[8] = {
45 const uint8_t gr_mask[16] = {
46 (uint8_t)~0xf0, /* 0x00 */
47 (uint8_t)~0xf0, /* 0x01 */
48 (uint8_t)~0xf0, /* 0x02 */
49 (uint8_t)~0xe0, /* 0x03 */
50 (uint8_t)~0xfc, /* 0x04 */
51 (uint8_t)~0x84, /* 0x05 */
52 (uint8_t)~0xf0, /* 0x06 */
53 (uint8_t)~0xf0, /* 0x07 */
54 (uint8_t)~0x00, /* 0x08 */
55 (uint8_t)~0xff, /* 0x09 */
56 (uint8_t)~0xff, /* 0x0a */
57 (uint8_t)~0xff, /* 0x0b */
58 (uint8_t)~0xff, /* 0x0c */
59 (uint8_t)~0xff, /* 0x0d */
60 (uint8_t)~0xff, /* 0x0e */
61 (uint8_t)~0xff, /* 0x0f */
64 #define cbswap_32(__x) \
66 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
67 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
68 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
69 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
71 #ifdef WORDS_BIGENDIAN
72 #define PAT(x) cbswap_32(x)
77 #ifdef WORDS_BIGENDIAN
83 #ifdef WORDS_BIGENDIAN
84 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
86 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
89 static const uint32_t mask16[16] = {
110 #ifdef WORDS_BIGENDIAN
113 #define PAT(x) cbswap_32(x)
116 static const uint32_t dmask16[16] = {
135 static const uint32_t dmask4[4] = {
142 static uint32_t expand4[256];
143 static uint16_t expand2[256];
144 static uint8_t expand4to8[16];
149 static void vga_screen_dump(void *opaque, const char *filename);
151 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
153 VGAState *s = opaque;
156 /* check port range access depending on color/monochrome mode */
157 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
158 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
163 if (s->ar_flip_flop == 0) {
170 index = s->ar_index & 0x1f;
183 val = s->sr[s->sr_index];
185 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
192 val = s->dac_write_index;
195 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
196 if (++s->dac_sub_index == 3) {
197 s->dac_sub_index = 0;
211 val = s->gr[s->gr_index];
213 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
222 val = s->cr[s->cr_index];
224 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
229 /* just toggle to fool polling */
230 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
239 #if defined(DEBUG_VGA)
240 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
245 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
247 VGAState *s = opaque;
250 /* check port range access depending on color/monochrome mode */
251 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
252 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
256 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
261 if (s->ar_flip_flop == 0) {
265 index = s->ar_index & 0x1f;
268 s->ar[index] = val & 0x3f;
271 s->ar[index] = val & ~0x10;
277 s->ar[index] = val & ~0xc0;
280 s->ar[index] = val & ~0xf0;
283 s->ar[index] = val & ~0xf0;
289 s->ar_flip_flop ^= 1;
292 s->msr = val & ~0x10;
295 s->sr_index = val & 7;
299 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
301 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
304 s->dac_read_index = val;
305 s->dac_sub_index = 0;
309 s->dac_write_index = val;
310 s->dac_sub_index = 0;
314 s->dac_cache[s->dac_sub_index] = val;
315 if (++s->dac_sub_index == 3) {
316 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
317 s->dac_sub_index = 0;
318 s->dac_write_index++;
322 s->gr_index = val & 0x0f;
326 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
328 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
337 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
339 /* handle CR0-7 protection */
340 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
341 /* can always write bit 4 of CR7 */
342 if (s->cr_index == 7)
343 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
346 switch(s->cr_index) {
347 case 0x01: /* horizontal display end */
352 case 0x12: /* veritcal display end */
353 s->cr[s->cr_index] = val;
356 s->cr[s->cr_index] = val;
367 #ifdef CONFIG_BOCHS_VBE
368 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
370 VGAState *s = opaque;
376 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
378 VGAState *s = opaque;
381 if (s->vbe_index <= VBE_DISPI_INDEX_NB)
382 val = s->vbe_regs[s->vbe_index];
385 #ifdef DEBUG_BOCHS_VBE
386 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
391 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
393 VGAState *s = opaque;
397 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
399 VGAState *s = opaque;
401 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
402 #ifdef DEBUG_BOCHS_VBE
403 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
405 switch(s->vbe_index) {
406 case VBE_DISPI_INDEX_ID:
407 if (val == VBE_DISPI_ID0 ||
408 val == VBE_DISPI_ID1 ||
409 val == VBE_DISPI_ID2) {
410 s->vbe_regs[s->vbe_index] = val;
413 case VBE_DISPI_INDEX_XRES:
414 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
415 s->vbe_regs[s->vbe_index] = val;
418 case VBE_DISPI_INDEX_YRES:
419 if (val <= VBE_DISPI_MAX_YRES) {
420 s->vbe_regs[s->vbe_index] = val;
423 case VBE_DISPI_INDEX_BPP:
426 if (val == 4 || val == 8 || val == 15 ||
427 val == 16 || val == 24 || val == 32) {
428 s->vbe_regs[s->vbe_index] = val;
431 case VBE_DISPI_INDEX_BANK:
432 val &= s->vbe_bank_mask;
433 s->vbe_regs[s->vbe_index] = val;
434 s->bank_offset = (val << 16);
436 case VBE_DISPI_INDEX_ENABLE:
437 if (val & VBE_DISPI_ENABLED) {
438 int h, shift_control;
440 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
441 s->vbe_regs[VBE_DISPI_INDEX_XRES];
442 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
443 s->vbe_regs[VBE_DISPI_INDEX_YRES];
444 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
445 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
447 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
448 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
450 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
451 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
452 s->vbe_start_addr = 0;
454 /* clear the screen (should be done in BIOS) */
455 if (!(val & VBE_DISPI_NOCLEARMEM)) {
456 memset(s->vram_ptr, 0,
457 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
460 /* we initialize the VGA graphic mode (should be done
462 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
463 s->cr[0x17] |= 3; /* no CGA modes */
464 s->cr[0x13] = s->vbe_line_offset >> 3;
466 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
468 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
470 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
471 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
472 /* line compare to 1023 */
477 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
479 s->sr[0x01] &= ~8; /* no double line */
482 s->sr[4] |= 0x08; /* set chain 4 mode */
483 s->sr[2] |= 0x0f; /* activate all planes */
485 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
486 s->cr[0x09] &= ~0x9f; /* no double scan */
488 /* XXX: the bios should do that */
491 s->vbe_regs[s->vbe_index] = val;
493 case VBE_DISPI_INDEX_VIRT_WIDTH:
495 int w, h, line_offset;
497 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
500 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
501 line_offset = w >> 1;
503 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
504 h = s->vram_size / line_offset;
505 /* XXX: support weird bochs semantics ? */
506 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
508 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
509 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
510 s->vbe_line_offset = line_offset;
513 case VBE_DISPI_INDEX_X_OFFSET:
514 case VBE_DISPI_INDEX_Y_OFFSET:
517 s->vbe_regs[s->vbe_index] = val;
518 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
519 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
520 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
521 s->vbe_start_addr += x >> 1;
523 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
524 s->vbe_start_addr >>= 2;
534 /* called for accesses between 0xa0000 and 0xc0000 */
535 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
537 VGAState *s = opaque;
538 int memory_map_mode, plane;
541 /* convert to VGA memory offset */
542 memory_map_mode = (s->gr[6] >> 2) & 3;
544 switch(memory_map_mode) {
550 addr += s->bank_offset;
565 if (s->sr[4] & 0x08) {
566 /* chain 4 mode : simplest access */
567 ret = s->vram_ptr[addr];
568 } else if (s->gr[5] & 0x10) {
569 /* odd/even mode (aka text mode mapping) */
570 plane = (s->gr[4] & 2) | (addr & 1);
571 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
573 /* standard VGA latched access */
574 s->latch = ((uint32_t *)s->vram_ptr)[addr];
576 if (!(s->gr[5] & 0x08)) {
579 ret = GET_PLANE(s->latch, plane);
582 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
591 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
594 #ifdef TARGET_WORDS_BIGENDIAN
595 v = vga_mem_readb(opaque, addr) << 8;
596 v |= vga_mem_readb(opaque, addr + 1);
598 v = vga_mem_readb(opaque, addr);
599 v |= vga_mem_readb(opaque, addr + 1) << 8;
604 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
607 #ifdef TARGET_WORDS_BIGENDIAN
608 v = vga_mem_readb(opaque, addr) << 24;
609 v |= vga_mem_readb(opaque, addr + 1) << 16;
610 v |= vga_mem_readb(opaque, addr + 2) << 8;
611 v |= vga_mem_readb(opaque, addr + 3);
613 v = vga_mem_readb(opaque, addr);
614 v |= vga_mem_readb(opaque, addr + 1) << 8;
615 v |= vga_mem_readb(opaque, addr + 2) << 16;
616 v |= vga_mem_readb(opaque, addr + 3) << 24;
621 /* called for accesses between 0xa0000 and 0xc0000 */
622 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
624 VGAState *s = opaque;
625 int memory_map_mode, plane, write_mode, b, func_select, mask;
626 uint32_t write_mask, bit_mask, set_mask;
629 printf("vga: [0x%x] = 0x%02x\n", addr, val);
631 /* convert to VGA memory offset */
632 memory_map_mode = (s->gr[6] >> 2) & 3;
634 switch(memory_map_mode) {
640 addr += s->bank_offset;
655 if (s->sr[4] & 0x08) {
656 /* chain 4 mode : simplest access */
659 if (s->sr[2] & mask) {
660 s->vram_ptr[addr] = val;
662 printf("vga: chain4: [0x%x]\n", addr);
664 s->plane_updated |= mask; /* only used to detect font change */
665 cpu_physical_memory_set_dirty(s->vram_offset + addr);
667 } else if (s->gr[5] & 0x10) {
668 /* odd/even mode (aka text mode mapping) */
669 plane = (s->gr[4] & 2) | (addr & 1);
671 if (s->sr[2] & mask) {
672 addr = ((addr & ~1) << 1) | plane;
673 s->vram_ptr[addr] = val;
675 printf("vga: odd/even: [0x%x]\n", addr);
677 s->plane_updated |= mask; /* only used to detect font change */
678 cpu_physical_memory_set_dirty(s->vram_offset + addr);
681 /* standard VGA latched access */
682 write_mode = s->gr[5] & 3;
688 val = ((val >> b) | (val << (8 - b))) & 0xff;
692 /* apply set/reset mask */
693 set_mask = mask16[s->gr[1]];
694 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
701 val = mask16[val & 0x0f];
707 val = (val >> b) | (val << (8 - b));
709 bit_mask = s->gr[8] & val;
710 val = mask16[s->gr[0]];
714 /* apply logical operation */
715 func_select = s->gr[3] >> 3;
716 switch(func_select) {
736 bit_mask |= bit_mask << 8;
737 bit_mask |= bit_mask << 16;
738 val = (val & bit_mask) | (s->latch & ~bit_mask);
741 /* mask data according to sr[2] */
743 s->plane_updated |= mask; /* only used to detect font change */
744 write_mask = mask16[mask];
745 ((uint32_t *)s->vram_ptr)[addr] =
746 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
749 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
750 addr * 4, write_mask, val);
752 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
756 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
758 #ifdef TARGET_WORDS_BIGENDIAN
759 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
760 vga_mem_writeb(opaque, addr + 1, val & 0xff);
762 vga_mem_writeb(opaque, addr, val & 0xff);
763 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
767 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
769 #ifdef TARGET_WORDS_BIGENDIAN
770 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
771 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
772 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
773 vga_mem_writeb(opaque, addr + 3, val & 0xff);
775 vga_mem_writeb(opaque, addr, val & 0xff);
776 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
777 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
778 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
782 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
783 const uint8_t *font_ptr, int h,
784 uint32_t fgcol, uint32_t bgcol);
785 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
786 const uint8_t *font_ptr, int h,
787 uint32_t fgcol, uint32_t bgcol, int dup9);
788 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
789 const uint8_t *s, int width);
791 static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
793 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
796 static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
798 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
801 static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
803 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
806 static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
808 return (r << 16) | (g << 8) | b;
811 static inline unsigned int rgb_to_pixel32bgr(unsigned int r, unsigned int g, unsigned b)
813 return (b << 16) | (g << 8) | r;
817 #include "vga_template.h"
820 #include "vga_template.h"
823 #include "vga_template.h"
826 #include "vga_template.h"
830 #include "vga_template.h"
832 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
835 col = rgb_to_pixel8(r, g, b);
841 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
844 col = rgb_to_pixel15(r, g, b);
849 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
852 col = rgb_to_pixel16(r, g, b);
857 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
860 col = rgb_to_pixel32(r, g, b);
864 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
867 col = rgb_to_pixel32bgr(r, g, b);
871 /* return true if the palette was modified */
872 static int update_palette16(VGAState *s)
875 uint32_t v, col, *palette;
878 palette = s->last_palette;
879 for(i = 0; i < 16; i++) {
881 if (s->ar[0x10] & 0x80)
882 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
884 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
886 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
887 c6_to_8(s->palette[v + 1]),
888 c6_to_8(s->palette[v + 2]));
889 if (col != palette[i]) {
897 /* return true if the palette was modified */
898 static int update_palette256(VGAState *s)
901 uint32_t v, col, *palette;
904 palette = s->last_palette;
906 for(i = 0; i < 256; i++) {
907 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
908 c6_to_8(s->palette[v + 1]),
909 c6_to_8(s->palette[v + 2]));
910 if (col != palette[i]) {
919 static void vga_get_offsets(VGAState *s,
920 uint32_t *pline_offset,
921 uint32_t *pstart_addr)
923 uint32_t start_addr, line_offset;
924 #ifdef CONFIG_BOCHS_VBE
925 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
926 line_offset = s->vbe_line_offset;
927 start_addr = s->vbe_start_addr;
931 /* compute line_offset in bytes */
932 line_offset = s->cr[0x13];
935 /* starting address */
936 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
938 *pline_offset = line_offset;
939 *pstart_addr = start_addr;
942 /* update start_addr and line_offset. Return TRUE if modified */
943 static int update_basic_params(VGAState *s)
946 uint32_t start_addr, line_offset, line_compare;
950 s->get_offsets(s, &line_offset, &start_addr);
952 line_compare = s->cr[0x18] |
953 ((s->cr[0x07] & 0x10) << 4) |
954 ((s->cr[0x09] & 0x40) << 3);
956 if (line_offset != s->line_offset ||
957 start_addr != s->start_addr ||
958 line_compare != s->line_compare) {
959 s->line_offset = line_offset;
960 s->start_addr = start_addr;
961 s->line_compare = line_compare;
969 static inline int get_depth_index(DisplayState *s)
987 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
995 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1000 vga_draw_glyph16_32,
1003 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1011 static const uint8_t cursor_glyph[32 * 4] = {
1012 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1013 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1014 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1015 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1016 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1017 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1018 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1019 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1020 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1021 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1022 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1023 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1024 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1025 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1026 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1027 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1038 static void vga_draw_text(VGAState *s, int full_update)
1040 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1041 int cx_min, cx_max, linesize, x_incr;
1042 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1043 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1044 const uint8_t *font_ptr, *font_base[2];
1045 int dup9, line_offset, depth_index;
1047 uint32_t *ch_attr_ptr;
1048 vga_draw_glyph8_func *vga_draw_glyph8;
1049 vga_draw_glyph9_func *vga_draw_glyph9;
1051 full_update |= update_palette16(s);
1052 palette = s->last_palette;
1054 /* compute font data address (in plane 2) */
1056 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1057 if (offset != s->font_offsets[0]) {
1058 s->font_offsets[0] = offset;
1061 font_base[0] = s->vram_ptr + offset;
1063 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1064 font_base[1] = s->vram_ptr + offset;
1065 if (offset != s->font_offsets[1]) {
1066 s->font_offsets[1] = offset;
1069 if (s->plane_updated & (1 << 2)) {
1070 /* if the plane 2 was modified since the last display, it
1071 indicates the font may have been modified */
1072 s->plane_updated = 0;
1075 full_update |= update_basic_params(s);
1077 line_offset = s->line_offset;
1078 s1 = s->vram_ptr + (s->start_addr * 4);
1080 /* total width & height */
1081 cheight = (s->cr[9] & 0x1f) + 1;
1083 if (!(s->sr[1] & 0x01))
1085 if (s->sr[1] & 0x08)
1086 cw = 16; /* NOTE: no 18 pixel wide */
1087 x_incr = cw * ((s->ds->depth + 7) >> 3);
1088 width = (s->cr[0x01] + 1);
1089 if (s->cr[0x06] == 100) {
1090 /* ugly hack for CGA 160x100x16 - explain me the logic */
1093 height = s->cr[0x12] |
1094 ((s->cr[0x07] & 0x02) << 7) |
1095 ((s->cr[0x07] & 0x40) << 3);
1096 height = (height + 1) / cheight;
1098 if ((height * width) > CH_ATTR_SIZE) {
1099 /* better than nothing: exit if transient size is too big */
1103 if (width != s->last_width || height != s->last_height ||
1104 cw != s->last_cw || cheight != s->last_ch) {
1105 s->last_scr_width = width * cw;
1106 s->last_scr_height = height * cheight;
1107 dpy_resize(s->ds, s->last_scr_width, s->last_scr_height);
1108 s->last_width = width;
1109 s->last_height = height;
1110 s->last_ch = cheight;
1114 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1115 if (cursor_offset != s->cursor_offset ||
1116 s->cr[0xa] != s->cursor_start ||
1117 s->cr[0xb] != s->cursor_end) {
1118 /* if the cursor position changed, we update the old and new
1120 if (s->cursor_offset < CH_ATTR_SIZE)
1121 s->last_ch_attr[s->cursor_offset] = -1;
1122 if (cursor_offset < CH_ATTR_SIZE)
1123 s->last_ch_attr[cursor_offset] = -1;
1124 s->cursor_offset = cursor_offset;
1125 s->cursor_start = s->cr[0xa];
1126 s->cursor_end = s->cr[0xb];
1128 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1130 depth_index = get_depth_index(s->ds);
1132 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1134 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1135 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1138 linesize = s->ds->linesize;
1139 ch_attr_ptr = s->last_ch_attr;
1140 for(cy = 0; cy < height; cy++) {
1145 for(cx = 0; cx < width; cx++) {
1146 ch_attr = *(uint16_t *)src;
1147 if (full_update || ch_attr != *ch_attr_ptr) {
1152 *ch_attr_ptr = ch_attr;
1153 #ifdef WORDS_BIGENDIAN
1155 cattr = ch_attr & 0xff;
1157 ch = ch_attr & 0xff;
1158 cattr = ch_attr >> 8;
1160 font_ptr = font_base[(cattr >> 3) & 1];
1161 font_ptr += 32 * 4 * ch;
1162 bgcol = palette[cattr >> 4];
1163 fgcol = palette[cattr & 0x0f];
1165 vga_draw_glyph8(d1, linesize,
1166 font_ptr, cheight, fgcol, bgcol);
1169 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1171 vga_draw_glyph9(d1, linesize,
1172 font_ptr, cheight, fgcol, bgcol, dup9);
1174 if (src == cursor_ptr &&
1175 !(s->cr[0x0a] & 0x20)) {
1176 int line_start, line_last, h;
1177 /* draw the cursor */
1178 line_start = s->cr[0x0a] & 0x1f;
1179 line_last = s->cr[0x0b] & 0x1f;
1180 /* XXX: check that */
1181 if (line_last > cheight - 1)
1182 line_last = cheight - 1;
1183 if (line_last >= line_start && line_start < cheight) {
1184 h = line_last - line_start + 1;
1185 d = d1 + linesize * line_start;
1187 vga_draw_glyph8(d, linesize,
1188 cursor_glyph, h, fgcol, bgcol);
1190 vga_draw_glyph9(d, linesize,
1191 cursor_glyph, h, fgcol, bgcol, 1);
1201 dpy_update(s->ds, cx_min * cw, cy * cheight,
1202 (cx_max - cx_min + 1) * cw, cheight);
1204 dest += linesize * cheight;
1223 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1231 vga_draw_line2d2_16,
1232 vga_draw_line2d2_16,
1233 vga_draw_line2d2_32,
1234 vga_draw_line2d2_32,
1243 vga_draw_line4d2_16,
1244 vga_draw_line4d2_16,
1245 vga_draw_line4d2_32,
1246 vga_draw_line4d2_32,
1249 vga_draw_line8d2_16,
1250 vga_draw_line8d2_16,
1251 vga_draw_line8d2_32,
1252 vga_draw_line8d2_32,
1264 vga_draw_line15_32bgr,
1270 vga_draw_line16_32bgr,
1276 vga_draw_line24_32bgr,
1282 vga_draw_line32_32bgr,
1285 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1287 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1292 rgb_to_pixel32bgr_dup,
1295 static int vga_get_bpp(VGAState *s)
1298 #ifdef CONFIG_BOCHS_VBE
1299 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1300 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1309 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1313 width = (s->cr[0x01] + 1) * 8;
1314 height = s->cr[0x12] |
1315 ((s->cr[0x07] & 0x02) << 7) |
1316 ((s->cr[0x07] & 0x40) << 3);
1317 height = (height + 1);
1322 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1325 if (y1 >= VGA_MAX_HEIGHT)
1327 if (y2 >= VGA_MAX_HEIGHT)
1328 y2 = VGA_MAX_HEIGHT;
1329 for(y = y1; y < y2; y++) {
1330 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1337 static void vga_draw_graphic(VGAState *s, int full_update)
1339 int y1, y, update, page_min, page_max, linesize, y_start, double_scan, mask;
1340 int width, height, shift_control, line_offset, page0, page1, bwidth;
1341 int disp_width, multi_scan, multi_run;
1343 uint32_t v, addr1, addr;
1344 vga_draw_line_func *vga_draw_line;
1346 full_update |= update_basic_params(s);
1348 s->get_resolution(s, &width, &height);
1351 shift_control = (s->gr[0x05] >> 5) & 3;
1352 double_scan = (s->cr[0x09] >> 7);
1353 if (shift_control != 1) {
1354 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1356 /* in CGA modes, multi_scan is ignored */
1357 /* XXX: is it correct ? */
1358 multi_scan = double_scan;
1360 multi_run = multi_scan;
1361 if (shift_control != s->shift_control ||
1362 double_scan != s->double_scan) {
1364 s->shift_control = shift_control;
1365 s->double_scan = double_scan;
1368 if (shift_control == 0) {
1369 full_update |= update_palette16(s);
1370 if (s->sr[0x01] & 8) {
1371 v = VGA_DRAW_LINE4D2;
1376 } else if (shift_control == 1) {
1377 full_update |= update_palette16(s);
1378 if (s->sr[0x01] & 8) {
1379 v = VGA_DRAW_LINE2D2;
1385 switch(s->get_bpp(s)) {
1388 full_update |= update_palette256(s);
1389 v = VGA_DRAW_LINE8D2;
1392 full_update |= update_palette256(s);
1396 v = VGA_DRAW_LINE15;
1399 v = VGA_DRAW_LINE16;
1402 v = VGA_DRAW_LINE24;
1405 v = VGA_DRAW_LINE32;
1409 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1411 if (disp_width != s->last_width ||
1412 height != s->last_height) {
1413 dpy_resize(s->ds, disp_width, height);
1414 s->last_scr_width = disp_width;
1415 s->last_scr_height = height;
1416 s->last_width = disp_width;
1417 s->last_height = height;
1420 if (s->cursor_invalidate)
1421 s->cursor_invalidate(s);
1423 line_offset = s->line_offset;
1425 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1426 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1428 addr1 = (s->start_addr * 4);
1431 page_min = 0x7fffffff;
1434 linesize = s->ds->linesize;
1436 for(y = 0; y < height; y++) {
1438 if (!(s->cr[0x17] & 1)) {
1440 /* CGA compatibility handling */
1441 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1442 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1444 if (!(s->cr[0x17] & 2)) {
1445 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1447 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1448 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1449 update = full_update |
1450 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1451 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1452 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1453 /* if wide line, can use another page */
1454 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1457 /* explicit invalidation for the hardware cursor */
1458 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1462 if (page0 < page_min)
1464 if (page1 > page_max)
1466 vga_draw_line(s, d, s->vram_ptr + addr, width);
1467 if (s->cursor_draw_line)
1468 s->cursor_draw_line(s, d, y);
1471 /* flush to display */
1472 dpy_update(s->ds, 0, y_start,
1473 disp_width, y - y_start);
1478 mask = (s->cr[0x17] & 3) ^ 3;
1479 if ((y1 & mask) == mask)
1480 addr1 += line_offset;
1482 multi_run = multi_scan;
1486 /* line compare acts on the displayed lines */
1487 if (y == s->line_compare)
1492 /* flush to display */
1493 dpy_update(s->ds, 0, y_start,
1494 disp_width, y - y_start);
1496 /* reset modified pages */
1497 if (page_max != -1) {
1498 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1501 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1504 static void vga_draw_blank(VGAState *s, int full_update)
1511 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1513 if (s->ds->depth == 8)
1514 val = s->rgb_to_pixel(0, 0, 0);
1517 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
1519 for(i = 0; i < s->last_scr_height; i++) {
1521 d += s->ds->linesize;
1523 dpy_update(s->ds, 0, 0,
1524 s->last_scr_width, s->last_scr_height);
1527 #define GMODE_TEXT 0
1528 #define GMODE_GRAPH 1
1529 #define GMODE_BLANK 2
1531 static void vga_update_display(void *opaque)
1533 VGAState *s = (VGAState *)opaque;
1534 int full_update, graphic_mode;
1536 if (s->ds->depth == 0) {
1540 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1543 if (!(s->ar_index & 0x20)) {
1544 graphic_mode = GMODE_BLANK;
1546 graphic_mode = s->gr[6] & 1;
1548 if (graphic_mode != s->graphic_mode) {
1549 s->graphic_mode = graphic_mode;
1552 switch(graphic_mode) {
1554 vga_draw_text(s, full_update);
1557 vga_draw_graphic(s, full_update);
1561 vga_draw_blank(s, full_update);
1567 /* force a full display refresh */
1568 static void vga_invalidate_display(void *opaque)
1570 VGAState *s = (VGAState *)opaque;
1573 s->last_height = -1;
1576 static void vga_reset(VGAState *s)
1578 memset(s, 0, sizeof(VGAState));
1579 s->graphic_mode = -1; /* force full update */
1582 static CPUReadMemoryFunc *vga_mem_read[3] = {
1588 static CPUWriteMemoryFunc *vga_mem_write[3] = {
1594 static void vga_save(QEMUFile *f, void *opaque)
1596 VGAState *s = opaque;
1599 qemu_put_be32s(f, &s->latch);
1600 qemu_put_8s(f, &s->sr_index);
1601 qemu_put_buffer(f, s->sr, 8);
1602 qemu_put_8s(f, &s->gr_index);
1603 qemu_put_buffer(f, s->gr, 16);
1604 qemu_put_8s(f, &s->ar_index);
1605 qemu_put_buffer(f, s->ar, 21);
1606 qemu_put_be32s(f, &s->ar_flip_flop);
1607 qemu_put_8s(f, &s->cr_index);
1608 qemu_put_buffer(f, s->cr, 256);
1609 qemu_put_8s(f, &s->msr);
1610 qemu_put_8s(f, &s->fcr);
1611 qemu_put_8s(f, &s->st00);
1612 qemu_put_8s(f, &s->st01);
1614 qemu_put_8s(f, &s->dac_state);
1615 qemu_put_8s(f, &s->dac_sub_index);
1616 qemu_put_8s(f, &s->dac_read_index);
1617 qemu_put_8s(f, &s->dac_write_index);
1618 qemu_put_buffer(f, s->dac_cache, 3);
1619 qemu_put_buffer(f, s->palette, 768);
1621 qemu_put_be32s(f, &s->bank_offset);
1622 #ifdef CONFIG_BOCHS_VBE
1623 qemu_put_byte(f, 1);
1624 qemu_put_be16s(f, &s->vbe_index);
1625 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
1626 qemu_put_be16s(f, &s->vbe_regs[i]);
1627 qemu_put_be32s(f, &s->vbe_start_addr);
1628 qemu_put_be32s(f, &s->vbe_line_offset);
1629 qemu_put_be32s(f, &s->vbe_bank_mask);
1631 qemu_put_byte(f, 0);
1635 static int vga_load(QEMUFile *f, void *opaque, int version_id)
1637 VGAState *s = opaque;
1640 if (version_id != 1)
1643 qemu_get_be32s(f, &s->latch);
1644 qemu_get_8s(f, &s->sr_index);
1645 qemu_get_buffer(f, s->sr, 8);
1646 qemu_get_8s(f, &s->gr_index);
1647 qemu_get_buffer(f, s->gr, 16);
1648 qemu_get_8s(f, &s->ar_index);
1649 qemu_get_buffer(f, s->ar, 21);
1650 qemu_get_be32s(f, &s->ar_flip_flop);
1651 qemu_get_8s(f, &s->cr_index);
1652 qemu_get_buffer(f, s->cr, 256);
1653 qemu_get_8s(f, &s->msr);
1654 qemu_get_8s(f, &s->fcr);
1655 qemu_get_8s(f, &s->st00);
1656 qemu_get_8s(f, &s->st01);
1658 qemu_get_8s(f, &s->dac_state);
1659 qemu_get_8s(f, &s->dac_sub_index);
1660 qemu_get_8s(f, &s->dac_read_index);
1661 qemu_get_8s(f, &s->dac_write_index);
1662 qemu_get_buffer(f, s->dac_cache, 3);
1663 qemu_get_buffer(f, s->palette, 768);
1665 qemu_get_be32s(f, &s->bank_offset);
1666 is_vbe = qemu_get_byte(f);
1667 #ifdef CONFIG_BOCHS_VBE
1670 qemu_get_be16s(f, &s->vbe_index);
1671 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
1672 qemu_get_be16s(f, &s->vbe_regs[i]);
1673 qemu_get_be32s(f, &s->vbe_start_addr);
1674 qemu_get_be32s(f, &s->vbe_line_offset);
1675 qemu_get_be32s(f, &s->vbe_bank_mask);
1682 s->graphic_mode = -1;
1686 static void vga_map(PCIDevice *pci_dev, int region_num,
1687 uint32_t addr, uint32_t size, int type)
1689 VGAState *s = vga_state;
1690 if (region_num == PCI_ROM_SLOT) {
1691 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
1693 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
1697 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
1698 unsigned long vga_ram_offset, int vga_ram_size)
1702 for(i = 0;i < 256; i++) {
1704 for(j = 0; j < 8; j++) {
1705 v |= ((i >> j) & 1) << (j * 4);
1710 for(j = 0; j < 4; j++) {
1711 v |= ((i >> (2 * j)) & 3) << (j * 4);
1715 for(i = 0; i < 16; i++) {
1717 for(j = 0; j < 4; j++) {
1720 v |= b << (2 * j + 1);
1727 s->vram_ptr = vga_ram_base;
1728 s->vram_offset = vga_ram_offset;
1729 s->vram_size = vga_ram_size;
1731 s->get_bpp = vga_get_bpp;
1732 s->get_offsets = vga_get_offsets;
1733 s->get_resolution = vga_get_resolution;
1734 graphic_console_init(s->ds, vga_update_display, vga_invalidate_display,
1735 vga_screen_dump, s);
1736 /* XXX: currently needed for display */
1741 int vga_initialize(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1742 unsigned long vga_ram_offset, int vga_ram_size,
1743 unsigned long vga_bios_offset, int vga_bios_size)
1747 s = qemu_mallocz(sizeof(VGAState));
1751 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1753 register_savevm("vga", 0, 1, vga_save, vga_load, s);
1755 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
1757 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
1758 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
1759 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
1760 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
1762 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
1764 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
1765 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
1766 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
1767 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
1770 #ifdef CONFIG_BOCHS_VBE
1771 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1772 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
1773 #if defined (TARGET_I386)
1774 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
1775 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
1777 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
1778 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
1780 /* old Bochs IO ports */
1781 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
1782 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
1784 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
1785 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
1787 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
1788 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
1790 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
1791 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
1793 #endif /* CONFIG_BOCHS_VBE */
1795 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
1796 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
1803 d = pci_register_device(bus, "VGA",
1806 pci_conf = d->config;
1807 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
1808 pci_conf[0x01] = 0x12;
1809 pci_conf[0x02] = 0x11;
1810 pci_conf[0x03] = 0x11;
1811 pci_conf[0x0a] = 0x00; // VGA controller
1812 pci_conf[0x0b] = 0x03;
1813 pci_conf[0x0e] = 0x00; // header_type
1815 /* XXX: vga_ram_size must be a power of two */
1816 pci_register_io_region(d, 0, vga_ram_size,
1817 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
1818 if (vga_bios_size != 0) {
1819 unsigned int bios_total_size;
1820 s->bios_offset = vga_bios_offset;
1821 s->bios_size = vga_bios_size;
1822 /* must be a power of two */
1823 bios_total_size = 1;
1824 while (bios_total_size < vga_bios_size)
1825 bios_total_size <<= 1;
1826 pci_register_io_region(d, PCI_ROM_SLOT, bios_total_size,
1827 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
1830 #ifdef CONFIG_BOCHS_VBE
1831 /* XXX: use optimized standard vga accesses */
1832 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1833 vga_ram_size, vga_ram_offset);
1839 /********************************************************/
1840 /* vga screen dump */
1842 static int vga_save_w, vga_save_h;
1844 static void vga_save_dpy_update(DisplayState *s,
1845 int x, int y, int w, int h)
1849 static void vga_save_dpy_resize(DisplayState *s, int w, int h)
1851 s->linesize = w * 4;
1852 s->data = qemu_malloc(h * s->linesize);
1857 static void vga_save_dpy_refresh(DisplayState *s)
1861 static int ppm_save(const char *filename, uint8_t *data,
1862 int w, int h, int linesize)
1869 f = fopen(filename, "wb");
1872 fprintf(f, "P6\n%d %d\n%d\n",
1875 for(y = 0; y < h; y++) {
1877 for(x = 0; x < w; x++) {
1879 fputc((v >> 16) & 0xff, f);
1880 fputc((v >> 8) & 0xff, f);
1881 fputc((v) & 0xff, f);
1890 /* save the vga display in a PPM image even if no display is
1892 static void vga_screen_dump(void *opaque, const char *filename)
1894 VGAState *s = (VGAState *)opaque;
1895 DisplayState *saved_ds, ds1, *ds = &ds1;
1897 /* XXX: this is a little hackish */
1898 vga_invalidate_display(s);
1901 memset(ds, 0, sizeof(DisplayState));
1902 ds->dpy_update = vga_save_dpy_update;
1903 ds->dpy_resize = vga_save_dpy_resize;
1904 ds->dpy_refresh = vga_save_dpy_refresh;
1908 s->graphic_mode = -1;
1909 vga_update_display(s);
1912 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
1914 qemu_free(ds->data);