2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-timer.h"
33 #include "firmware_abi.h"
39 #define DPRINTF(fmt, args...) \
40 do { printf("CPUIRQ: " fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...)
45 #define KERNEL_LOAD_ADDR 0x00404000
46 #define CMDLINE_ADDR 0x003ff000
47 #define INITRD_LOAD_ADDR 0x00300000
48 #define PROM_SIZE_MAX (4 * 1024 * 1024)
49 #define PROM_VADDR 0x000ffd00000ULL
50 #define APB_SPECIAL_BASE 0x1fe00000000ULL
51 #define APB_MEM_BASE 0x1ff00000000ULL
52 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
53 #define PROM_FILENAME "openbios-sparc64"
54 #define NVRAM_SIZE 0x2000
56 #define BIOS_CFG_IOPORT 0x510
61 const char * const default_cpu_model;
64 uint64_t console_serial_base;
67 int DMA_get_channel_mode (int nchan)
71 int DMA_read_memory (int nchan, void *buf, int pos, int size)
75 int DMA_write_memory (int nchan, void *buf, int pos, int size)
79 void DMA_hold_DREQ (int nchan) {}
80 void DMA_release_DREQ (int nchan) {}
81 void DMA_schedule(int nchan) {}
82 void DMA_run (void) {}
83 void DMA_init (int high_page_enable) {}
84 void DMA_register_channel (int nchan,
85 DMA_transfer_handler transfer_handler,
90 static int nvram_boot_set(void *opaque, const char *boot_device)
93 uint8_t image[sizeof(ohwcfg_v3_t)];
94 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
95 m48t59_t *nvram = (m48t59_t *)opaque;
97 for (i = 0; i < sizeof(image); i++)
98 image[i] = m48t59_read(nvram, i) & 0xff;
100 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
102 header->nboot_devices = strlen(boot_device) & 0xff;
103 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
105 for (i = 0; i < sizeof(image); i++)
106 m48t59_write(nvram, i, image[i]);
111 extern int nographic;
113 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
116 const char *boot_devices,
117 uint32_t kernel_image, uint32_t kernel_size,
119 uint32_t initrd_image, uint32_t initrd_size,
120 uint32_t NVRAM_image,
121 int width, int height, int depth,
122 const uint8_t *macaddr)
126 uint8_t image[0x1ff0];
127 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
128 struct sparc_arch_cfg *sparc_header;
129 struct OpenBIOS_nvpart_v1 *part_header;
131 memset(image, '\0', sizeof(image));
133 // Try to match PPC NVRAM
134 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
136 header->struct_version = cpu_to_be32(3); /* structure v3 */
138 header->nvram_size = cpu_to_be16(NVRAM_size);
139 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
140 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
141 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
142 header->nb_cpus = smp_cpus & 0xff;
143 header->RAM0_base = 0;
144 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
145 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
147 header->nboot_devices = strlen(boot_devices) & 0xff;
148 header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
149 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
151 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
152 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
153 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
155 header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
156 header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
157 header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
159 header->width = cpu_to_be16(width);
160 header->height = cpu_to_be16(height);
161 header->depth = cpu_to_be16(depth);
163 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
165 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
167 // Architecture specific header
168 start = sizeof(ohwcfg_v3_t);
169 sparc_header = (struct sparc_arch_cfg *)&image[start];
170 sparc_header->valid = 0;
171 start += sizeof(struct sparc_arch_cfg);
173 // OpenBIOS nvram variables
174 // Variable partition
175 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
176 part_header->signature = OPENBIOS_PART_SYSTEM;
177 pstrcpy(part_header->name, sizeof(part_header->name), "system");
179 end = start + sizeof(struct OpenBIOS_nvpart_v1);
180 for (i = 0; i < nb_prom_envs; i++)
181 end = OpenBIOS_set_var(image, end, prom_envs[i]);
186 end = start + ((end - start + 15) & ~15);
187 OpenBIOS_finish_partition(part_header, end - start);
191 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
192 part_header->signature = OPENBIOS_PART_FREE;
193 pstrcpy(part_header->name, sizeof(part_header->name), "free");
196 OpenBIOS_finish_partition(part_header, end - start);
198 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
200 for (i = 0; i < sizeof(image); i++)
201 m48t59_write(nvram, i, image[i]);
203 qemu_register_boot_set(nvram_boot_set, nvram);
216 void cpu_check_irqs(CPUState *env)
218 uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
219 ((env->softint & SOFTINT_TIMER) << 14);
221 if (pil && (env->interrupt_index == 0 ||
222 (env->interrupt_index & ~15) == TT_EXTINT)) {
225 for (i = 15; i > 0; i--) {
226 if (pil & (1 << i)) {
227 int old_interrupt = env->interrupt_index;
229 env->interrupt_index = TT_EXTINT | i;
230 if (old_interrupt != env->interrupt_index) {
231 DPRINTF("Set CPU IRQ %d\n", i);
232 cpu_interrupt(env, CPU_INTERRUPT_HARD);
237 } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
238 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
239 env->interrupt_index = 0;
240 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
244 static void cpu_set_irq(void *opaque, int irq, int level)
246 CPUState *env = opaque;
249 DPRINTF("Raise CPU IRQ %d\n", irq);
251 env->pil_in |= 1 << irq;
254 DPRINTF("Lower CPU IRQ %d\n", irq);
255 env->pil_in &= ~(1 << irq);
260 void qemu_system_powerdown(void)
264 typedef struct ResetData {
269 static void main_cpu_reset(void *opaque)
271 ResetData *s = (ResetData *)opaque;
272 CPUState *env = s->env;
275 ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
276 ptimer_run(env->tick, 0);
277 ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
278 ptimer_run(env->stick, 0);
279 ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
280 ptimer_run(env->hstick, 0);
281 env->gregs[1] = 0; // Memory start
282 env->gregs[2] = ram_size; // Memory size
283 env->gregs[3] = 0; // Machine description XXX
284 env->pc = s->reset_addr;
285 env->npc = env->pc + 4;
288 static void tick_irq(void *opaque)
290 CPUState *env = opaque;
292 env->softint |= SOFTINT_TIMER;
293 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
296 static void stick_irq(void *opaque)
298 CPUState *env = opaque;
300 env->softint |= SOFTINT_TIMER;
301 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
304 static void hstick_irq(void *opaque)
306 CPUState *env = opaque;
308 env->softint |= SOFTINT_TIMER;
309 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
312 void cpu_tick_set_count(void *opaque, uint64_t count)
314 ptimer_set_count(opaque, -count);
317 uint64_t cpu_tick_get_count(void *opaque)
319 return -ptimer_get_count(opaque);
322 void cpu_tick_set_limit(void *opaque, uint64_t limit)
324 ptimer_set_limit(opaque, -limit, 0);
327 static const int ide_iobase[2] = { 0x1f0, 0x170 };
328 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
329 static const int ide_irq[2] = { 14, 15 };
331 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
332 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
334 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
335 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
337 static fdctrl_t *floppy_controller;
339 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
340 const char *boot_devices, DisplayState *ds,
341 const char *kernel_filename, const char *kernel_cmdline,
342 const char *initrd_filename, const char *cpu_model,
343 const struct hwdef *hwdef)
350 long prom_offset, initrd_size, kernel_size;
355 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
356 BlockDriverState *fd[MAX_FD];
358 ResetData *reset_info;
360 linux_boot = (kernel_filename != NULL);
364 cpu_model = hwdef->default_cpu_model;
366 env = cpu_init(cpu_model);
368 fprintf(stderr, "Unable to find Sparc CPU definition\n");
371 bh = qemu_bh_new(tick_irq, env);
372 env->tick = ptimer_init(bh);
373 ptimer_set_period(env->tick, 1ULL);
375 bh = qemu_bh_new(stick_irq, env);
376 env->stick = ptimer_init(bh);
377 ptimer_set_period(env->stick, 1ULL);
379 bh = qemu_bh_new(hstick_irq, env);
380 env->hstick = ptimer_init(bh);
381 ptimer_set_period(env->hstick, 1ULL);
383 reset_info = qemu_mallocz(sizeof(ResetData));
384 reset_info->env = env;
385 reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
386 qemu_register_reset(main_cpu_reset, reset_info);
387 main_cpu_reset(reset_info);
388 // Override warm reset address with cold start address
389 env->pc = hwdef->prom_addr + 0x20ULL;
390 env->npc = env->pc + 4;
393 cpu_register_physical_memory(0, RAM_size, 0);
395 prom_offset = RAM_size + vga_ram_size;
396 cpu_register_physical_memory(hwdef->prom_addr,
397 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
399 prom_offset | IO_MEM_ROM);
401 if (bios_name == NULL)
402 bios_name = PROM_FILENAME;
403 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
404 ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL);
406 ret = load_image_targphys(buf, hwdef->prom_addr,
407 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
410 fprintf(stderr, "qemu: could not load prom '%s'\n",
419 /* XXX: put correct offset */
420 kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
422 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
423 ram_size - KERNEL_LOAD_ADDR);
425 kernel_size = load_image_targphys(kernel_filename,
427 ram_size - KERNEL_LOAD_ADDR);
428 if (kernel_size < 0) {
429 fprintf(stderr, "qemu: could not load kernel '%s'\n",
435 if (initrd_filename) {
436 initrd_size = load_image_targphys(initrd_filename,
438 ram_size - INITRD_LOAD_ADDR);
439 if (initrd_size < 0) {
440 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
445 if (initrd_size > 0) {
446 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
447 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
448 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
449 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
455 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
456 isa_mem_base = VGA_BASE;
457 pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
461 if (hwdef->console_serial_base) {
462 serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
466 for(; i < MAX_SERIAL_PORTS; i++) {
468 serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
473 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
474 if (parallel_hds[i]) {
475 parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
480 for(i = 0; i < nb_nics; i++) {
481 if (!nd_table[i].model)
482 nd_table[i].model = "ne2k_pci";
483 pci_nic_init(pci_bus, &nd_table[i], -1);
486 irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
487 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
488 fprintf(stderr, "qemu: too many IDE bus\n");
491 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
492 drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
494 if (drive_index != -1)
495 hd[i] = drives_table[drive_index].bdrv;
500 // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
501 pci_piix3_ide_init(pci_bus, hd, -1, irq);
502 /* FIXME: wire up interrupts. */
503 i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
504 for(i = 0; i < MAX_FD; i++) {
505 drive_index = drive_get_index(IF_FLOPPY, 0, i);
506 if (drive_index != -1)
507 fd[i] = drives_table[drive_index].bdrv;
511 floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
512 nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
513 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
514 KERNEL_LOAD_ADDR, kernel_size,
516 INITRD_LOAD_ADDR, initrd_size,
517 /* XXX: need an option to load a NVRAM image */
519 graphic_width, graphic_height, graphic_depth,
520 (uint8_t *)&nd_table[0].macaddr);
522 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
523 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
524 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
525 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
534 static const struct hwdef hwdefs[] = {
535 /* Sun4u generic PC-like machine */
537 .default_cpu_model = "TI UltraSparc II",
538 .machine_id = sun4u_id,
539 .prom_addr = 0x1fff0000000ULL,
540 .console_serial_base = 0,
542 /* Sun4v generic PC-like machine */
544 .default_cpu_model = "Sun UltraSparc T1",
545 .machine_id = sun4v_id,
546 .prom_addr = 0x1fff0000000ULL,
547 .console_serial_base = 0,
549 /* Sun4v generic Niagara machine */
551 .default_cpu_model = "Sun UltraSparc T1",
552 .machine_id = niagara_id,
553 .prom_addr = 0xfff0000000ULL,
554 .console_serial_base = 0xfff0c2c000ULL,
558 /* Sun4u hardware initialisation */
559 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
560 const char *boot_devices, DisplayState *ds,
561 const char *kernel_filename, const char *kernel_cmdline,
562 const char *initrd_filename, const char *cpu_model)
564 sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
565 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
568 /* Sun4v hardware initialisation */
569 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
570 const char *boot_devices, DisplayState *ds,
571 const char *kernel_filename, const char *kernel_cmdline,
572 const char *initrd_filename, const char *cpu_model)
574 sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
575 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
578 /* Niagara hardware initialisation */
579 static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
580 const char *boot_devices, DisplayState *ds,
581 const char *kernel_filename, const char *kernel_cmdline,
582 const char *initrd_filename, const char *cpu_model)
584 sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
585 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
588 QEMUMachine sun4u_machine = {
590 .desc = "Sun4u platform",
592 .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
596 QEMUMachine sun4v_machine = {
598 .desc = "Sun4v platform",
600 .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
604 QEMUMachine niagara_machine = {
606 .desc = "Sun4v platform, Niagara",
607 .init = niagara_init,
608 .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,