2 * QEMU Sun4u System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "firmware_abi.h"
28 #define KERNEL_LOAD_ADDR 0x00404000
29 #define CMDLINE_ADDR 0x003ff000
30 #define INITRD_LOAD_ADDR 0x00300000
31 #define PROM_SIZE_MAX (512 * 1024)
32 #define PROM_ADDR 0x1fff0000000ULL
33 #define PROM_VADDR 0x000ffd00000ULL
34 #define APB_SPECIAL_BASE 0x1fe00000000ULL
35 #define APB_MEM_BASE 0x1ff00000000ULL
36 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
37 #define PROM_FILENAME "openbios-sparc64"
38 #define NVRAM_SIZE 0x2000
42 uint64_t cpu_get_tsc()
44 return qemu_get_clock(vm_clock);
47 int DMA_get_channel_mode (int nchan)
51 int DMA_read_memory (int nchan, void *buf, int pos, int size)
55 int DMA_write_memory (int nchan, void *buf, int pos, int size)
59 void DMA_hold_DREQ (int nchan) {}
60 void DMA_release_DREQ (int nchan) {}
61 void DMA_schedule(int nchan) {}
62 void DMA_run (void) {}
63 void DMA_init (int high_page_enable) {}
64 void DMA_register_channel (int nchan,
65 DMA_transfer_handler transfer_handler,
72 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
73 const unsigned char *arch,
74 uint32_t RAM_size, const char *boot_devices,
75 uint32_t kernel_image, uint32_t kernel_size,
77 uint32_t initrd_image, uint32_t initrd_size,
79 int width, int height, int depth)
83 uint8_t image[0x1ff0];
84 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
85 struct sparc_arch_cfg *sparc_header;
86 struct OpenBIOS_nvpart_v1 *part_header;
88 memset(image, '\0', sizeof(image));
90 // Try to match PPC NVRAM
91 strcpy(header->struct_ident, "QEMU_BIOS");
92 header->struct_version = cpu_to_be32(3); /* structure v3 */
94 header->nvram_size = cpu_to_be16(NVRAM_size);
95 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
96 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
97 strcpy(header->arch, arch);
98 header->nb_cpus = smp_cpus & 0xff;
99 header->RAM0_base = 0;
100 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
101 strcpy(header->boot_devices, boot_devices);
102 header->nboot_devices = strlen(boot_devices) & 0xff;
103 header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
104 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
106 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
107 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
108 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
110 header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
111 header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
112 header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
114 header->width = cpu_to_be16(width);
115 header->height = cpu_to_be16(height);
116 header->depth = cpu_to_be16(depth);
118 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
120 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
122 // Architecture specific header
123 start = sizeof(ohwcfg_v3_t);
124 sparc_header = (struct sparc_arch_cfg *)&image[start];
125 sparc_header->valid = 0;
126 start += sizeof(struct sparc_arch_cfg);
128 // OpenBIOS nvram variables
129 // Variable partition
130 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
131 part_header->signature = OPENBIOS_PART_SYSTEM;
132 strcpy(part_header->name, "system");
134 end = start + sizeof(struct OpenBIOS_nvpart_v1);
135 for (i = 0; i < nb_prom_envs; i++)
136 end = OpenBIOS_set_var(image, end, prom_envs[i]);
141 end = start + ((end - start + 15) & ~15);
142 OpenBIOS_finish_partition(part_header, end - start);
146 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
147 part_header->signature = OPENBIOS_PART_FREE;
148 strcpy(part_header->name, "free");
151 OpenBIOS_finish_partition(part_header, end - start);
153 for (i = 0; i < sizeof(image); i++)
154 m48t59_write(nvram, i, image[i]);
167 void qemu_system_powerdown(void)
171 static void main_cpu_reset(void *opaque)
173 CPUState *env = opaque;
176 ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
177 ptimer_run(env->tick, 0);
178 ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
179 ptimer_run(env->stick, 0);
180 ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
181 ptimer_run(env->hstick, 0);
184 void tick_irq(void *opaque)
186 CPUState *env = opaque;
188 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
191 void stick_irq(void *opaque)
193 CPUState *env = opaque;
195 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
198 void hstick_irq(void *opaque)
200 CPUState *env = opaque;
202 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
205 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
209 static const int ide_iobase[2] = { 0x1f0, 0x170 };
210 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
211 static const int ide_irq[2] = { 14, 15 };
213 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
214 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
216 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
217 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
219 static fdctrl_t *floppy_controller;
221 /* Sun4u hardware initialisation */
222 static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_devices,
223 DisplayState *ds, const char **fd_filename, int snapshot,
224 const char *kernel_filename, const char *kernel_cmdline,
225 const char *initrd_filename, const char *cpu_model)
232 long prom_offset, initrd_size, kernel_size;
237 linux_boot = (kernel_filename != NULL);
240 if (cpu_model == NULL)
241 cpu_model = "TI UltraSparc II";
242 env = cpu_init(cpu_model);
244 fprintf(stderr, "Unable to find Sparc CPU definition\n");
247 bh = qemu_bh_new(tick_irq, env);
248 env->tick = ptimer_init(bh);
249 ptimer_set_period(env->tick, 1ULL);
251 bh = qemu_bh_new(stick_irq, env);
252 env->stick = ptimer_init(bh);
253 ptimer_set_period(env->stick, 1ULL);
255 bh = qemu_bh_new(hstick_irq, env);
256 env->hstick = ptimer_init(bh);
257 ptimer_set_period(env->hstick, 1ULL);
258 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
259 qemu_register_reset(main_cpu_reset, env);
263 cpu_register_physical_memory(0, ram_size, 0);
265 prom_offset = ram_size + vga_ram_size;
266 cpu_register_physical_memory(PROM_ADDR,
267 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
268 prom_offset | IO_MEM_ROM);
270 if (bios_name == NULL)
271 bios_name = PROM_FILENAME;
272 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
273 ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
275 fprintf(stderr, "qemu: could not load prom '%s'\n",
283 /* XXX: put correct offset */
284 kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
286 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
288 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
289 if (kernel_size < 0) {
290 fprintf(stderr, "qemu: could not load kernel '%s'\n",
296 if (initrd_filename) {
297 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
298 if (initrd_size < 0) {
299 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
304 if (initrd_size > 0) {
305 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
306 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
307 == 0x48647253) { // HdrS
308 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
309 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
315 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
316 isa_mem_base = VGA_BASE;
317 pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
319 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
321 serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
325 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
326 if (parallel_hds[i]) {
327 parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
331 for(i = 0; i < nb_nics; i++) {
332 if (!nd_table[i].model)
333 nd_table[i].model = "ne2k_pci";
334 pci_nic_init(pci_bus, &nd_table[i], -1);
337 irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
338 // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
339 pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
340 /* FIXME: wire up interrupts. */
341 i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
342 floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
343 nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
344 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
345 KERNEL_LOAD_ADDR, kernel_size,
347 INITRD_LOAD_ADDR, initrd_size,
348 /* XXX: need an option to load a NVRAM image */
350 graphic_width, graphic_height, graphic_depth);
354 QEMUMachine sun4u_machine = {