2 * QEMU Sun4u System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu-timer.h"
33 #include "firmware_abi.h"
35 #define KERNEL_LOAD_ADDR 0x00404000
36 #define CMDLINE_ADDR 0x003ff000
37 #define INITRD_LOAD_ADDR 0x00300000
38 #define PROM_SIZE_MAX (4 * 1024 * 1024)
39 #define PROM_ADDR 0x1fff0000000ULL
40 #define PROM_VADDR 0x000ffd00000ULL
41 #define APB_SPECIAL_BASE 0x1fe00000000ULL
42 #define APB_MEM_BASE 0x1ff00000000ULL
43 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
44 #define PROM_FILENAME "openbios-sparc64"
45 #define NVRAM_SIZE 0x2000
48 int DMA_get_channel_mode (int nchan)
52 int DMA_read_memory (int nchan, void *buf, int pos, int size)
56 int DMA_write_memory (int nchan, void *buf, int pos, int size)
60 void DMA_hold_DREQ (int nchan) {}
61 void DMA_release_DREQ (int nchan) {}
62 void DMA_schedule(int nchan) {}
63 void DMA_run (void) {}
64 void DMA_init (int high_page_enable) {}
65 void DMA_register_channel (int nchan,
66 DMA_transfer_handler transfer_handler,
71 static int nvram_boot_set(void *opaque, const char *boot_device)
74 uint8_t image[sizeof(ohwcfg_v3_t)];
75 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
76 m48t59_t *nvram = (m48t59_t *)opaque;
78 for (i = 0; i < sizeof(image); i++)
79 image[i] = m48t59_read(nvram, i) & 0xff;
81 strcpy((char *)header->boot_devices, boot_device);
82 header->nboot_devices = strlen(boot_device) & 0xff;
83 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
85 for (i = 0; i < sizeof(image); i++)
86 m48t59_write(nvram, i, image[i]);
93 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
96 const char *boot_devices,
97 uint32_t kernel_image, uint32_t kernel_size,
99 uint32_t initrd_image, uint32_t initrd_size,
100 uint32_t NVRAM_image,
101 int width, int height, int depth,
102 const uint8_t *macaddr)
106 uint8_t image[0x1ff0];
107 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
108 struct sparc_arch_cfg *sparc_header;
109 struct OpenBIOS_nvpart_v1 *part_header;
111 memset(image, '\0', sizeof(image));
113 // Try to match PPC NVRAM
114 strcpy((char *)header->struct_ident, "QEMU_BIOS");
115 header->struct_version = cpu_to_be32(3); /* structure v3 */
117 header->nvram_size = cpu_to_be16(NVRAM_size);
118 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
119 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
120 strcpy((char *)header->arch, arch);
121 header->nb_cpus = smp_cpus & 0xff;
122 header->RAM0_base = 0;
123 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
124 strcpy((char *)header->boot_devices, boot_devices);
125 header->nboot_devices = strlen(boot_devices) & 0xff;
126 header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
127 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
129 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
130 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
131 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
133 header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
134 header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
135 header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
137 header->width = cpu_to_be16(width);
138 header->height = cpu_to_be16(height);
139 header->depth = cpu_to_be16(depth);
141 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
143 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
145 // Architecture specific header
146 start = sizeof(ohwcfg_v3_t);
147 sparc_header = (struct sparc_arch_cfg *)&image[start];
148 sparc_header->valid = 0;
149 start += sizeof(struct sparc_arch_cfg);
151 // OpenBIOS nvram variables
152 // Variable partition
153 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
154 part_header->signature = OPENBIOS_PART_SYSTEM;
155 strcpy(part_header->name, "system");
157 end = start + sizeof(struct OpenBIOS_nvpart_v1);
158 for (i = 0; i < nb_prom_envs; i++)
159 end = OpenBIOS_set_var(image, end, prom_envs[i]);
164 end = start + ((end - start + 15) & ~15);
165 OpenBIOS_finish_partition(part_header, end - start);
169 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
170 part_header->signature = OPENBIOS_PART_FREE;
171 strcpy(part_header->name, "free");
174 OpenBIOS_finish_partition(part_header, end - start);
176 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
178 for (i = 0; i < sizeof(image); i++)
179 m48t59_write(nvram, i, image[i]);
181 qemu_register_boot_set(nvram_boot_set, nvram);
194 void qemu_system_powerdown(void)
198 static void main_cpu_reset(void *opaque)
200 CPUState *env = opaque;
203 ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
204 ptimer_run(env->tick, 0);
205 ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
206 ptimer_run(env->stick, 0);
207 ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
208 ptimer_run(env->hstick, 0);
211 static void tick_irq(void *opaque)
213 CPUState *env = opaque;
215 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
218 static void stick_irq(void *opaque)
220 CPUState *env = opaque;
222 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
225 static void hstick_irq(void *opaque)
227 CPUState *env = opaque;
229 cpu_interrupt(env, CPU_INTERRUPT_TIMER);
232 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
236 static const int ide_iobase[2] = { 0x1f0, 0x170 };
237 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
238 static const int ide_irq[2] = { 14, 15 };
240 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
241 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
243 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
244 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
246 static fdctrl_t *floppy_controller;
248 /* Sun4u hardware initialisation */
249 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
250 const char *boot_devices, DisplayState *ds,
251 const char *kernel_filename, const char *kernel_cmdline,
252 const char *initrd_filename, const char *cpu_model)
259 long prom_offset, initrd_size, kernel_size;
264 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
265 BlockDriverState *fd[MAX_FD];
267 linux_boot = (kernel_filename != NULL);
270 if (cpu_model == NULL)
271 cpu_model = "TI UltraSparc II";
272 env = cpu_init(cpu_model);
274 fprintf(stderr, "Unable to find Sparc CPU definition\n");
277 bh = qemu_bh_new(tick_irq, env);
278 env->tick = ptimer_init(bh);
279 ptimer_set_period(env->tick, 1ULL);
281 bh = qemu_bh_new(stick_irq, env);
282 env->stick = ptimer_init(bh);
283 ptimer_set_period(env->stick, 1ULL);
285 bh = qemu_bh_new(hstick_irq, env);
286 env->hstick = ptimer_init(bh);
287 ptimer_set_period(env->hstick, 1ULL);
288 qemu_register_reset(main_cpu_reset, env);
292 cpu_register_physical_memory(0, RAM_size, 0);
294 prom_offset = RAM_size + vga_ram_size;
295 cpu_register_physical_memory(PROM_ADDR,
296 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
298 prom_offset | IO_MEM_ROM);
300 if (bios_name == NULL)
301 bios_name = PROM_FILENAME;
302 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
303 ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
305 fprintf(stderr, "qemu: could not load prom '%s'\n",
313 /* XXX: put correct offset */
314 kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
316 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
317 ram_size - KERNEL_LOAD_ADDR);
319 kernel_size = load_image_targphys(kernel_filename,
321 ram_size - KERNEL_LOAD_ADDR);
322 if (kernel_size < 0) {
323 fprintf(stderr, "qemu: could not load kernel '%s'\n",
329 if (initrd_filename) {
330 initrd_size = load_image_targphys(initrd_filename,
332 ram_size - INITRD_LOAD_ADDR);
333 if (initrd_size < 0) {
334 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
339 if (initrd_size > 0) {
340 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
341 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
342 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
343 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
349 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
350 isa_mem_base = VGA_BASE;
351 pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
354 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
356 serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
361 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
362 if (parallel_hds[i]) {
363 parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
368 for(i = 0; i < nb_nics; i++) {
369 if (!nd_table[i].model)
370 nd_table[i].model = "ne2k_pci";
371 pci_nic_init(pci_bus, &nd_table[i], -1);
374 irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
375 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
376 fprintf(stderr, "qemu: too many IDE bus\n");
379 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
380 drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
382 if (drive_index != -1)
383 hd[i] = drives_table[drive_index].bdrv;
388 // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
389 pci_piix3_ide_init(pci_bus, hd, -1, irq);
390 /* FIXME: wire up interrupts. */
391 i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
392 for(i = 0; i < MAX_FD; i++) {
393 drive_index = drive_get_index(IF_FLOPPY, 0, i);
394 if (drive_index != -1)
395 fd[i] = drives_table[drive_index].bdrv;
399 floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
400 nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
401 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
402 KERNEL_LOAD_ADDR, kernel_size,
404 INITRD_LOAD_ADDR, initrd_size,
405 /* XXX: need an option to load a NVRAM image */
407 graphic_width, graphic_height, graphic_depth,
408 (uint8_t *)&nd_table[0].macaddr);
412 QEMUMachine sun4u_machine = {
416 PROM_SIZE_MAX + VGA_RAM_SIZE,