2 * QEMU Sun4u System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #define KERNEL_LOAD_ADDR 0x00404000
28 #define CMDLINE_ADDR 0x003ff000
29 #define INITRD_LOAD_ADDR 0x00300000
30 #define PROM_SIZE_MAX (256 * 1024)
31 #define PROM_ADDR 0x1fff0000000ULL
32 #define APB_SPECIAL_BASE 0x1fe00000000ULL
33 #define APB_MEM_BASE 0x1ff00000000ULL
34 #define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
35 #define PROM_FILENAMEB "proll-sparc64.bin"
36 #define PROM_FILENAMEE "proll-sparc64.elf"
37 #define NVRAM_SIZE 0x2000
41 uint64_t cpu_get_tsc()
43 return qemu_get_clock(vm_clock);
46 int DMA_get_channel_mode (int nchan)
50 int DMA_read_memory (int nchan, void *buf, int pos, int size)
54 int DMA_write_memory (int nchan, void *buf, int pos, int size)
58 void DMA_hold_DREQ (int nchan) {}
59 void DMA_release_DREQ (int nchan) {}
60 void DMA_schedule(int nchan) {}
61 void DMA_run (void) {}
62 void DMA_init (int high_page_enable) {}
63 void DMA_register_channel (int nchan,
64 DMA_transfer_handler transfer_handler,
70 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
72 m48t59_write(nvram, addr, value);
75 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
77 return m48t59_read(nvram, addr);
80 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
82 m48t59_write(nvram, addr, value >> 8);
83 m48t59_write(nvram, addr + 1, value & 0xFF);
86 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
90 tmp = m48t59_read(nvram, addr) << 8;
91 tmp |= m48t59_read(nvram, addr + 1);
96 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
98 m48t59_write(nvram, addr, value >> 24);
99 m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
100 m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
101 m48t59_write(nvram, addr + 3, value & 0xFF);
104 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
108 tmp = m48t59_read(nvram, addr) << 24;
109 tmp |= m48t59_read(nvram, addr + 1) << 16;
110 tmp |= m48t59_read(nvram, addr + 2) << 8;
111 tmp |= m48t59_read(nvram, addr + 3);
116 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
117 const unsigned char *str, uint32_t max)
121 for (i = 0; i < max && str[i] != '\0'; i++) {
122 m48t59_write(nvram, addr + i, str[i]);
124 m48t59_write(nvram, addr + max - 1, '\0');
127 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
132 for (i = 0; i < max; i++) {
133 dst[i] = NVRAM_get_byte(nvram, addr + i);
141 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
144 uint16_t pd, pd1, pd2;
149 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
150 tmp ^= (pd1 << 3) | (pd1 << 8);
151 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
156 uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
159 uint16_t crc = 0xFFFF;
164 for (i = 0; i != count; i++) {
165 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
168 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
174 extern int nographic;
176 int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
177 const unsigned char *arch,
178 uint32_t RAM_size, int boot_device,
179 uint32_t kernel_image, uint32_t kernel_size,
181 uint32_t initrd_image, uint32_t initrd_size,
182 uint32_t NVRAM_image,
183 int width, int height, int depth)
187 /* Set parameters for Open Hack'Ware BIOS */
188 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
189 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
190 NVRAM_set_word(nvram, 0x14, NVRAM_size);
191 NVRAM_set_string(nvram, 0x20, arch, 16);
192 NVRAM_set_byte(nvram, 0x2f, nographic & 0xff);
193 NVRAM_set_lword(nvram, 0x30, RAM_size);
194 NVRAM_set_byte(nvram, 0x34, boot_device);
195 NVRAM_set_lword(nvram, 0x38, kernel_image);
196 NVRAM_set_lword(nvram, 0x3C, kernel_size);
198 /* XXX: put the cmdline in NVRAM too ? */
199 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
200 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
201 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
203 NVRAM_set_lword(nvram, 0x40, 0);
204 NVRAM_set_lword(nvram, 0x44, 0);
206 NVRAM_set_lword(nvram, 0x48, initrd_image);
207 NVRAM_set_lword(nvram, 0x4C, initrd_size);
208 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
210 NVRAM_set_word(nvram, 0x54, width);
211 NVRAM_set_word(nvram, 0x56, height);
212 NVRAM_set_word(nvram, 0x58, depth);
213 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
214 NVRAM_set_word(nvram, 0xFC, crc);
227 void pic_set_irq(int irq, int level)
231 void pic_set_irq_new(void *opaque, int irq, int level)
235 void qemu_system_powerdown(void)
239 static void main_cpu_reset(void *opaque)
241 CPUState *env = opaque;
245 static const int ide_iobase[2] = { 0x1f0, 0x170 };
246 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
247 static const int ide_irq[2] = { 14, 15 };
249 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
250 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
252 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
253 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
255 static fdctrl_t *floppy_controller;
257 /* Sun4u hardware initialisation */
258 static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
259 DisplayState *ds, const char **fd_filename, int snapshot,
260 const char *kernel_filename, const char *kernel_cmdline,
261 const char *initrd_filename)
268 long prom_offset, initrd_size, kernel_size;
271 linux_boot = (kernel_filename != NULL);
274 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
275 qemu_register_reset(main_cpu_reset, env);
278 cpu_register_physical_memory(0, ram_size, 0);
280 prom_offset = ram_size + vga_ram_size;
281 cpu_register_physical_memory(PROM_ADDR,
282 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
283 prom_offset | IO_MEM_ROM);
285 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
286 ret = load_elf(buf, 0, NULL);
288 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
289 ret = load_image(buf, phys_ram_base + prom_offset);
292 fprintf(stderr, "qemu: could not load prom '%s'\n",
300 /* XXX: put correct offset */
301 kernel_size = load_elf(kernel_filename, 0, NULL);
303 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
305 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
306 if (kernel_size < 0) {
307 fprintf(stderr, "qemu: could not load kernel '%s'\n",
313 if (initrd_filename) {
314 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
315 if (initrd_size < 0) {
316 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
321 if (initrd_size > 0) {
322 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
323 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
324 == 0x48647253) { // HdrS
325 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
326 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
332 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
333 isa_mem_base = VGA_BASE;
334 vga_initialize(pci_bus, ds, phys_ram_base + ram_size, ram_size,
336 cpu_register_physical_memory(VGA_BASE, vga_ram_size, ram_size);
337 //pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
339 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
341 serial_init(&pic_set_irq_new, NULL,
342 serial_io[i], serial_irq[i], serial_hds[i]);
346 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
347 if (parallel_hds[i]) {
348 parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
352 for(i = 0; i < nb_nics; i++) {
353 if (!nd_table[i].model)
354 nd_table[i].model = "ne2k_pci";
355 pci_nic_init(pci_bus, &nd_table[i]);
358 pci_cmd646_ide_init(pci_bus, bs_table, 1);
360 floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
361 nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
362 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
363 KERNEL_LOAD_ADDR, kernel_size,
365 INITRD_LOAD_ADDR, initrd_size,
366 /* XXX: need an option to load a NVRAM image */
368 graphic_width, graphic_height, graphic_depth);
372 QEMUMachine sun4u_machine = {