2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-timer.h"
31 #define DPRINTF(fmt, args...) \
32 do { printf("TIMER: " fmt , ##args); } while (0)
34 #define DPRINTF(fmt, args...)
38 * Registers of hardware timer in sun4m.
40 * This is the timer/counter part of chip STP2001 (Slave I/O), also
41 * produced as NCR89C105. See
42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
44 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
45 * are zero. Bit 31 is 1 when count has been reached.
47 * Per-CPU timers interrupt local CPU, system timer uses normal
54 typedef struct SLAVIO_TIMERState {
57 uint32_t count, counthigh, reached;
61 struct SLAVIO_TIMERState *master;
64 unsigned int num_slaves;
65 struct SLAVIO_TIMERState *slave[MAX_CPUS];
69 #define TIMER_MAXADDR 0x1f
70 #define SYS_TIMER_SIZE 0x14
71 #define CPU_TIMER_SIZE 0x10
73 #define SYS_TIMER_OFFSET 0x10000ULL
74 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
77 #define TIMER_COUNTER 1
78 #define TIMER_COUNTER_NORST 2
79 #define TIMER_STATUS 3
82 #define TIMER_COUNT_MASK32 0xfffffe00
83 #define TIMER_LIMIT_MASK32 0x7fffffff
84 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
85 #define TIMER_MAX_COUNT32 0x7ffffe00ULL
86 #define TIMER_REACHED 0x80000000
87 #define TIMER_PERIOD 500ULL // 500ns
88 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
89 #define PERIODS_TO_LIMIT(l) ((l) << 9)
91 static int slavio_timer_is_user(SLAVIO_TIMERState *s)
93 return s->master && (s->master->slave_mode & (1 << s->slave_index));
96 // Update count, set irq, update expire_time
97 // Convert from ptimer countdown units
98 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
102 count = s->limit - PERIODS_TO_LIMIT(ptimer_get_count(s->timer));
103 DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit,
104 s->counthigh, s->count);
105 s->count = count & TIMER_COUNT_MASK32;
106 s->counthigh = count >> 32;
110 static void slavio_timer_irq(void *opaque)
112 SLAVIO_TIMERState *s = opaque;
114 slavio_timer_get_out(s);
115 DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
116 if (!slavio_timer_is_user(s)) {
117 s->reached = TIMER_REACHED;
118 qemu_irq_raise(s->irq);
122 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
124 SLAVIO_TIMERState *s = opaque;
127 saddr = (addr & TIMER_MAXADDR) >> 2;
130 // read limit (system counter mode) or read most signifying
131 // part of counter (user mode)
132 if (slavio_timer_is_user(s)) {
133 // read user timer MSW
134 slavio_timer_get_out(s);
139 qemu_irq_lower(s->irq);
141 ret = s->limit & TIMER_LIMIT_MASK32;
145 // read counter and reached bit (system mode) or read lsbits
146 // of counter (user mode)
147 slavio_timer_get_out(s);
148 if (slavio_timer_is_user(s)) // read user timer LSW
149 ret = s->count & TIMER_COUNT_MASK32;
151 ret = (s->count & TIMER_MAX_COUNT32) | s->reached;
154 // only available in processor counter/timer
155 // read start/stop status
159 // only available in system counter
160 // read user/system mode
164 DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
168 DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
173 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
176 SLAVIO_TIMERState *s = opaque;
179 DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
180 saddr = (addr & TIMER_MAXADDR) >> 2;
183 if (slavio_timer_is_user(s)) {
184 // set user counter MSW, reset counter
185 qemu_irq_lower(s->irq);
186 s->limit = TIMER_MAX_COUNT64;
187 DPRINTF("processor %d user timer reset\n", s->slave_index);
188 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
190 // set limit, reset counter
191 qemu_irq_lower(s->irq);
192 s->limit = val & TIMER_MAX_COUNT32;
193 if (s->limit == 0) /* free-run */
194 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
196 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
200 if (slavio_timer_is_user(s)) {
201 // set user counter LSW, reset counter
202 qemu_irq_lower(s->irq);
203 s->limit = TIMER_MAX_COUNT64;
204 DPRINTF("processor %d user timer reset\n", s->slave_index);
205 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
207 DPRINTF("not user timer\n");
209 case TIMER_COUNTER_NORST:
210 // set limit without resetting counter
211 s->limit = val & TIMER_MAX_COUNT32;
212 if (s->limit == 0) /* free-run */
213 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
215 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 0);
218 if (slavio_timer_is_user(s)) {
219 // start/stop user counter
220 if ((val & 1) && !s->running) {
221 DPRINTF("processor %d user timer started\n", s->slave_index);
222 ptimer_run(s->timer, 0);
224 } else if (!(val & 1) && s->running) {
225 DPRINTF("processor %d user timer stopped\n", s->slave_index);
226 ptimer_stop(s->timer);
232 if (s->master == NULL) {
235 for (i = 0; i < s->num_slaves; i++) {
236 if (val & (1 << i)) {
237 qemu_irq_lower(s->slave[i]->irq);
238 s->slave[i]->limit = -1ULL;
240 if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
241 ptimer_stop(s->slave[i]->timer);
242 ptimer_set_limit(s->slave[i]->timer,
243 LIMIT_TO_PERIODS(s->slave[i]->limit), 1);
244 DPRINTF("processor %d timer changed\n",
245 s->slave[i]->slave_index);
246 ptimer_run(s->slave[i]->timer, 0);
249 s->slave_mode = val & ((1 << s->num_slaves) - 1);
251 DPRINTF("not system timer\n");
254 DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
259 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
260 slavio_timer_mem_readl,
261 slavio_timer_mem_readl,
262 slavio_timer_mem_readl,
265 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
266 slavio_timer_mem_writel,
267 slavio_timer_mem_writel,
268 slavio_timer_mem_writel,
271 static void slavio_timer_save(QEMUFile *f, void *opaque)
273 SLAVIO_TIMERState *s = opaque;
275 qemu_put_be64s(f, &s->limit);
276 qemu_put_be32s(f, &s->count);
277 qemu_put_be32s(f, &s->counthigh);
278 qemu_put_be32(f, 0); // Was irq
279 qemu_put_be32s(f, &s->reached);
280 qemu_put_be32s(f, &s->running);
281 qemu_put_be32s(f, 0); // Was mode
282 qemu_put_ptimer(f, s->timer);
285 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
287 SLAVIO_TIMERState *s = opaque;
293 qemu_get_be64s(f, &s->limit);
294 qemu_get_be32s(f, &s->count);
295 qemu_get_be32s(f, &s->counthigh);
296 qemu_get_be32s(f, &tmp); // Was irq
297 qemu_get_be32s(f, &s->reached);
298 qemu_get_be32s(f, &s->running);
299 qemu_get_be32s(f, &tmp); // Was mode
300 qemu_get_ptimer(f, s->timer);
305 static void slavio_timer_reset(void *opaque)
307 SLAVIO_TIMERState *s = opaque;
309 if (slavio_timer_is_user(s))
310 s->limit = TIMER_MAX_COUNT64;
312 s->limit = TIMER_MAX_COUNT32;
315 ptimer_set_limit(s->timer, LIMIT_TO_PERIODS(s->limit), 1);
316 ptimer_run(s->timer, 0);
318 qemu_irq_lower(s->irq);
321 static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
323 SLAVIO_TIMERState *master,
326 int slavio_timer_io_memory;
327 SLAVIO_TIMERState *s;
330 s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
335 s->slave_index = slave_index;
336 bh = qemu_bh_new(slavio_timer_irq, s);
337 s->timer = ptimer_init(bh);
338 ptimer_set_period(s->timer, TIMER_PERIOD);
340 slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
341 slavio_timer_mem_write, s);
343 cpu_register_physical_memory(addr, CPU_TIMER_SIZE,
344 slavio_timer_io_memory);
346 cpu_register_physical_memory(addr, SYS_TIMER_SIZE,
347 slavio_timer_io_memory);
348 register_savevm("slavio_timer", addr, 2, slavio_timer_save,
349 slavio_timer_load, s);
350 qemu_register_reset(slavio_timer_reset, s);
351 slavio_timer_reset(s);
356 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
357 qemu_irq *cpu_irqs, unsigned int num_cpus)
359 SLAVIO_TIMERState *master;
362 master = slavio_timer_init(base + SYS_TIMER_OFFSET, master_irq, NULL, 0);
364 master->num_slaves = num_cpus;
366 for (i = 0; i < MAX_CPUS; i++) {
367 master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
369 cpu_irqs[i], master, i);