2 * QEMU Sparc SLAVIO serial port emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define DEBUG_SERIAL
31 /* debug keyboard : only mouse */
35 * This is the serial port, mouse and keyboard part of chip STP2001
36 * (Slave I/O), also produced as NCR89C105. See
37 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
39 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
40 * mouse and keyboard ports don't implement all functions and they are
41 * only asynchronous. There is no DMA.
45 typedef struct ChannelState {
49 uint8_t rx, tx, wregs[16], rregs[16];
54 struct ChannelState chn[2];
57 #define SERIAL_MAXADDR 7
59 static void slavio_serial_update_irq(ChannelState *s)
61 if ((s->wregs[1] & 1) && // interrupts enabled
62 (((s->wregs[1] & 2) && s->txint == 1) || // tx ints enabled, pending
63 ((((s->wregs[1] & 0x18) == 8) || ((s->wregs[1] & 0x18) == 0x10)) &&
64 s->rxint == 1) || // rx ints enabled, pending
65 ((s->wregs[15] & 0x80) && (s->rregs[0] & 0x80)))) { // break int e&p
66 pic_set_irq(s->irq, 1);
68 pic_set_irq(s->irq, 0);
72 static void slavio_serial_reset_chn(ChannelState *s)
77 for (i = 0; i < SERIAL_MAXADDR; i++) {
90 s->rxint = s->txint = 0;
93 static void slavio_serial_reset(void *opaque)
95 SerialState *s = opaque;
96 slavio_serial_reset_chn(&s->chn[0]);
97 slavio_serial_reset_chn(&s->chn[1]);
100 static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
102 SerialState *ser = opaque;
108 saddr = (addr & 3) >> 1;
109 channel = (addr & SERIAL_MAXADDR) >> 2;
110 s = &ser->chn[channel];
134 s->wregs[s->reg] = val;
137 switch (val & 0xc0) {
142 slavio_serial_reset_chn(&ser->chn[1]);
145 slavio_serial_reset_chn(&ser->chn[0]);
148 slavio_serial_reset(ser);
161 if (s->wregs[5] & 8) { // tx enabled
164 qemu_chr_write(s->chr, &s->tx, 1);
173 static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
175 SerialState *ser = opaque;
181 saddr = (addr & 3) >> 1;
182 channel = (addr & SERIAL_MAXADDR) >> 2;
183 s = &ser->chn[channel];
186 ret = s->rregs[s->reg];
198 static int serial_can_receive(void *opaque)
200 ChannelState *s = opaque;
201 if (((s->wregs[3] & 1) == 0) // Rx not enabled
202 || ((s->rregs[0] & 1) == 1)) // char already available
208 static void serial_receive_byte(ChannelState *s, int ch)
213 slavio_serial_update_irq(s);
216 static void serial_receive_break(ChannelState *s)
219 slavio_serial_update_irq(s);
222 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
224 ChannelState *s = opaque;
225 serial_receive_byte(s, buf[0]);
228 static void serial_event(void *opaque, int event)
230 ChannelState *s = opaque;
231 if (event == CHR_EVENT_BREAK)
232 serial_receive_break(s);
235 static CPUReadMemoryFunc *slavio_serial_mem_read[3] = {
236 slavio_serial_mem_readb,
237 slavio_serial_mem_readb,
238 slavio_serial_mem_readb,
241 static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = {
242 slavio_serial_mem_writeb,
243 slavio_serial_mem_writeb,
244 slavio_serial_mem_writeb,
247 static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
249 qemu_put_be32s(f, &s->irq);
250 qemu_put_be32s(f, &s->reg);
251 qemu_put_be32s(f, &s->rxint);
252 qemu_put_be32s(f, &s->txint);
253 qemu_put_8s(f, &s->rx);
254 qemu_put_8s(f, &s->tx);
255 qemu_put_buffer(f, s->wregs, 16);
256 qemu_put_buffer(f, s->rregs, 16);
259 static void slavio_serial_save(QEMUFile *f, void *opaque)
261 SerialState *s = opaque;
263 slavio_serial_save_chn(f, &s->chn[0]);
264 slavio_serial_save_chn(f, &s->chn[1]);
267 static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id)
272 qemu_get_be32s(f, &s->irq);
273 qemu_get_be32s(f, &s->reg);
274 qemu_get_be32s(f, &s->rxint);
275 qemu_get_be32s(f, &s->txint);
276 qemu_get_8s(f, &s->rx);
277 qemu_get_8s(f, &s->tx);
278 qemu_get_buffer(f, s->wregs, 16);
279 qemu_get_buffer(f, s->rregs, 16);
283 static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
285 SerialState *s = opaque;
288 ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
291 ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
296 SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2)
298 int slavio_serial_io_memory;
301 s = qemu_mallocz(sizeof(SerialState));
306 s->chn[0].chr = chr1;
307 s->chn[1].chr = chr2;
309 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
310 cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
313 qemu_chr_add_read_handler(chr1, serial_can_receive, serial_receive1, &s->chn[0]);
314 qemu_chr_add_event_handler(chr1, serial_event);
317 qemu_chr_add_read_handler(chr2, serial_can_receive, serial_receive1, &s->chn[1]);
318 qemu_chr_add_event_handler(chr2, serial_event);
320 register_savevm("slavio_serial", base, 1, slavio_serial_save, slavio_serial_load, s);
321 qemu_register_reset(slavio_serial_reset, s);
322 slavio_serial_reset(s);
326 static void sunkbd_event(void *opaque, int ch)
328 ChannelState *s = opaque;
329 // XXX: PC -> Sun Type 5 translation?
330 serial_receive_byte(s, ch);
333 static void sunmouse_event(void *opaque,
334 int dx, int dy, int dz, int buttons_state)
336 ChannelState *s = opaque;
341 serial_receive_byte(s, ch);
344 void slavio_serial_ms_kbd_init(int base, int irq)
346 int slavio_serial_io_memory;
349 s = qemu_mallocz(sizeof(SerialState));
354 s->chn[0].chr = NULL;
355 s->chn[1].chr = NULL;
357 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s);
358 cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory);
360 qemu_add_kbd_event_handler(sunkbd_event, &s->chn[0]);
361 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[1]);
362 qemu_register_reset(slavio_serial_reset, s);
363 slavio_serial_reset(s);