2 * QEMU Sparc SLAVIO aux io port emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 * This is the auxio port, chip control and system control part of
30 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
31 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
33 * This also includes the PMC CPU idle controller.
37 #define MISC_DPRINTF(fmt, args...) \
38 do { printf("MISC: " fmt , ##args); } while (0)
40 #define MISC_DPRINTF(fmt, args...)
43 typedef struct MiscState {
47 uint8_t diag, mctrl, sysctrl;
50 #define MISC_MAXADDR 1
52 static void slavio_misc_update_irq(void *opaque)
54 MiscState *s = opaque;
56 if ((s->aux2 & 0x4) && (s->config & 0x8)) {
57 pic_set_irq(s->irq, 1);
59 pic_set_irq(s->irq, 0);
63 static void slavio_misc_reset(void *opaque)
65 MiscState *s = opaque;
67 // Diagnostic and system control registers not cleared in reset
68 s->config = s->aux1 = s->aux2 = s->mctrl = 0;
71 void slavio_set_power_fail(void *opaque, int power_failing)
73 MiscState *s = opaque;
75 MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
76 if (power_failing && (s->config & 0x8)) {
81 slavio_misc_update_irq(s);
84 static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
86 MiscState *s = opaque;
88 switch (addr & 0xfff0000) {
90 MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
91 s->config = val & 0xff;
92 slavio_misc_update_irq(s);
95 MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
100 MISC_DPRINTF("Write aux2 %2.2x\n", val);
101 val |= s->aux2 & 0x4;
102 if (val & 0x2) // Clear Power Fail int
106 qemu_system_shutdown_request();
107 slavio_misc_update_irq(s);
110 MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
111 s->diag = val & 0xff;
114 MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
115 s->mctrl = val & 0xff;
118 MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);
121 qemu_system_reset_request();
125 MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
128 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
134 static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
136 MiscState *s = opaque;
139 switch (addr & 0xfff0000) {
142 MISC_DPRINTF("Read config %2.2x\n", ret);
146 MISC_DPRINTF("Read aux1 %2.2x\n", ret);
150 MISC_DPRINTF("Read aux2 %2.2x\n", ret);
154 MISC_DPRINTF("Read diag %2.2x\n", ret);
158 MISC_DPRINTF("Read modem control %2.2x\n", ret);
161 MISC_DPRINTF("Read system control %2.2x\n", ret);
165 MISC_DPRINTF("Read power management %2.2x\n", ret);
171 static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
172 slavio_misc_mem_readb,
173 slavio_misc_mem_readb,
174 slavio_misc_mem_readb,
177 static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
178 slavio_misc_mem_writeb,
179 slavio_misc_mem_writeb,
180 slavio_misc_mem_writeb,
183 static void slavio_misc_save(QEMUFile *f, void *opaque)
185 MiscState *s = opaque;
187 qemu_put_be32s(f, &s->irq);
188 qemu_put_8s(f, &s->config);
189 qemu_put_8s(f, &s->aux1);
190 qemu_put_8s(f, &s->aux2);
191 qemu_put_8s(f, &s->diag);
192 qemu_put_8s(f, &s->mctrl);
193 qemu_put_8s(f, &s->sysctrl);
196 static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
198 MiscState *s = opaque;
203 qemu_get_be32s(f, &s->irq);
204 qemu_get_8s(f, &s->config);
205 qemu_get_8s(f, &s->aux1);
206 qemu_get_8s(f, &s->aux2);
207 qemu_get_8s(f, &s->diag);
208 qemu_get_8s(f, &s->mctrl);
209 qemu_get_8s(f, &s->sysctrl);
213 void *slavio_misc_init(uint32_t base, int irq)
215 int slavio_misc_io_memory;
218 s = qemu_mallocz(sizeof(MiscState));
222 slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);
224 cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory);
226 cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory);
228 cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory);
230 cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory);
232 cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory);
234 cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);
236 cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);
240 register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s);
241 qemu_register_reset(slavio_misc_reset, s);
242 slavio_misc_reset(s);