2 * QEMU 16450 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define DEBUG_SERIAL
28 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
30 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
31 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
32 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
33 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
35 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
36 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
38 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
39 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
40 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
41 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
44 * These are the definitions for the Modem Control Register
46 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
47 #define UART_MCR_OUT2 0x08 /* Out2 complement */
48 #define UART_MCR_OUT1 0x04 /* Out1 complement */
49 #define UART_MCR_RTS 0x02 /* RTS complement */
50 #define UART_MCR_DTR 0x01 /* DTR complement */
53 * These are the definitions for the Modem Status Register
55 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
56 #define UART_MSR_RI 0x40 /* Ring Indicator */
57 #define UART_MSR_DSR 0x20 /* Data Set Ready */
58 #define UART_MSR_CTS 0x10 /* Clear to Send */
59 #define UART_MSR_DDCD 0x08 /* Delta DCD */
60 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
61 #define UART_MSR_DDSR 0x02 /* Delta DSR */
62 #define UART_MSR_DCTS 0x01 /* Delta CTS */
63 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
65 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
66 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
67 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
68 #define UART_LSR_FE 0x08 /* Frame error indicator */
69 #define UART_LSR_PE 0x04 /* Parity error indicator */
70 #define UART_LSR_OE 0x02 /* Overrun error indicator */
71 #define UART_LSR_DR 0x01 /* Receiver data ready */
75 uint8_t rbr; /* receive register */
77 uint8_t iir; /* read only */
80 uint8_t lsr; /* read only */
83 /* NOTE: this hidden state is necessary for tx irq generation as
84 it can be reset while reading iir */
88 int last_break_enable;
91 static void serial_update_irq(SerialState *s)
93 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
94 s->iir = UART_IIR_RDI;
95 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
96 s->iir = UART_IIR_THRI;
98 s->iir = UART_IIR_NO_INT;
100 if (s->iir != UART_IIR_NO_INT) {
101 pic_set_irq(s->irq, 1);
103 pic_set_irq(s->irq, 0);
107 static void serial_update_parameters(SerialState *s)
109 int speed, parity, data_bits, stop_bits;
123 data_bits = (s->lcr & 0x03) + 5;
126 speed = 115200 / s->divider;
128 printf("speed=%d parity=%c data=%d stop=%d\n",
129 speed, parity, data_bits, stop_bits);
133 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
135 SerialState *s = opaque;
140 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
145 if (s->lcr & UART_LCR_DLAB) {
146 s->divider = (s->divider & 0xff00) | val;
147 serial_update_parameters(s);
150 s->lsr &= ~UART_LSR_THRE;
151 serial_update_irq(s);
153 qemu_chr_write(s->chr, &ch, 1);
155 s->lsr |= UART_LSR_THRE;
156 s->lsr |= UART_LSR_TEMT;
157 serial_update_irq(s);
161 if (s->lcr & UART_LCR_DLAB) {
162 s->divider = (s->divider & 0x00ff) | (val << 8);
163 serial_update_parameters(s);
166 if (s->lsr & UART_LSR_THRE) {
169 serial_update_irq(s);
178 serial_update_parameters(s);
179 break_enable = (val >> 6) & 1;
180 if (break_enable != s->last_break_enable) {
181 s->last_break_enable = break_enable;
182 qemu_chr_set_serial_break(s, break_enable);
200 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
202 SerialState *s = opaque;
209 if (s->lcr & UART_LCR_DLAB) {
210 ret = s->divider & 0xff;
213 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
214 serial_update_irq(s);
218 if (s->lcr & UART_LCR_DLAB) {
219 ret = (s->divider >> 8) & 0xff;
226 /* reset THR pending bit */
227 if ((ret & 0x7) == UART_IIR_THRI)
229 serial_update_irq(s);
241 if (s->mcr & UART_MCR_LOOP) {
242 /* in loopback, the modem output pins are connected to the
244 ret = (s->mcr & 0x0c) << 4;
245 ret |= (s->mcr & 0x02) << 3;
246 ret |= (s->mcr & 0x01) << 5;
256 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
261 static int serial_can_receive(SerialState *s)
263 return !(s->lsr & UART_LSR_DR);
266 static void serial_receive_byte(SerialState *s, int ch)
269 s->lsr |= UART_LSR_DR;
270 serial_update_irq(s);
273 static void serial_receive_break(SerialState *s)
276 s->lsr |= UART_LSR_BI | UART_LSR_DR;
277 serial_update_irq(s);
280 static int serial_can_receive1(void *opaque)
282 SerialState *s = opaque;
283 return serial_can_receive(s);
286 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
288 SerialState *s = opaque;
289 serial_receive_byte(s, buf[0]);
292 static void serial_event(void *opaque, int event)
294 SerialState *s = opaque;
295 if (event == CHR_EVENT_BREAK)
296 serial_receive_break(s);
299 static void serial_save(QEMUFile *f, void *opaque)
301 SerialState *s = opaque;
303 qemu_put_8s(f,&s->divider);
304 qemu_put_8s(f,&s->rbr);
305 qemu_put_8s(f,&s->ier);
306 qemu_put_8s(f,&s->iir);
307 qemu_put_8s(f,&s->lcr);
308 qemu_put_8s(f,&s->mcr);
309 qemu_put_8s(f,&s->lsr);
310 qemu_put_8s(f,&s->msr);
311 qemu_put_8s(f,&s->scr);
314 static int serial_load(QEMUFile *f, void *opaque, int version_id)
316 SerialState *s = opaque;
321 qemu_get_8s(f,&s->divider);
322 qemu_get_8s(f,&s->rbr);
323 qemu_get_8s(f,&s->ier);
324 qemu_get_8s(f,&s->iir);
325 qemu_get_8s(f,&s->lcr);
326 qemu_get_8s(f,&s->mcr);
327 qemu_get_8s(f,&s->lsr);
328 qemu_get_8s(f,&s->msr);
329 qemu_get_8s(f,&s->scr);
334 /* If fd is zero, it means that the serial device uses the console */
335 SerialState *serial_init(int base, int irq, CharDriverState *chr)
339 s = qemu_mallocz(sizeof(SerialState));
343 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
344 s->iir = UART_IIR_NO_INT;
346 register_savevm("serial", base, 1, serial_save, serial_load, s);
348 register_ioport_write(base, 8, 1, serial_ioport_write, s);
349 register_ioport_read(base, 8, 1, serial_ioport_read, s);
351 qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
352 qemu_chr_add_event_handler(chr, serial_event);