2 * QEMU 16450 UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 //#define DEBUG_SERIAL
28 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
30 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
31 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
32 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
33 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
35 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
36 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
38 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
39 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
40 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
41 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
44 * These are the definitions for the Modem Control Register
46 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
47 #define UART_MCR_OUT2 0x08 /* Out2 complement */
48 #define UART_MCR_OUT1 0x04 /* Out1 complement */
49 #define UART_MCR_RTS 0x02 /* RTS complement */
50 #define UART_MCR_DTR 0x01 /* DTR complement */
53 * These are the definitions for the Modem Status Register
55 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
56 #define UART_MSR_RI 0x40 /* Ring Indicator */
57 #define UART_MSR_DSR 0x20 /* Data Set Ready */
58 #define UART_MSR_CTS 0x10 /* Clear to Send */
59 #define UART_MSR_DDCD 0x08 /* Delta DCD */
60 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
61 #define UART_MSR_DDSR 0x02 /* Delta DSR */
62 #define UART_MSR_DCTS 0x01 /* Delta CTS */
63 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
65 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
66 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
67 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
68 #define UART_LSR_FE 0x08 /* Frame error indicator */
69 #define UART_LSR_PE 0x04 /* Parity error indicator */
70 #define UART_LSR_OE 0x02 /* Overrun error indicator */
71 #define UART_LSR_DR 0x01 /* Receiver data ready */
75 uint8_t rbr; /* receive register */
77 uint8_t iir; /* read only */
80 uint8_t lsr; /* read only */
83 /* NOTE: this hidden state is necessary for tx irq generation as
84 it can be reset while reading iir */
90 int last_break_enable;
95 static void serial_update_irq(SerialState *s)
97 if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
98 s->iir = UART_IIR_RDI;
99 } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
100 s->iir = UART_IIR_THRI;
102 s->iir = UART_IIR_NO_INT;
104 if (s->iir != UART_IIR_NO_INT) {
105 s->set_irq(s->irq_opaque, s->irq, 1);
107 s->set_irq(s->irq_opaque, s->irq, 0);
111 static void serial_update_parameters(SerialState *s)
113 int speed, parity, data_bits, stop_bits;
114 QEMUSerialSetParams ssp;
128 data_bits = (s->lcr & 0x03) + 5;
131 speed = 115200 / s->divider;
134 ssp.data_bits = data_bits;
135 ssp.stop_bits = stop_bits;
136 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
138 printf("speed=%d parity=%c data=%d stop=%d\n",
139 speed, parity, data_bits, stop_bits);
143 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
145 SerialState *s = opaque;
150 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
155 if (s->lcr & UART_LCR_DLAB) {
156 s->divider = (s->divider & 0xff00) | val;
157 serial_update_parameters(s);
160 s->lsr &= ~UART_LSR_THRE;
161 serial_update_irq(s);
163 qemu_chr_write(s->chr, &ch, 1);
165 s->lsr |= UART_LSR_THRE;
166 s->lsr |= UART_LSR_TEMT;
167 serial_update_irq(s);
171 if (s->lcr & UART_LCR_DLAB) {
172 s->divider = (s->divider & 0x00ff) | (val << 8);
173 serial_update_parameters(s);
176 if (s->lsr & UART_LSR_THRE) {
179 serial_update_irq(s);
188 serial_update_parameters(s);
189 break_enable = (val >> 6) & 1;
190 if (break_enable != s->last_break_enable) {
191 s->last_break_enable = break_enable;
192 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
211 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
213 SerialState *s = opaque;
220 if (s->lcr & UART_LCR_DLAB) {
221 ret = s->divider & 0xff;
224 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
225 serial_update_irq(s);
229 if (s->lcr & UART_LCR_DLAB) {
230 ret = (s->divider >> 8) & 0xff;
237 /* reset THR pending bit */
238 if ((ret & 0x7) == UART_IIR_THRI)
240 serial_update_irq(s);
252 if (s->mcr & UART_MCR_LOOP) {
253 /* in loopback, the modem output pins are connected to the
255 ret = (s->mcr & 0x0c) << 4;
256 ret |= (s->mcr & 0x02) << 3;
257 ret |= (s->mcr & 0x01) << 5;
267 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
272 static int serial_can_receive(SerialState *s)
274 return !(s->lsr & UART_LSR_DR);
277 static void serial_receive_byte(SerialState *s, int ch)
280 s->lsr |= UART_LSR_DR;
281 serial_update_irq(s);
284 static void serial_receive_break(SerialState *s)
287 s->lsr |= UART_LSR_BI | UART_LSR_DR;
288 serial_update_irq(s);
291 static int serial_can_receive1(void *opaque)
293 SerialState *s = opaque;
294 return serial_can_receive(s);
297 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
299 SerialState *s = opaque;
300 serial_receive_byte(s, buf[0]);
303 static void serial_event(void *opaque, int event)
305 SerialState *s = opaque;
306 if (event == CHR_EVENT_BREAK)
307 serial_receive_break(s);
310 static void serial_save(QEMUFile *f, void *opaque)
312 SerialState *s = opaque;
314 qemu_put_8s(f,&s->divider);
315 qemu_put_8s(f,&s->rbr);
316 qemu_put_8s(f,&s->ier);
317 qemu_put_8s(f,&s->iir);
318 qemu_put_8s(f,&s->lcr);
319 qemu_put_8s(f,&s->mcr);
320 qemu_put_8s(f,&s->lsr);
321 qemu_put_8s(f,&s->msr);
322 qemu_put_8s(f,&s->scr);
325 static int serial_load(QEMUFile *f, void *opaque, int version_id)
327 SerialState *s = opaque;
332 qemu_get_8s(f,&s->divider);
333 qemu_get_8s(f,&s->rbr);
334 qemu_get_8s(f,&s->ier);
335 qemu_get_8s(f,&s->iir);
336 qemu_get_8s(f,&s->lcr);
337 qemu_get_8s(f,&s->mcr);
338 qemu_get_8s(f,&s->lsr);
339 qemu_get_8s(f,&s->msr);
340 qemu_get_8s(f,&s->scr);
345 /* If fd is zero, it means that the serial device uses the console */
346 SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
347 int base, int irq, CharDriverState *chr)
351 s = qemu_mallocz(sizeof(SerialState));
354 s->set_irq = set_irq;
355 s->irq_opaque = opaque;
357 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
358 s->iir = UART_IIR_NO_INT;
360 register_savevm("serial", base, 1, serial_save, serial_load, s);
362 register_ioport_write(base, 8, 1, serial_ioport_write, s);
363 register_ioport_read(base, 8, 1, serial_ioport_read, s);
365 qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
366 qemu_chr_add_event_handler(chr, serial_event);
370 /* Memory mapped interface */
371 static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
373 SerialState *s = opaque;
375 return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
378 static void serial_mm_writeb (void *opaque,
379 target_phys_addr_t addr, uint32_t value)
381 SerialState *s = opaque;
383 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
386 static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
388 SerialState *s = opaque;
390 return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
393 static void serial_mm_writew (void *opaque,
394 target_phys_addr_t addr, uint32_t value)
396 SerialState *s = opaque;
398 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
401 static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
403 SerialState *s = opaque;
405 return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
408 static void serial_mm_writel (void *opaque,
409 target_phys_addr_t addr, uint32_t value)
411 SerialState *s = opaque;
413 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
416 static CPUReadMemoryFunc *serial_mm_read[] = {
422 static CPUWriteMemoryFunc *serial_mm_write[] = {
428 SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
429 target_ulong base, int it_shift,
430 int irq, CharDriverState *chr)
435 s = qemu_mallocz(sizeof(SerialState));
438 s->set_irq = set_irq;
439 s->irq_opaque = opaque;
441 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
442 s->iir = UART_IIR_NO_INT;
444 s->it_shift = it_shift;
446 register_savevm("serial", base, 1, serial_save, serial_load, s);
448 s_io_memory = cpu_register_io_memory(0, serial_mm_read,
450 cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
452 qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
453 qemu_chr_add_event_handler(chr, serial_event);