2 * QEMU PowerPC 4xx embedded processors shared devices emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 //#define DEBUG_UNASSIGNED
34 /*****************************************************************************/
35 /* Generic PowerPC 4xx processor instanciation */
36 CPUState *ppc4xx_init (const char *cpu_model,
37 clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
43 env = cpu_init(cpu_model);
45 fprintf(stderr, "Unable to find PowerPC %s CPU definition\n",
49 cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
50 cpu_clk->opaque = env;
51 /* Set time-base frequency to sysclk */
52 tb_clk->cb = ppc_emb_timers_init(env, sysclk);
54 ppc_dcr_init(env, NULL, NULL);
55 /* Register qemu callbacks */
56 qemu_register_reset(&cpu_ppc_reset, env);
61 /*****************************************************************************/
62 /* Fake device used to map multiple devices in a single memory page */
63 #define MMIO_AREA_BITS 8
64 #define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)
65 #define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))
66 #define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))
67 struct ppc4xx_mmio_t {
68 target_phys_addr_t base;
69 CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];
70 CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];
71 void *opaque[MMIO_AREA_NB];
74 static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)
76 #ifdef DEBUG_UNASSIGNED
80 printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",
87 static void unassigned_mmio_writeb (void *opaque,
88 target_phys_addr_t addr, uint32_t val)
90 #ifdef DEBUG_UNASSIGNED
94 printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",
95 addr, val, mmio->base);
99 static CPUReadMemoryFunc *unassigned_mmio_read[3] = {
100 unassigned_mmio_readb,
101 unassigned_mmio_readb,
102 unassigned_mmio_readb,
105 static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {
106 unassigned_mmio_writeb,
107 unassigned_mmio_writeb,
108 unassigned_mmio_writeb,
111 static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,
112 target_phys_addr_t addr, int len)
114 CPUReadMemoryFunc **mem_read;
118 idx = MMIO_IDX(addr - mmio->base);
119 #if defined(DEBUG_MMIO)
120 printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,
121 mmio, len, addr, idx);
123 mem_read = mmio->mem_read[idx];
124 ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);
129 static void mmio_writelen (ppc4xx_mmio_t *mmio,
130 target_phys_addr_t addr, uint32_t value, int len)
132 CPUWriteMemoryFunc **mem_write;
135 idx = MMIO_IDX(addr - mmio->base);
136 #if defined(DEBUG_MMIO)
137 printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n",
138 __func__, mmio, len, addr, idx, value);
140 mem_write = mmio->mem_write[idx];
141 (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);
144 static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)
146 #if defined(DEBUG_MMIO)
147 printf("%s: addr " PADDRX "\n", __func__, addr);
150 return mmio_readlen(opaque, addr, 0);
153 static void mmio_writeb (void *opaque,
154 target_phys_addr_t addr, uint32_t value)
156 #if defined(DEBUG_MMIO)
157 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
159 mmio_writelen(opaque, addr, value, 0);
162 static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)
164 #if defined(DEBUG_MMIO)
165 printf("%s: addr " PADDRX "\n", __func__, addr);
168 return mmio_readlen(opaque, addr, 1);
171 static void mmio_writew (void *opaque,
172 target_phys_addr_t addr, uint32_t value)
174 #if defined(DEBUG_MMIO)
175 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
177 mmio_writelen(opaque, addr, value, 1);
180 static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)
182 #if defined(DEBUG_MMIO)
183 printf("%s: addr " PADDRX "\n", __func__, addr);
186 return mmio_readlen(opaque, addr, 2);
189 static void mmio_writel (void *opaque,
190 target_phys_addr_t addr, uint32_t value)
192 #if defined(DEBUG_MMIO)
193 printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);
195 mmio_writelen(opaque, addr, value, 2);
198 static CPUReadMemoryFunc *mmio_read[] = {
204 static CPUWriteMemoryFunc *mmio_write[] = {
210 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
211 target_phys_addr_t offset, uint32_t len,
212 CPUReadMemoryFunc **mem_read,
213 CPUWriteMemoryFunc **mem_write, void *opaque)
215 target_phys_addr_t end;
218 if ((offset + len) > TARGET_PAGE_SIZE)
220 idx = MMIO_IDX(offset);
221 end = offset + len - 1;
222 eidx = MMIO_IDX(end);
223 #if defined(DEBUG_MMIO)
224 printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n",
225 __func__, offset, len, end, idx, eidx);
227 for (; idx <= eidx; idx++) {
228 mmio->mem_read[idx] = mem_read;
229 mmio->mem_write[idx] = mem_write;
230 mmio->opaque[idx] = opaque;
236 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)
241 mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));
244 mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);
245 #if defined(DEBUG_MMIO)
246 printf("%s: base " PADDRX " len %08x %d\n", __func__,
247 base, TARGET_PAGE_SIZE, mmio_memory);
249 cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);
250 ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,
251 unassigned_mmio_read, unassigned_mmio_write,
258 /*****************************************************************************/
259 /* "Universal" Interrupt controller */
273 #define UIC_MAX_IRQ 32
274 typedef struct ppcuic_t ppcuic_t;
278 uint32_t level; /* Remembers the state of level-triggered interrupts. */
279 uint32_t uicsr; /* Status register */
280 uint32_t uicer; /* Enable register */
281 uint32_t uiccr; /* Critical register */
282 uint32_t uicpr; /* Polarity register */
283 uint32_t uictr; /* Triggering register */
284 uint32_t uicvcr; /* Vector configuration register */
289 static void ppcuic_trigger_irq (ppcuic_t *uic)
292 int start, end, inc, i;
294 /* Trigger interrupt if any is pending */
295 ir = uic->uicsr & uic->uicer & (~uic->uiccr);
296 cr = uic->uicsr & uic->uicer & uic->uiccr;
298 if (loglevel & CPU_LOG_INT) {
299 fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
300 " uiccr %08" PRIx32 "\n"
301 " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
302 __func__, uic->uicsr, uic->uicer, uic->uiccr,
303 uic->uicsr & uic->uicer, ir, cr);
306 if (ir != 0x0000000) {
308 if (loglevel & CPU_LOG_INT) {
309 fprintf(logfile, "Raise UIC interrupt\n");
312 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
315 if (loglevel & CPU_LOG_INT) {
316 fprintf(logfile, "Lower UIC interrupt\n");
319 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
321 /* Trigger critical interrupt if any is pending and update vector */
322 if (cr != 0x0000000) {
323 qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);
324 if (uic->use_vectors) {
325 /* Compute critical IRQ vector */
326 if (uic->uicvcr & 1) {
335 uic->uicvr = uic->uicvcr & 0xFFFFFFFC;
336 for (i = start; i <= end; i += inc) {
338 uic->uicvr += (i - start) * 512 * inc;
344 if (loglevel & CPU_LOG_INT) {
345 fprintf(logfile, "Raise UIC critical interrupt - "
346 "vector %08" PRIx32 "\n", uic->uicvr);
351 if (loglevel & CPU_LOG_INT) {
352 fprintf(logfile, "Lower UIC critical interrupt\n");
355 qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
356 uic->uicvr = 0x00000000;
360 static void ppcuic_set_irq (void *opaque, int irq_num, int level)
366 mask = 1 << (31-irq_num);
368 if (loglevel & CPU_LOG_INT) {
369 fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
370 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
371 __func__, irq_num, level,
372 uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
375 if (irq_num < 0 || irq_num > 31)
379 /* Update status register */
380 if (uic->uictr & mask) {
381 /* Edge sensitive interrupt */
385 /* Level sensitive interrupt */
395 if (loglevel & CPU_LOG_INT) {
396 fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
397 "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
400 if (sr != uic->uicsr)
401 ppcuic_trigger_irq(uic);
404 static target_ulong dcr_read_uic (void *opaque, int dcrn)
410 dcrn -= uic->dcr_base;
429 ret = uic->uicsr & uic->uicer;
432 if (!uic->use_vectors)
437 if (!uic->use_vectors)
450 static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
455 dcrn -= uic->dcr_base;
457 if (loglevel & CPU_LOG_INT) {
458 fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
464 uic->uicsr |= uic->level;
465 ppcuic_trigger_irq(uic);
469 ppcuic_trigger_irq(uic);
473 ppcuic_trigger_irq(uic);
477 ppcuic_trigger_irq(uic);
484 ppcuic_trigger_irq(uic);
491 uic->uicvcr = val & 0xFFFFFFFD;
492 ppcuic_trigger_irq(uic);
497 static void ppcuic_reset (void *opaque)
502 uic->uiccr = 0x00000000;
503 uic->uicer = 0x00000000;
504 uic->uicpr = 0x00000000;
505 uic->uicsr = 0x00000000;
506 uic->uictr = 0x00000000;
507 if (uic->use_vectors) {
508 uic->uicvcr = 0x00000000;
509 uic->uicvr = 0x0000000;
513 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
514 uint32_t dcr_base, int has_ssr, int has_vr)
519 uic = qemu_mallocz(sizeof(ppcuic_t));
521 uic->dcr_base = dcr_base;
524 uic->use_vectors = 1;
525 for (i = 0; i < DCR_UICMAX; i++) {
526 ppc_dcr_register(env, dcr_base + i, uic,
527 &dcr_read_uic, &dcr_write_uic);
529 qemu_register_reset(ppcuic_reset, uic);
533 return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);