2 * Arm PrimeCell PL110 Color LCD Controller
4 * Copyright (c) 2005-2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GNU LGPL
11 #include "primecell.h"
14 #define PL110_CR_EN 0x001
15 #define PL110_CR_BGR 0x100
16 #define PL110_CR_BEBO 0x200
17 #define PL110_CR_BEPO 0x400
18 #define PL110_CR_PWR 0x800
33 /* The Versatile/PB uses a slightly modified PL110 controller. */
43 enum pl110_bppmode bpp;
45 uint32_t pallette[256];
46 uint32_t raw_pallette[128];
50 static const unsigned char pl110_id[] =
51 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
53 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
54 has a different ID. However Linux only looks for the normal ID. */
56 static const unsigned char pl110_versatile_id[] =
57 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
59 #define pl110_versatile_id pl110_id
62 #include "pixel_ops.h"
64 typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int);
67 #include "pl110_template.h"
69 #include "pl110_template.h"
71 #include "pl110_template.h"
73 #include "pl110_template.h"
75 #include "pl110_template.h"
77 static int pl110_enabled(pl110_state *s)
79 return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
82 static void pl110_update_display(void *opaque)
84 pl110_state *s = (pl110_state *)opaque;
99 if (!pl110_enabled(s))
102 switch (ds_get_bits_per_pixel(s->ds)) {
106 fntable = pl110_draw_fn_8;
110 fntable = pl110_draw_fn_15;
114 fntable = pl110_draw_fn_16;
118 fntable = pl110_draw_fn_24;
122 fntable = pl110_draw_fn_32;
126 fprintf(stderr, "pl110: Bad color depth\n");
129 if (s->cr & PL110_CR_BGR)
134 if (s->cr & PL110_CR_BEBO)
135 fn = fntable[s->bpp + 6 + bpp_offset];
136 else if (s->cr & PL110_CR_BEPO)
137 fn = fntable[s->bpp + 12 + bpp_offset];
139 fn = fntable[s->bpp + bpp_offset];
161 dest_width *= s->cols;
162 pallette = s->pallette;
164 /* HACK: Arm aliases physical memory at 0x80000000. */
165 if (base > 0x80000000)
167 src = phys_ram_base + base;
168 dest = ds_get_data(s->ds);
172 dirty = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
174 for (i = 0; i < s->rows; i++) {
175 if ((addr & ~TARGET_PAGE_MASK) + src_width >= TARGET_PAGE_SIZE) {
178 for (tmp = 0; tmp < src_width; tmp += TARGET_PAGE_SIZE) {
179 new_dirty |= cpu_physical_memory_get_dirty(addr + tmp,
184 if (dirty || new_dirty || s->invalidate) {
185 fn(pallette, dest, src, s->cols);
199 cpu_physical_memory_reset_dirty(base + first * src_width,
200 base + (last + 1) * src_width,
202 dpy_update(s->ds, 0, first, s->cols, last - first + 1);
205 static void pl110_invalidate_display(void * opaque)
207 pl110_state *s = (pl110_state *)opaque;
211 static void pl110_update_pallette(pl110_state *s, int n)
215 unsigned int r, g, b;
217 raw = s->raw_pallette[n];
219 for (i = 0; i < 2; i++) {
220 r = (raw & 0x1f) << 3;
222 g = (raw & 0x1f) << 3;
224 b = (raw & 0x1f) << 3;
225 /* The I bit is ignored. */
227 switch (ds_get_bits_per_pixel(s->ds)) {
229 s->pallette[n] = rgb_to_pixel8(r, g, b);
232 s->pallette[n] = rgb_to_pixel15(r, g, b);
235 s->pallette[n] = rgb_to_pixel16(r, g, b);
239 s->pallette[n] = rgb_to_pixel32(r, g, b);
246 static void pl110_resize(pl110_state *s, int width, int height)
248 if (width != s->cols || height != s->rows) {
249 if (pl110_enabled(s)) {
250 qemu_console_resize(s->ds, width, height);
257 /* Update interrupts. */
258 static void pl110_update(pl110_state *s)
260 /* TODO: Implement interrupts. */
263 static uint32_t pl110_read(void *opaque, target_phys_addr_t offset)
265 pl110_state *s = (pl110_state *)opaque;
267 if (offset >= 0xfe0 && offset < 0x1000) {
269 return pl110_versatile_id[(offset - 0xfe0) >> 2];
271 return pl110_id[(offset - 0xfe0) >> 2];
273 if (offset >= 0x200 && offset < 0x400) {
274 return s->raw_pallette[(offset - 0x200) >> 2];
276 switch (offset >> 2) {
277 case 0: /* LCDTiming0 */
279 case 1: /* LCDTiming1 */
281 case 2: /* LCDTiming2 */
283 case 3: /* LCDTiming3 */
285 case 4: /* LCDUPBASE */
287 case 5: /* LCDLPBASE */
289 case 6: /* LCDIMSC */
293 case 7: /* LCDControl */
298 return s->int_status;
300 return s->int_status & s->int_mask;
301 case 11: /* LCDUPCURR */
302 /* TODO: Implement vertical refresh. */
304 case 12: /* LCDLPCURR */
307 cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset);
312 static void pl110_write(void *opaque, target_phys_addr_t offset,
315 pl110_state *s = (pl110_state *)opaque;
318 /* For simplicity invalidate the display whenever a control register
321 if (offset >= 0x200 && offset < 0x400) {
323 n = (offset - 0x200) >> 2;
324 s->raw_pallette[(offset - 0x200) >> 2] = val;
325 pl110_update_pallette(s, n);
328 switch (offset >> 2) {
329 case 0: /* LCDTiming0 */
331 n = ((val & 0xfc) + 4) * 4;
332 pl110_resize(s, n, s->rows);
334 case 1: /* LCDTiming1 */
336 n = (val & 0x3ff) + 1;
337 pl110_resize(s, s->cols, n);
339 case 2: /* LCDTiming2 */
342 case 3: /* LCDTiming3 */
345 case 4: /* LCDUPBASE */
348 case 5: /* LCDLPBASE */
351 case 6: /* LCDIMSC */
358 case 7: /* LCDControl */
363 s->bpp = (val >> 1) & 7;
364 if (pl110_enabled(s)) {
365 qemu_console_resize(s->ds, s->cols, s->rows);
368 case 10: /* LCDICR */
369 s->int_status &= ~val;
373 cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset);
377 static CPUReadMemoryFunc *pl110_readfn[] = {
383 static CPUWriteMemoryFunc *pl110_writefn[] = {
389 void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
394 s = (pl110_state *)qemu_mallocz(sizeof(pl110_state));
395 iomemtype = cpu_register_io_memory(0, pl110_readfn,
397 cpu_register_physical_memory(base, 0x00001000, iomemtype);
398 s->versatile = versatile;
400 s->ds = graphic_console_init(pl110_update_display,
401 pl110_invalidate_display,
403 /* ??? Save/restore. */