2 * Arm PrimeCell PL061 General Purpose IO with additional
3 * Luminary Micro Stellaris bits.
5 * Copyright (c) 2007 CodeSourcery.
6 * Written by Paul Brook
8 * This code is licenced under the GPL.
13 //#define DEBUG_PL061 1
16 #define DPRINTF(fmt, args...) \
17 do { printf("pl061: " fmt , ##args); } while (0)
18 #define BADF(fmt, args...) \
19 do { fprintf(stderr, "pl061: error: " fmt , ##args); exit(1);} while (0)
21 #define DPRINTF(fmt, args...) do {} while(0)
22 #define BADF(fmt, args...) \
23 do { fprintf(stderr, "pl061: error: " fmt , ##args);} while (0)
26 static const uint8_t pl061_id[12] =
27 { 0x00, 0x00, 0x00, 0x00, 0x61, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
54 static void pl061_update(pl061_state *s)
60 changed = s->old_data ^ s->data;
64 s->old_data = s->data;
65 for (i = 0; i < 8; i++) {
67 if ((changed & mask & s->dir) && s->out) {
68 DPRINTF("Set output %d = %d\n", i, (s->data & mask) != 0);
69 qemu_set_irq(s->out[i], (s->data & mask) != 0);
73 /* FIXME: Implement input interrupts. */
76 static uint32_t pl061_read(void *opaque, target_phys_addr_t offset)
78 pl061_state *s = (pl061_state *)opaque;
81 if (offset >= 0xfd0 && offset < 0x1000) {
82 return pl061_id[(offset - 0xfd0) >> 2];
85 return s->data & (offset >> 2);
88 case 0x400: /* Direction */
90 case 0x404: /* Interrupt sense */
92 case 0x408: /* Interrupt both edges */
94 case 0x40c: /* Interupt event */
96 case 0x410: /* Interrupt mask */
98 case 0x414: /* Raw interrupt status */
100 case 0x418: /* Masked interrupt status */
101 return s->istate | s->im;
102 case 0x420: /* Alternate function select */
104 case 0x500: /* 2mA drive */
106 case 0x504: /* 4mA drive */
108 case 0x508: /* 8mA drive */
110 case 0x50c: /* Open drain */
112 case 0x510: /* Pull-up */
114 case 0x514: /* Pull-down */
116 case 0x518: /* Slew rate control */
118 case 0x51c: /* Digital enable */
120 case 0x520: /* Lock */
122 case 0x524: /* Commit */
125 cpu_abort (cpu_single_env, "pl061_read: Bad offset %x\n",
131 static void pl061_write(void *opaque, target_phys_addr_t offset,
134 pl061_state *s = (pl061_state *)opaque;
138 if (offset < 0x400) {
139 mask = (offset >> 2) & s->dir;
140 s->data = (s->data & ~mask) | (value & mask);
145 case 0x400: /* Direction */
148 case 0x404: /* Interrupt sense */
151 case 0x408: /* Interrupt both edges */
154 case 0x40c: /* Interupt event */
157 case 0x410: /* Interrupt mask */
160 case 0x41c: /* Interrupt clear */
163 case 0x420: /* Alternate function select */
165 s->afsel = (s->afsel & ~mask) | (value & mask);
167 case 0x500: /* 2mA drive */
170 case 0x504: /* 4mA drive */
173 case 0x508: /* 8mA drive */
176 case 0x50c: /* Open drain */
179 case 0x510: /* Pull-up */
182 case 0x514: /* Pull-down */
185 case 0x518: /* Slew rate control */
188 case 0x51c: /* Digital enable */
191 case 0x520: /* Lock */
192 s->locked = (value != 0xacce551);
194 case 0x524: /* Commit */
199 cpu_abort (cpu_single_env, "pl061_write: Bad offset %x\n",
205 static void pl061_reset(pl061_state *s)
211 void pl061_set_irq(void * opaque, int irq, int level)
213 pl061_state *s = (pl061_state *)opaque;
217 if ((s->dir & mask) == 0) {
225 static CPUReadMemoryFunc *pl061_readfn[] = {
231 static CPUWriteMemoryFunc *pl061_writefn[] = {
237 /* Returns an array of inputs. */
238 qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out)
243 s = (pl061_state *)qemu_mallocz(sizeof(pl061_state));
244 iomemtype = cpu_register_io_memory(0, pl061_readfn,
246 cpu_register_physical_memory(base, 0x00001000, iomemtype);
253 /* ??? Save/restore. */
254 return qemu_allocate_irqs(pl061_set_irq, s, 8);