2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
23 * Supported commands/modes are:
29 * - unlock bypass command
32 * It does not support flash interleaving.
33 * It does not implement boot blocs with reduced size
34 * It does not implement software data protection as found in many real chips
35 * It does not implement erase suspend/resume commands
36 * It does not implement multiple sectors erase
41 #include "qemu-timer.h"
44 //#define PFLASH_DEBUG
46 #define DPRINTF(fmt, args...) \
48 printf("PFLASH: " fmt , ##args); \
51 #define DPRINTF(fmt, args...) do { } while (0)
56 target_phys_addr_t base;
60 int wcycle; /* if 0, the flash is read normally */
67 uint8_t cfi_table[0x52];
74 static void pflash_timer (void *opaque)
76 pflash_t *pfl = opaque;
78 DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
84 cpu_register_physical_memory(pfl->base, pfl->total_len,
85 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
91 static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
97 DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
100 boff = offset & 0xFF;
103 else if (pfl->width == 4)
107 /* This should never happen : reset state & treat it as a read*/
108 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
112 /* We accept reads during second unlock sequence... */
115 /* Flash area read */
120 // DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
123 #if defined(TARGET_WORDS_BIGENDIAN)
124 ret = p[offset] << 8;
125 ret |= p[offset + 1];
128 ret |= p[offset + 1] << 8;
130 // DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
133 #if defined(TARGET_WORDS_BIGENDIAN)
134 ret = p[offset] << 24;
135 ret |= p[offset + 1] << 16;
136 ret |= p[offset + 2] << 8;
137 ret |= p[offset + 3];
140 ret |= p[offset + 1] << 8;
141 ret |= p[offset + 2] << 16;
142 ret |= p[offset + 3] << 24;
144 // DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
153 ret = pfl->ident[boff & 0x01];
156 ret = 0x00; /* Pretend all sectors are unprotected */
160 if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1)
162 ret = pfl->ident[2 + (boff & 0x01)];
167 DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
172 /* Status register read */
174 DPRINTF("%s: status %x\n", __func__, ret);
180 if (boff > pfl->cfi_len)
183 ret = pfl->cfi_table[boff];
190 /* update flash content on disk */
191 static void pflash_update(pflash_t *pfl, int offset,
196 offset_end = offset + size;
197 /* round to sectors */
198 offset = offset >> 9;
199 offset_end = (offset_end + 511) >> 9;
200 bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
201 offset_end - offset);
205 static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
212 /* WARNING: when the memory area is in ROMD mode, the offset is a
213 ram offset, not a physical address */
215 if (pfl->cmd != 0xA0 && cmd == 0xF0) {
217 DPRINTF("%s: flash reset asked (%02x %02x)\n",
218 __func__, pfl->cmd, cmd);
222 DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
223 offset, value, width, pfl->wcycle);
224 if (pfl->wcycle == 0)
225 offset -= (uint32_t)(long)pfl->storage;
229 DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
230 offset, value, width);
231 /* Set the device in I/O access mode */
232 cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
233 boff = offset & (pfl->sector_len - 1);
236 else if (pfl->width == 4)
238 switch (pfl->wcycle) {
240 /* We're in read mode */
242 if (boff == 0x55 && cmd == 0x98) {
244 /* Enter CFI query mode */
249 if (boff != 0x555 || cmd != 0xAA) {
250 DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
251 __func__, boff, cmd, 0x555);
254 DPRINTF("%s: unlock sequence started\n", __func__);
257 /* We started an unlock sequence */
259 if (boff != 0x2AA || cmd != 0x55) {
260 DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
264 DPRINTF("%s: unlock sequence done\n", __func__);
267 /* We finished an unlock sequence */
268 if (!pfl->bypass && boff != 0x555) {
269 DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
281 DPRINTF("%s: starting command %02x\n", __func__, cmd);
284 DPRINTF("%s: unknown command %02x\n", __func__, cmd);
291 /* We need another unlock sequence */
294 DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
295 __func__, offset, value, width);
300 pflash_update(pfl, offset, 1);
303 #if defined(TARGET_WORDS_BIGENDIAN)
304 p[offset] &= value >> 8;
305 p[offset + 1] &= value;
308 p[offset + 1] &= value >> 8;
310 pflash_update(pfl, offset, 2);
313 #if defined(TARGET_WORDS_BIGENDIAN)
314 p[offset] &= value >> 24;
315 p[offset + 1] &= value >> 16;
316 p[offset + 2] &= value >> 8;
317 p[offset + 3] &= value;
320 p[offset + 1] &= value >> 8;
321 p[offset + 2] &= value >> 16;
322 p[offset + 3] &= value >> 24;
324 pflash_update(pfl, offset, 4);
327 pfl->status = 0x00 | ~(value & 0x80);
328 /* Let's pretend write is immediate */
333 if (pfl->bypass && cmd == 0x00) {
334 /* Unlock bypass reset */
337 /* We can enter CFI query mode from autoselect mode */
338 if (boff == 0x55 && cmd == 0x98)
342 DPRINTF("%s: invalid write for command %02x\n",
349 /* Ignore writes while flash data write is occuring */
350 /* As we suppose write is immediate, this should never happen */
355 /* Should never happen */
356 DPRINTF("%s: invalid command state %02x (wc 4)\n",
365 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
370 DPRINTF("%s: start chip erase\n", __func__);
371 memset(pfl->storage, 0xFF, pfl->total_len);
373 pflash_update(pfl, 0, pfl->total_len);
374 /* Let's wait 5 seconds before chip erase is done */
375 qemu_mod_timer(pfl->timer,
376 qemu_get_clock(vm_clock) + (ticks_per_sec * 5));
381 offset &= ~(pfl->sector_len - 1);
382 DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
384 memset(p + offset, 0xFF, pfl->sector_len);
385 pflash_update(pfl, offset, pfl->sector_len);
387 /* Let's wait 1/2 second before sector erase is done */
388 qemu_mod_timer(pfl->timer,
389 qemu_get_clock(vm_clock) + (ticks_per_sec / 2));
392 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
400 /* Ignore writes during chip erase */
403 /* Ignore writes during sector erase */
406 /* Should never happen */
407 DPRINTF("%s: invalid command state %02x (wc 6)\n",
412 case 7: /* Special value for CFI queries */
413 DPRINTF("%s: invalid write in CFI query mode\n", __func__);
416 /* Should never happen */
417 DPRINTF("%s: invalid write state (wc 7)\n", __func__);
426 cpu_register_physical_memory(pfl->base, pfl->total_len,
427 pfl->off | IO_MEM_ROMD | pfl->fl_mem);
440 static uint32_t pflash_readb (void *opaque, target_phys_addr_t addr)
442 return pflash_read(opaque, addr, 1);
445 static uint32_t pflash_readw (void *opaque, target_phys_addr_t addr)
447 pflash_t *pfl = opaque;
449 return pflash_read(pfl, addr, 2);
452 static uint32_t pflash_readl (void *opaque, target_phys_addr_t addr)
454 pflash_t *pfl = opaque;
456 return pflash_read(pfl, addr, 4);
459 static void pflash_writeb (void *opaque, target_phys_addr_t addr,
462 pflash_write(opaque, addr, value, 1);
465 static void pflash_writew (void *opaque, target_phys_addr_t addr,
468 pflash_t *pfl = opaque;
470 pflash_write(pfl, addr, value, 2);
473 static void pflash_writel (void *opaque, target_phys_addr_t addr,
476 pflash_t *pfl = opaque;
478 pflash_write(pfl, addr, value, 4);
481 static CPUWriteMemoryFunc *pflash_write_ops[] = {
487 static CPUReadMemoryFunc *pflash_read_ops[] = {
493 /* Count trailing zeroes of a 32 bits quantity */
494 static int ctz32 (uint32_t n)
519 #if 0 /* This is not necessary as n is never 0 */
527 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
528 BlockDriverState *bs,
529 uint32_t sector_len, int nb_blocs, int width,
530 uint16_t id0, uint16_t id1,
531 uint16_t id2, uint16_t id3)
536 total_len = sector_len * nb_blocs;
537 /* XXX: to be fixed */
539 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
540 total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
543 pfl = qemu_mallocz(sizeof(pflash_t));
546 pfl->storage = phys_ram_base + off;
547 pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops,
550 cpu_register_physical_memory(base, total_len,
551 off | pfl->fl_mem | IO_MEM_ROMD);
554 /* read the initial flash content */
555 bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
557 #if 0 /* XXX: there should be a bit to set up read-only,
558 * the same way the hardware does (with WP pin).
564 pfl->timer = qemu_new_timer(vm_clock, pflash_timer, pfl);
566 pfl->sector_len = sector_len;
567 pfl->total_len = total_len;
576 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
578 /* Standard "QRY" string */
579 pfl->cfi_table[0x10] = 'Q';
580 pfl->cfi_table[0x11] = 'R';
581 pfl->cfi_table[0x12] = 'Y';
582 /* Command set (AMD/Fujitsu) */
583 pfl->cfi_table[0x13] = 0x02;
584 pfl->cfi_table[0x14] = 0x00;
585 /* Primary extended table address (none) */
586 pfl->cfi_table[0x15] = 0x00;
587 pfl->cfi_table[0x16] = 0x00;
588 /* Alternate command set (none) */
589 pfl->cfi_table[0x17] = 0x00;
590 pfl->cfi_table[0x18] = 0x00;
591 /* Alternate extended table (none) */
592 pfl->cfi_table[0x19] = 0x00;
593 pfl->cfi_table[0x1A] = 0x00;
595 pfl->cfi_table[0x1B] = 0x27;
597 pfl->cfi_table[0x1C] = 0x36;
598 /* Vpp min (no Vpp pin) */
599 pfl->cfi_table[0x1D] = 0x00;
600 /* Vpp max (no Vpp pin) */
601 pfl->cfi_table[0x1E] = 0x00;
603 pfl->cfi_table[0x1F] = 0x07;
604 /* Timeout for min size buffer write (16 µs) */
605 pfl->cfi_table[0x20] = 0x04;
606 /* Typical timeout for block erase (512 ms) */
607 pfl->cfi_table[0x21] = 0x09;
608 /* Typical timeout for full chip erase (4096 ms) */
609 pfl->cfi_table[0x22] = 0x0C;
611 pfl->cfi_table[0x23] = 0x01;
612 /* Max timeout for buffer write */
613 pfl->cfi_table[0x24] = 0x04;
614 /* Max timeout for block erase */
615 pfl->cfi_table[0x25] = 0x0A;
616 /* Max timeout for chip erase */
617 pfl->cfi_table[0x26] = 0x0D;
619 pfl->cfi_table[0x27] = ctz32(total_len) + 1;
620 /* Flash device interface (8 & 16 bits) */
621 pfl->cfi_table[0x28] = 0x02;
622 pfl->cfi_table[0x29] = 0x00;
623 /* Max number of bytes in multi-bytes write */
624 /* XXX: disable buffered write as it's not supported */
625 // pfl->cfi_table[0x2A] = 0x05;
626 pfl->cfi_table[0x2A] = 0x00;
627 pfl->cfi_table[0x2B] = 0x00;
628 /* Number of erase block regions (uniform) */
629 pfl->cfi_table[0x2C] = 0x01;
630 /* Erase block region 1 */
631 pfl->cfi_table[0x2D] = nb_blocs - 1;
632 pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
633 pfl->cfi_table[0x2F] = sector_len >> 8;
634 pfl->cfi_table[0x30] = sector_len >> 16;