4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #define PCI_VENDOR_ID 0x00 /* 16 bits */
29 #define PCI_DEVICE_ID 0x02 /* 16 bits */
30 #define PCI_COMMAND 0x04 /* 16 bits */
31 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33 #define PCI_CLASS_DEVICE 0x0a /* Device class */
34 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36 #define PCI_MIN_GNT 0x3e /* 8 bits */
37 #define PCI_MAX_LAT 0x3f /* 8 bits */
39 /* just used for simpler irq handling. */
40 #define PCI_DEVICES_MAX 64
41 #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
46 void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
47 uint32_t config_reg; /* XXX: suppress */
49 SetIRQFunc *low_set_irq;
51 PCIDevice *devices[256];
54 target_phys_addr_t pci_mem_base;
55 static int pci_irq_index;
56 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
57 static PCIBus *first_bus;
59 static PCIBus *pci_register_bus(void)
62 bus = qemu_mallocz(sizeof(PCIBus));
67 void generic_pci_save(QEMUFile* f, void *opaque)
69 PCIDevice* s=(PCIDevice*)opaque;
71 qemu_put_buffer(f, s->config, 256);
74 int generic_pci_load(QEMUFile* f, void *opaque, int version_id)
76 PCIDevice* s=(PCIDevice*)opaque;
81 qemu_get_buffer(f, s->config, 256);
85 /* -1 for devfn means auto assign */
86 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
87 int instance_size, int devfn,
88 PCIConfigReadFunc *config_read,
89 PCIConfigWriteFunc *config_write)
93 if (pci_irq_index >= PCI_DEVICES_MAX)
97 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
98 if (!bus->devices[devfn])
104 pci_dev = qemu_mallocz(instance_size);
108 pci_dev->devfn = devfn;
109 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
112 config_read = pci_default_read_config;
114 config_write = pci_default_write_config;
115 pci_dev->config_read = config_read;
116 pci_dev->config_write = config_write;
117 pci_dev->irq_index = pci_irq_index++;
118 bus->devices[devfn] = pci_dev;
122 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
123 uint32_t size, int type,
124 PCIMapIORegionFunc *map_func)
128 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
130 r = &pci_dev->io_regions[region_num];
134 r->map_func = map_func;
137 static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
143 static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
146 return s->config_reg;
149 static void pci_update_mappings(PCIDevice *d)
153 uint32_t last_addr, new_addr, config_ofs;
155 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
156 for(i = 0; i < PCI_NUM_REGIONS; i++) {
157 r = &d->io_regions[i];
158 if (i == PCI_ROM_SLOT) {
161 config_ofs = 0x10 + i * 4;
164 if (r->type & PCI_ADDRESS_SPACE_IO) {
165 if (cmd & PCI_COMMAND_IO) {
166 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
168 new_addr = new_addr & ~(r->size - 1);
169 last_addr = new_addr + r->size - 1;
170 /* NOTE: we have only 64K ioports on PC */
171 if (last_addr <= new_addr || new_addr == 0 ||
172 last_addr >= 0x10000) {
179 if (cmd & PCI_COMMAND_MEMORY) {
180 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
182 /* the ROM slot has a specific enable bit */
183 if (i == PCI_ROM_SLOT && !(new_addr & 1))
185 new_addr = new_addr & ~(r->size - 1);
186 last_addr = new_addr + r->size - 1;
187 /* NOTE: we do not support wrapping */
188 /* XXX: as we cannot support really dynamic
189 mappings, we handle specific values as invalid
191 if (last_addr <= new_addr || new_addr == 0 ||
200 /* now do the real mapping */
201 if (new_addr != r->addr) {
203 if (r->type & PCI_ADDRESS_SPACE_IO) {
205 /* NOTE: specific hack for IDE in PC case:
206 only one byte must be mapped. */
207 class = d->config[0x0a] | (d->config[0x0b] << 8);
208 if (class == 0x0101 && r->size == 4) {
209 isa_unassign_ioport(r->addr + 2, 1);
211 isa_unassign_ioport(r->addr, r->size);
214 cpu_register_physical_memory(r->addr + pci_mem_base,
221 r->map_func(d, i, r->addr, r->size, r->type);
228 uint32_t pci_default_read_config(PCIDevice *d,
229 uint32_t address, int len)
234 val = d->config[address];
237 val = le16_to_cpu(*(uint16_t *)(d->config + address));
241 val = le32_to_cpu(*(uint32_t *)(d->config + address));
247 void pci_default_write_config(PCIDevice *d,
248 uint32_t address, uint32_t val, int len)
253 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
254 (address >= 0x30 && address < 0x34))) {
258 if ( address >= 0x30 ) {
261 reg = (address - 0x10) >> 2;
263 r = &d->io_regions[reg];
266 /* compute the stored value */
267 if (reg == PCI_ROM_SLOT) {
268 /* keep ROM enable bit */
269 val &= (~(r->size - 1)) | 1;
271 val &= ~(r->size - 1);
274 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
275 pci_update_mappings(d);
279 /* not efficient, but simple */
281 for(i = 0; i < len; i++) {
282 /* default read/write accesses */
283 switch(d->config[0x0e]) {
296 case 0x10 ... 0x27: /* base */
297 case 0x30 ... 0x33: /* rom */
318 case 0x38 ... 0x3b: /* rom */
329 d->config[addr] = val;
336 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
337 /* if the command register is modified, we must modify the mappings */
338 pci_update_mappings(d);
342 static void pci_data_write(void *opaque, uint32_t addr,
343 uint32_t val, int len)
347 int config_addr, bus_num;
349 #if defined(DEBUG_PCI) && 0
350 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
351 s->config_reg, val, len);
353 if (!(s->config_reg & (1 << 31))) {
356 if ((s->config_reg & 0x3) != 0) {
359 bus_num = (s->config_reg >> 16) & 0xff;
362 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
365 config_addr = (s->config_reg & 0xfc) | (addr & 3);
366 #if defined(DEBUG_PCI)
367 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
368 pci_dev->name, config_addr, val, len);
370 pci_dev->config_write(pci_dev, config_addr, val, len);
373 static uint32_t pci_data_read(void *opaque, uint32_t addr,
378 int config_addr, bus_num;
381 if (!(s->config_reg & (1 << 31)))
383 if ((s->config_reg & 0x3) != 0)
385 bus_num = (s->config_reg >> 16) & 0xff;
388 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
405 config_addr = (s->config_reg & 0xfc) | (addr & 3);
406 val = pci_dev->config_read(pci_dev, config_addr, len);
407 #if defined(DEBUG_PCI)
408 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
409 pci_dev->name, config_addr, val, len);
412 #if defined(DEBUG_PCI) && 0
413 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
414 s->config_reg, val, len);
419 static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
421 pci_data_write(opaque, addr, val, 1);
424 static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
426 pci_data_write(opaque, addr, val, 2);
429 static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
431 pci_data_write(opaque, addr, val, 4);
434 static uint32_t pci_data_readb(void* opaque, uint32_t addr)
436 return pci_data_read(opaque, addr, 1);
439 static uint32_t pci_data_readw(void* opaque, uint32_t addr)
441 return pci_data_read(opaque, addr, 2);
444 static uint32_t pci_data_readl(void* opaque, uint32_t addr)
446 return pci_data_read(opaque, addr, 4);
449 /* i440FX PCI bridge */
451 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);
453 PCIBus *i440fx_init(void)
458 s = pci_register_bus();
459 s->set_irq = piix3_set_irq;
461 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
462 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
464 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
465 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
466 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
467 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
468 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
469 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
471 d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0,
474 d->config[0x00] = 0x86; // vendor_id
475 d->config[0x01] = 0x80;
476 d->config[0x02] = 0x37; // device_id
477 d->config[0x03] = 0x12;
478 d->config[0x08] = 0x02; // revision
479 d->config[0x0a] = 0x00; // class_sub = host2pci
480 d->config[0x0b] = 0x06; // class_base = PCI_bridge
481 d->config[0x0e] = 0x00; // header_type
485 /* PIIX3 PCI to ISA bridge */
487 typedef struct PIIX3State {
491 PIIX3State *piix3_state;
493 /* return the global irq number corresponding to a given device irq
494 pin. We could also use the bus number to have a more precise
496 static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
499 slot_addend = (pci_dev->devfn >> 3) - 1;
500 return (irq_num + slot_addend) & 3;
503 static inline int get_pci_irq_level(int irq_num)
506 #if (PCI_IRQ_WORDS == 2)
507 pic_level = ((pci_irq_levels[irq_num][0] |
508 pci_irq_levels[irq_num][1]) != 0);
513 for(i = 0; i < PCI_IRQ_WORDS; i++) {
514 if (pci_irq_levels[irq_num][i]) {
524 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
526 int irq_index, shift, pic_irq, pic_level;
529 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
530 irq_index = pci_dev->irq_index;
531 p = &pci_irq_levels[irq_num][irq_index >> 5];
532 shift = (irq_index & 0x1f);
533 *p = (*p & ~(1 << shift)) | (level << shift);
535 /* now we change the pic irq level according to the piix irq mappings */
537 pic_irq = piix3_state->dev.config[0x60 + irq_num];
539 /* the pic level is the logical OR of all the PCI irqs mapped
542 if (pic_irq == piix3_state->dev.config[0x60])
543 pic_level |= get_pci_irq_level(0);
544 if (pic_irq == piix3_state->dev.config[0x61])
545 pic_level |= get_pci_irq_level(1);
546 if (pic_irq == piix3_state->dev.config[0x62])
547 pic_level |= get_pci_irq_level(2);
548 if (pic_irq == piix3_state->dev.config[0x63])
549 pic_level |= get_pci_irq_level(3);
550 pic_set_irq(pic_irq, pic_level);
554 static void piix3_reset(PIIX3State *d)
556 uint8_t *pci_conf = d->dev.config;
558 pci_conf[0x04] = 0x07; // master, memory and I/O
559 pci_conf[0x05] = 0x00;
560 pci_conf[0x06] = 0x00;
561 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
562 pci_conf[0x4c] = 0x4d;
563 pci_conf[0x4e] = 0x03;
564 pci_conf[0x4f] = 0x00;
565 pci_conf[0x60] = 0x80;
566 pci_conf[0x69] = 0x02;
567 pci_conf[0x70] = 0x80;
568 pci_conf[0x76] = 0x0c;
569 pci_conf[0x77] = 0x0c;
570 pci_conf[0x78] = 0x02;
571 pci_conf[0x79] = 0x00;
572 pci_conf[0x80] = 0x00;
573 pci_conf[0x82] = 0x00;
574 pci_conf[0xa0] = 0x08;
575 pci_conf[0xa0] = 0x08;
576 pci_conf[0xa2] = 0x00;
577 pci_conf[0xa3] = 0x00;
578 pci_conf[0xa4] = 0x00;
579 pci_conf[0xa5] = 0x00;
580 pci_conf[0xa6] = 0x00;
581 pci_conf[0xa7] = 0x00;
582 pci_conf[0xa8] = 0x0f;
583 pci_conf[0xaa] = 0x00;
584 pci_conf[0xab] = 0x00;
585 pci_conf[0xac] = 0x00;
586 pci_conf[0xae] = 0x00;
589 void piix3_init(PCIBus *bus)
594 d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
596 register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
599 pci_conf = d->dev.config;
601 pci_conf[0x00] = 0x86; // Intel
602 pci_conf[0x01] = 0x80;
603 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
604 pci_conf[0x03] = 0x70;
605 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
606 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
607 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
614 static inline void set_config(PCIBus *s, target_phys_addr_t addr)
618 for(i = 0; i < 11; i++) {
619 if ((addr & (1 << (11 + i))) != 0)
622 devfn = ((addr >> 8) & 7) | (i << 3);
623 s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
626 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
630 pci_data_write(s, addr, val, 1);
633 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
637 #ifdef TARGET_WORDS_BIGENDIAN
640 pci_data_write(s, addr, val, 2);
643 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
647 #ifdef TARGET_WORDS_BIGENDIAN
650 pci_data_write(s, addr, val, 4);
653 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
658 val = pci_data_read(s, addr, 1);
662 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
667 val = pci_data_read(s, addr, 2);
668 #ifdef TARGET_WORDS_BIGENDIAN
674 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
679 val = pci_data_read(s, addr, 4);
680 #ifdef TARGET_WORDS_BIGENDIAN
686 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
692 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
698 static void prep_set_irq(PCIDevice *d, int irq_num, int level)
700 /* XXX: we do not simulate the hardware - we rely on the BIOS to
701 set correctly for irq line field */
702 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
705 PCIBus *pci_prep_init(void)
711 s = pci_register_bus();
712 s->set_irq = prep_set_irq;
714 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
715 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
717 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
718 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
719 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
720 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
721 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
722 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
724 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
726 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
728 /* PCI host bridge */
729 d = pci_register_device(s, "PREP Host Bridge - Motorola Raven",
730 sizeof(PCIDevice), 0, NULL, NULL);
731 d->config[0x00] = 0x57; // vendor_id : Motorola
732 d->config[0x01] = 0x10;
733 d->config[0x02] = 0x01; // device_id : Raven
734 d->config[0x03] = 0x48;
735 d->config[0x08] = 0x00; // revision
736 d->config[0x0A] = 0x00; // class_sub = pci host
737 d->config[0x0B] = 0x06; // class_base = PCI_bridge
738 d->config[0x0C] = 0x08; // cache_line_size
739 d->config[0x0D] = 0x10; // latency_timer
740 d->config[0x0E] = 0x00; // header_type
741 d->config[0x34] = 0x00; // capabilities_pointer
747 /* Grackle PCI host */
748 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
752 #ifdef TARGET_WORDS_BIGENDIAN
758 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
764 #ifdef TARGET_WORDS_BIGENDIAN
770 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
771 &pci_grackle_config_writel,
772 &pci_grackle_config_writel,
773 &pci_grackle_config_writel,
776 static CPUReadMemoryFunc *pci_grackle_config_read[] = {
777 &pci_grackle_config_readl,
778 &pci_grackle_config_readl,
779 &pci_grackle_config_readl,
782 static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
786 pci_data_write(s, addr, val, 1);
789 static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
793 #ifdef TARGET_WORDS_BIGENDIAN
796 pci_data_write(s, addr, val, 2);
799 static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
803 #ifdef TARGET_WORDS_BIGENDIAN
806 pci_data_write(s, addr, val, 4);
809 static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
813 val = pci_data_read(s, addr, 1);
817 static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
821 val = pci_data_read(s, addr, 2);
822 #ifdef TARGET_WORDS_BIGENDIAN
828 static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
833 val = pci_data_read(s, addr, 4);
834 #ifdef TARGET_WORDS_BIGENDIAN
840 static CPUWriteMemoryFunc *pci_grackle_write[] = {
846 static CPUReadMemoryFunc *pci_grackle_read[] = {
852 void pci_set_pic(PCIBus *bus, SetIRQFunc *set_irq, void *irq_opaque)
854 bus->low_set_irq = set_irq;
855 bus->irq_opaque = irq_opaque;
858 /* XXX: we do not simulate the hardware - we rely on the BIOS to
859 set correctly for irq line field */
860 static void pci_set_irq_simple(PCIDevice *d, int irq_num, int level)
863 s->low_set_irq(s->irq_opaque, d->config[PCI_INTERRUPT_LINE], level);
866 PCIBus *pci_grackle_init(uint32_t base)
870 int pci_mem_config, pci_mem_data;
872 s = pci_register_bus();
873 s->set_irq = pci_set_irq_simple;
875 pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
876 pci_grackle_config_write, s);
877 pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
878 pci_grackle_write, s);
879 cpu_register_physical_memory(base, 0x1000, pci_mem_config);
880 cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
881 d = pci_register_device(s, "Grackle host bridge", sizeof(PCIDevice),
883 d->config[0x00] = 0x57; // vendor_id
884 d->config[0x01] = 0x10;
885 d->config[0x02] = 0x02; // device_id
886 d->config[0x03] = 0x00;
887 d->config[0x08] = 0x00; // revision
888 d->config[0x09] = 0x01;
889 d->config[0x0a] = 0x00; // class_sub = host
890 d->config[0x0b] = 0x06; // class_base = PCI_bridge
891 d->config[0x0e] = 0x00; // header_type
893 d->config[0x18] = 0x00; // primary_bus
894 d->config[0x19] = 0x01; // secondary_bus
895 d->config[0x1a] = 0x00; // subordinate_bus
896 d->config[0x1c] = 0x00;
897 d->config[0x1d] = 0x00;
899 d->config[0x20] = 0x00; // memory_base
900 d->config[0x21] = 0x00;
901 d->config[0x22] = 0x01; // memory_limit
902 d->config[0x23] = 0x00;
904 d->config[0x24] = 0x00; // prefetchable_memory_base
905 d->config[0x25] = 0x00;
906 d->config[0x26] = 0x00; // prefetchable_memory_limit
907 d->config[0x27] = 0x00;
910 /* PCI2PCI bridge same values as PearPC - check this */
911 d->config[0x00] = 0x11; // vendor_id
912 d->config[0x01] = 0x10;
913 d->config[0x02] = 0x26; // device_id
914 d->config[0x03] = 0x00;
915 d->config[0x08] = 0x02; // revision
916 d->config[0x0a] = 0x04; // class_sub = pci2pci
917 d->config[0x0b] = 0x06; // class_base = PCI_bridge
918 d->config[0x0e] = 0x01; // header_type
920 d->config[0x18] = 0x0; // primary_bus
921 d->config[0x19] = 0x1; // secondary_bus
922 d->config[0x1a] = 0x1; // subordinate_bus
923 d->config[0x1c] = 0x10; // io_base
924 d->config[0x1d] = 0x20; // io_limit
926 d->config[0x20] = 0x80; // memory_base
927 d->config[0x21] = 0x80;
928 d->config[0x22] = 0x90; // memory_limit
929 d->config[0x23] = 0x80;
931 d->config[0x24] = 0x00; // prefetchable_memory_base
932 d->config[0x25] = 0x84;
933 d->config[0x26] = 0x00; // prefetchable_memory_limit
934 d->config[0x27] = 0x85;
939 /* Uninorth PCI host (for all Mac99 and newer machines */
940 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
946 #ifdef TARGET_WORDS_BIGENDIAN
950 for (i = 11; i < 32; i++) {
951 if ((val & (1 << i)) != 0)
955 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
957 s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
961 static uint32_t pci_unin_main_config_readl (void *opaque,
962 target_phys_addr_t addr)
968 devfn = (s->config_reg >> 8) & 0xFF;
969 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
970 #ifdef TARGET_WORDS_BIGENDIAN
977 static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
978 &pci_unin_main_config_writel,
979 &pci_unin_main_config_writel,
980 &pci_unin_main_config_writel,
983 static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
984 &pci_unin_main_config_readl,
985 &pci_unin_main_config_readl,
986 &pci_unin_main_config_readl,
989 static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
993 pci_data_write(s, addr & 7, val, 1);
996 static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
1000 #ifdef TARGET_WORDS_BIGENDIAN
1003 pci_data_write(s, addr & 7, val, 2);
1006 static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
1010 #ifdef TARGET_WORDS_BIGENDIAN
1013 pci_data_write(s, addr & 7, val, 4);
1016 static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
1021 val = pci_data_read(s, addr & 7, 1);
1026 static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
1031 val = pci_data_read(s, addr & 7, 2);
1032 #ifdef TARGET_WORDS_BIGENDIAN
1039 static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
1044 val = pci_data_read(s, addr, 4);
1045 #ifdef TARGET_WORDS_BIGENDIAN
1052 static CPUWriteMemoryFunc *pci_unin_main_write[] = {
1053 &pci_unin_main_writeb,
1054 &pci_unin_main_writew,
1055 &pci_unin_main_writel,
1058 static CPUReadMemoryFunc *pci_unin_main_read[] = {
1059 &pci_unin_main_readb,
1060 &pci_unin_main_readw,
1061 &pci_unin_main_readl,
1066 static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
1071 #ifdef TARGET_WORDS_BIGENDIAN
1074 s->config_reg = 0x80000000 | (val & ~0x00000001);
1077 static uint32_t pci_unin_config_readl (void *opaque,
1078 target_phys_addr_t addr)
1083 val = (s->config_reg | 0x00000001) & ~0x80000000;
1084 #ifdef TARGET_WORDS_BIGENDIAN
1091 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
1092 &pci_unin_config_writel,
1093 &pci_unin_config_writel,
1094 &pci_unin_config_writel,
1097 static CPUReadMemoryFunc *pci_unin_config_read[] = {
1098 &pci_unin_config_readl,
1099 &pci_unin_config_readl,
1100 &pci_unin_config_readl,
1103 static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
1107 pci_data_write(s, addr & 3, val, 1);
1110 static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
1114 #ifdef TARGET_WORDS_BIGENDIAN
1117 pci_data_write(s, addr & 3, val, 2);
1120 static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
1124 #ifdef TARGET_WORDS_BIGENDIAN
1127 pci_data_write(s, addr & 3, val, 4);
1130 static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
1135 val = pci_data_read(s, addr & 3, 1);
1140 static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
1145 val = pci_data_read(s, addr & 3, 2);
1146 #ifdef TARGET_WORDS_BIGENDIAN
1153 static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
1158 val = pci_data_read(s, addr & 3, 4);
1159 #ifdef TARGET_WORDS_BIGENDIAN
1166 static CPUWriteMemoryFunc *pci_unin_write[] = {
1172 static CPUReadMemoryFunc *pci_unin_read[] = {
1179 PCIBus *pci_pmac_init(void)
1183 int pci_mem_config, pci_mem_data;
1185 /* Use values found on a real PowerMac */
1186 /* Uninorth main bus */
1187 s = pci_register_bus();
1188 s->set_irq = pci_set_irq_simple;
1190 pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1191 pci_unin_main_config_write, s);
1192 pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
1193 pci_unin_main_write, s);
1194 cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
1195 cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
1196 s->devfn_min = 11 << 3;
1197 d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice),
1198 11 << 3, NULL, NULL);
1199 d->config[0x00] = 0x6b; // vendor_id : Apple
1200 d->config[0x01] = 0x10;
1201 d->config[0x02] = 0x1F; // device_id
1202 d->config[0x03] = 0x00;
1203 d->config[0x08] = 0x00; // revision
1204 d->config[0x0A] = 0x00; // class_sub = pci host
1205 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1206 d->config[0x0C] = 0x08; // cache_line_size
1207 d->config[0x0D] = 0x10; // latency_timer
1208 d->config[0x0E] = 0x00; // header_type
1209 d->config[0x34] = 0x00; // capabilities_pointer
1211 #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
1212 /* pci-to-pci bridge */
1213 d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
1215 d->config[0x00] = 0x11; // vendor_id : TI
1216 d->config[0x01] = 0x10;
1217 d->config[0x02] = 0x26; // device_id
1218 d->config[0x03] = 0x00;
1219 d->config[0x08] = 0x05; // revision
1220 d->config[0x0A] = 0x04; // class_sub = pci2pci
1221 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1222 d->config[0x0C] = 0x08; // cache_line_size
1223 d->config[0x0D] = 0x20; // latency_timer
1224 d->config[0x0E] = 0x01; // header_type
1226 d->config[0x18] = 0x01; // primary_bus
1227 d->config[0x19] = 0x02; // secondary_bus
1228 d->config[0x1A] = 0x02; // subordinate_bus
1229 d->config[0x1B] = 0x20; // secondary_latency_timer
1230 d->config[0x1C] = 0x11; // io_base
1231 d->config[0x1D] = 0x01; // io_limit
1232 d->config[0x20] = 0x00; // memory_base
1233 d->config[0x21] = 0x80;
1234 d->config[0x22] = 0x00; // memory_limit
1235 d->config[0x23] = 0x80;
1236 d->config[0x24] = 0x01; // prefetchable_memory_base
1237 d->config[0x25] = 0x80;
1238 d->config[0x26] = 0xF1; // prefectchable_memory_limit
1239 d->config[0x27] = 0x7F;
1240 // d->config[0x34] = 0xdc // capabilities_pointer
1242 #if 0 // XXX: not needed for now
1243 /* Uninorth AGP bus */
1245 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1246 pci_unin_config_write, s);
1247 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1249 cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
1250 cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
1252 d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
1254 d->config[0x00] = 0x6b; // vendor_id : Apple
1255 d->config[0x01] = 0x10;
1256 d->config[0x02] = 0x20; // device_id
1257 d->config[0x03] = 0x00;
1258 d->config[0x08] = 0x00; // revision
1259 d->config[0x0A] = 0x00; // class_sub = pci host
1260 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1261 d->config[0x0C] = 0x08; // cache_line_size
1262 d->config[0x0D] = 0x10; // latency_timer
1263 d->config[0x0E] = 0x00; // header_type
1264 // d->config[0x34] = 0x80; // capabilities_pointer
1267 #if 0 // XXX: not needed for now
1268 /* Uninorth internal bus */
1270 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1271 pci_unin_config_write, s);
1272 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1274 cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
1275 cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
1277 d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
1278 3, 11 << 3, NULL, NULL);
1279 d->config[0x00] = 0x6b; // vendor_id : Apple
1280 d->config[0x01] = 0x10;
1281 d->config[0x02] = 0x1E; // device_id
1282 d->config[0x03] = 0x00;
1283 d->config[0x08] = 0x00; // revision
1284 d->config[0x0A] = 0x00; // class_sub = pci host
1285 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1286 d->config[0x0C] = 0x08; // cache_line_size
1287 d->config[0x0D] = 0x10; // latency_timer
1288 d->config[0x0E] = 0x00; // header_type
1289 d->config[0x34] = 0x00; // capabilities_pointer
1294 /* Ultrasparc APB PCI host */
1295 static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
1301 for (i = 11; i < 32; i++) {
1302 if ((val & (1 << i)) != 0)
1305 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
1308 static uint32_t pci_apb_config_readl (void *opaque,
1309 target_phys_addr_t addr)
1315 devfn = (s->config_reg >> 8) & 0xFF;
1316 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
1320 static CPUWriteMemoryFunc *pci_apb_config_write[] = {
1321 &pci_apb_config_writel,
1322 &pci_apb_config_writel,
1323 &pci_apb_config_writel,
1326 static CPUReadMemoryFunc *pci_apb_config_read[] = {
1327 &pci_apb_config_readl,
1328 &pci_apb_config_readl,
1329 &pci_apb_config_readl,
1332 static void apb_config_writel (void *opaque, target_phys_addr_t addr,
1335 //PCIBus *s = opaque;
1337 switch (addr & 0x3f) {
1338 case 0x00: // Control/Status
1341 case 0x20: // Diagnostic
1342 case 0x28: // Target address space
1349 static uint32_t apb_config_readl (void *opaque,
1350 target_phys_addr_t addr)
1352 //PCIBus *s = opaque;
1355 switch (addr & 0x3f) {
1356 case 0x00: // Control/Status
1359 case 0x20: // Diagnostic
1360 case 0x28: // Target address space
1369 static CPUWriteMemoryFunc *apb_config_write[] = {
1375 static CPUReadMemoryFunc *apb_config_read[] = {
1381 static void pci_apb_writeb (void *opaque, target_phys_addr_t addr,
1386 pci_data_write(s, addr & 7, val, 1);
1389 static void pci_apb_writew (void *opaque, target_phys_addr_t addr,
1394 pci_data_write(s, addr & 7, val, 2);
1397 static void pci_apb_writel (void *opaque, target_phys_addr_t addr,
1402 pci_data_write(s, addr & 7, val, 4);
1405 static uint32_t pci_apb_readb (void *opaque, target_phys_addr_t addr)
1410 val = pci_data_read(s, addr & 7, 1);
1414 static uint32_t pci_apb_readw (void *opaque, target_phys_addr_t addr)
1419 val = pci_data_read(s, addr & 7, 2);
1423 static uint32_t pci_apb_readl (void *opaque, target_phys_addr_t addr)
1428 val = pci_data_read(s, addr, 4);
1432 static CPUWriteMemoryFunc *pci_apb_write[] = {
1438 static CPUReadMemoryFunc *pci_apb_read[] = {
1444 static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
1447 cpu_outb(NULL, addr & 0xffff, val);
1450 static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
1453 cpu_outw(NULL, addr & 0xffff, val);
1456 static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
1459 cpu_outl(NULL, addr & 0xffff, val);
1462 static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
1466 val = cpu_inb(NULL, addr & 0xffff);
1470 static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
1474 val = cpu_inw(NULL, addr & 0xffff);
1478 static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
1482 val = cpu_inl(NULL, addr & 0xffff);
1486 static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
1492 static CPUReadMemoryFunc *pci_apb_ioread[] = {
1498 PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base)
1502 int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
1504 /* Ultrasparc APB main bus */
1505 s = pci_register_bus();
1506 s->set_irq = pci_set_irq_simple;
1508 pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
1509 pci_apb_config_write, s);
1510 apb_config = cpu_register_io_memory(0, apb_config_read,
1511 apb_config_write, s);
1512 pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
1514 pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
1515 pci_apb_iowrite, s);
1517 cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);
1518 cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config);
1519 cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
1520 cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
1522 d = pci_register_device(s, "Advanced PCI Bus", sizeof(PCIDevice),
1524 d->config[0x00] = 0x8e; // vendor_id : Sun
1525 d->config[0x01] = 0x10;
1526 d->config[0x02] = 0x00; // device_id
1527 d->config[0x03] = 0xa0;
1528 d->config[0x04] = 0x06; // command = bus master, pci mem
1529 d->config[0x05] = 0x00;
1530 d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
1531 d->config[0x07] = 0x03; // status = medium devsel
1532 d->config[0x08] = 0x00; // revision
1533 d->config[0x09] = 0x00; // programming i/f
1534 d->config[0x0A] = 0x00; // class_sub = pci host
1535 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1536 d->config[0x0D] = 0x10; // latency_timer
1537 d->config[0x0E] = 0x00; // header_type
1541 /***********************************************************/
1542 /* generic PCI irq support */
1544 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1545 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
1547 PCIBus *bus = pci_dev->bus;
1548 bus->set_irq(pci_dev, irq_num, level);
1551 /***********************************************************/
1552 /* monitor info on PCI */
1554 static void pci_info_device(PCIDevice *d)
1559 term_printf(" Bus %2d, device %3d, function %d:\n",
1560 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
1561 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1565 term_printf("IDE controller");
1568 term_printf("Ethernet controller");
1571 term_printf("VGA controller");
1574 term_printf("Class %04x", class);
1577 term_printf(": PCI device %04x:%04x\n",
1578 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1579 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
1581 if (d->config[PCI_INTERRUPT_PIN] != 0) {
1582 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
1584 for(i = 0;i < PCI_NUM_REGIONS; i++) {
1585 r = &d->io_regions[i];
1587 term_printf(" BAR%d: ", i);
1588 if (r->type & PCI_ADDRESS_SPACE_IO) {
1589 term_printf("I/O at 0x%04x [0x%04x].\n",
1590 r->addr, r->addr + r->size - 1);
1592 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
1593 r->addr, r->addr + r->size - 1);
1601 PCIBus *bus = first_bus;
1606 for(devfn = 0; devfn < 256; devfn++) {
1607 d = bus->devices[devfn];
1614 /***********************************************************/
1615 /* XXX: the following should be moved to the PC BIOS */
1617 static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
1619 return cpu_inb(cpu_single_env, addr);
1622 static void isa_outb(uint32_t val, uint32_t addr)
1624 cpu_outb(cpu_single_env, addr, val);
1627 static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
1629 return cpu_inw(cpu_single_env, addr);
1632 static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
1634 cpu_outw(cpu_single_env, addr, val);
1637 static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
1639 return cpu_inl(cpu_single_env, addr);
1642 static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
1644 cpu_outl(cpu_single_env, addr, val);
1647 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1650 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1651 (d->devfn << 8) | addr;
1652 pci_data_write(s, 0, val, 4);
1655 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1658 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1659 (d->devfn << 8) | (addr & ~3);
1660 pci_data_write(s, addr & 3, val, 2);
1663 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1666 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1667 (d->devfn << 8) | (addr & ~3);
1668 pci_data_write(s, addr & 3, val, 1);
1671 static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
1674 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1675 (d->devfn << 8) | addr;
1676 return pci_data_read(s, 0, 4);
1679 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1682 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1683 (d->devfn << 8) | (addr & ~3);
1684 return pci_data_read(s, addr & 3, 2);
1687 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1690 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1691 (d->devfn << 8) | (addr & ~3);
1692 return pci_data_read(s, addr & 3, 1);
1695 static uint32_t pci_bios_io_addr;
1696 static uint32_t pci_bios_mem_addr;
1697 /* host irqs corresponding to PCI irqs A-D */
1698 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
1700 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1706 if ( region_num == PCI_ROM_SLOT ) {
1709 ofs = 0x10 + region_num * 4;
1712 pci_config_writel(d, ofs, addr);
1713 r = &d->io_regions[region_num];
1715 /* enable memory mappings */
1716 cmd = pci_config_readw(d, PCI_COMMAND);
1717 if ( region_num == PCI_ROM_SLOT )
1719 else if (r->type & PCI_ADDRESS_SPACE_IO)
1723 pci_config_writew(d, PCI_COMMAND, cmd);
1726 static void pci_bios_init_device(PCIDevice *d)
1731 int i, pin, pic_irq, vendor_id, device_id;
1733 class = pci_config_readw(d, PCI_CLASS_DEVICE);
1734 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1735 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1738 if (vendor_id == 0x8086 && device_id == 0x7010) {
1740 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
1741 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
1744 /* IDE: we map it as in ISA mode */
1745 pci_set_io_region_addr(d, 0, 0x1f0);
1746 pci_set_io_region_addr(d, 1, 0x3f4);
1747 pci_set_io_region_addr(d, 2, 0x170);
1748 pci_set_io_region_addr(d, 3, 0x374);
1752 if (vendor_id != 0x1234)
1754 /* VGA: map frame buffer to default Bochs VBE address */
1755 pci_set_io_region_addr(d, 0, 0xE0000000);
1759 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1760 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1761 if (vendor_id == 0x1014) {
1763 if (device_id == 0x0046 || device_id == 0xFFFF) {
1765 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1770 if (vendor_id == 0x0106b &&
1771 (device_id == 0x0017 || device_id == 0x0022)) {
1773 pci_set_io_region_addr(d, 0, 0x80800000);
1778 /* default memory mappings */
1779 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1780 r = &d->io_regions[i];
1782 if (r->type & PCI_ADDRESS_SPACE_IO)
1783 paddr = &pci_bios_io_addr;
1785 paddr = &pci_bios_mem_addr;
1786 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1787 pci_set_io_region_addr(d, i, *paddr);
1794 /* map the interrupt */
1795 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1797 pin = pci_slot_get_pirq(d, pin - 1);
1798 pic_irq = pci_irqs[pin];
1799 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1804 * This function initializes the PCI devices as a normal PCI BIOS
1805 * would do. It is provided just in case the BIOS has no support for
1808 void pci_bios_init(void)
1815 pci_bios_io_addr = 0xc000;
1816 pci_bios_mem_addr = 0xf0000000;
1818 /* activate IRQ mappings */
1821 for(i = 0; i < 4; i++) {
1823 /* set to trigger level */
1824 elcr[irq >> 3] |= (1 << (irq & 7));
1825 /* activate irq remapping in PIIX */
1826 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1828 isa_outb(elcr[0], 0x4d0);
1829 isa_outb(elcr[1], 0x4d1);
1833 for(devfn = 0; devfn < 256; devfn++) {
1834 d = bus->devices[devfn];
1836 pci_bios_init_device(d);