4 * Copyright (c) 2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Based on OpenPic implementations:
27 * - Intel GW80314 I/O compagnion chip developper's manual
28 * - Motorola MPC8245 & MPC8540 user manuals.
29 * - Motorola MCP750 (aka Raven) programmer manual.
30 * - Motorola Harrier programmer manuel
32 * Serial interrupts, as implemented in Raven chipset are not supported yet.
37 //#define DEBUG_OPENPIC
40 #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
42 #define DPRINTF(fmt, args...) do { } while (0)
44 #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
46 #define USE_MPCxxx /* Intel model is broken, for now */
48 #if defined (USE_INTEL_GW80314)
49 /* Intel GW80314 I/O Companion chip */
59 #define VID (0x00000000)
61 #define OPENPIC_LITTLE_ENDIAN 1
62 #define OPENPIC_BIG_ENDIAN 0
64 #elif defined(USE_MPCxxx)
74 #define VID 0x03 /* MPIC version ID */
75 #define VENI 0x00000000 /* Vendor ID */
82 #define OPENPIC_LITTLE_ENDIAN 1
83 #define OPENPIC_BIG_ENDIAN 0
86 #error "Please select which OpenPic implementation is to be emulated"
89 #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \
90 (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN)
94 /* Interrupt definitions */
95 #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
96 #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */
97 #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */
99 #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
100 #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
102 #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
103 #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
106 #define BF_WIDTH(_bits_) \
107 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
109 static inline void set_bit (uint32_t *field, int bit)
111 field[bit >> 5] |= 1 << (bit & 0x1F);
114 static inline void reset_bit (uint32_t *field, int bit)
116 field[bit >> 5] &= ~(1 << (bit & 0x1F));
119 static inline int test_bit (uint32_t *field, int bit)
121 return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
131 typedef struct IRQ_queue_t {
132 uint32_t queue[BF_WIDTH(MAX_IRQ)];
137 typedef struct IRQ_src_t {
138 uint32_t ipvp; /* IRQ vector/priority register */
139 uint32_t ide; /* IRQ destination register */
142 int pending; /* TRUE if IRQ is pending */
152 #define IPVP_PRIORITY_MASK (0x1F << 16)
153 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16))
154 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1)
155 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK)
157 typedef struct IRQ_dst_t {
158 uint32_t pctp; /* CPU current task priority */
159 uint32_t pcsr; /* CPU sensitivity register */
161 IRQ_queue_t servicing;
162 CPUState *env; /* Needed if we did SMP */
168 /* Global registers */
169 uint32_t frep; /* Feature reporting register */
170 uint32_t glbc; /* Global configuration register */
171 uint32_t micr; /* MPIC interrupt configuration register */
172 uint32_t veni; /* Vendor identification register */
173 uint32_t spve; /* Spurious vector register */
174 uint32_t tifr; /* Timer frequency reporting register */
175 /* Source registers */
176 IRQ_src_t src[MAX_IRQ];
177 /* Local registers per output pin */
178 IRQ_dst_t dst[MAX_CPU];
180 /* Timer registers */
182 uint32_t ticc; /* Global timer current count register */
183 uint32_t tibc; /* Global timer base count register */
186 /* Doorbell registers */
187 uint32_t dar; /* Doorbell activate register */
189 uint32_t dmr; /* Doorbell messaging register */
190 } doorbells[MAX_DBL];
193 /* Mailbox registers */
195 uint32_t mbr; /* Mailbox register */
196 } mailboxes[MAX_MAILBOXES];
200 static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
202 set_bit(q->queue, n_IRQ);
205 static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ)
207 reset_bit(q->queue, n_IRQ);
210 static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ)
212 return test_bit(q->queue, n_IRQ);
215 static void IRQ_check (openpic_t *opp, IRQ_queue_t *q)
222 for (i = 0; i < MAX_IRQ; i++) {
223 if (IRQ_testbit(q, i)) {
224 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
225 i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
226 if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
228 priority = IPVP_PRIORITY(opp->src[i].ipvp);
233 q->priority = priority;
236 static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q)
246 static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ)
252 dst = &opp->dst[n_CPU];
253 src = &opp->src[n_IRQ];
254 priority = IPVP_PRIORITY(src->ipvp);
255 if (priority <= dst->pctp) {
256 /* Too low priority */
259 if (IRQ_testbit(&dst->raised, n_IRQ)) {
263 set_bit(&src->ipvp, IPVP_ACTIVITY);
264 IRQ_setbit(&dst->raised, n_IRQ);
265 if (priority > dst->raised.priority) {
266 IRQ_get_next(opp, &dst->raised);
267 DPRINTF("Raise CPU IRQ\n");
268 /* XXX: choose the correct cpu */
269 cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
273 /* update pic state because registers for n_IRQ have changed value */
274 static void openpic_update_irq(openpic_t *opp, int n_IRQ)
279 src = &opp->src[n_IRQ];
285 if (test_bit(&src->ipvp, IPVP_MASK)) {
286 /* Interrupt source is disabled */
289 if (IPVP_PRIORITY(src->ipvp) == 0) {
290 /* Priority set to zero */
293 if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
294 /* IRQ already active */
297 if (src->ide == 0x00000000) {
302 if (!test_bit(&src->ipvp, IPVP_MODE) ||
303 src->ide == (1 << src->last_cpu)) {
304 /* Directed delivery mode */
305 for (i = 0; i < opp->nb_cpus; i++) {
306 if (test_bit(&src->ide, i))
307 IRQ_local_pipe(opp, i, n_IRQ);
310 /* Distributed delivery mode */
311 /* XXX: incorrect code */
312 for (i = src->last_cpu; i < src->last_cpu; i++) {
315 if (test_bit(&src->ide, i)) {
316 IRQ_local_pipe(opp, i, n_IRQ);
324 void openpic_set_irq(void *opaque, int n_IRQ, int level)
326 openpic_t *opp = opaque;
329 src = &opp->src[n_IRQ];
330 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n",
331 n_IRQ, level, src->ipvp);
332 if (test_bit(&src->ipvp, IPVP_SENSE)) {
333 /* level-sensitive irq */
334 src->pending = level;
336 reset_bit(&src->ipvp, IPVP_ACTIVITY);
338 /* edge-sensitive irq */
342 openpic_update_irq(opp, n_IRQ);
345 static void openpic_reset (openpic_t *opp)
349 opp->glbc = 0x80000000;
350 /* Initialise controller registers */
351 opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID;
353 opp->spve = 0x000000FF;
354 opp->tifr = 0x003F7A00;
356 opp->micr = 0x00000000;
357 /* Initialise IRQ sources */
358 for (i = 0; i < MAX_IRQ; i++) {
359 opp->src[i].ipvp = 0xA0000000;
360 opp->src[i].ide = 0x00000000;
362 /* Initialise IRQ destinations */
363 for (i = 0; i < opp->nb_cpus; i++) {
364 opp->dst[i].pctp = 0x0000000F;
365 opp->dst[i].pcsr = 0x00000000;
366 memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
367 memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
369 /* Initialise timers */
370 for (i = 0; i < MAX_TMR; i++) {
371 opp->timers[i].ticc = 0x00000000;
372 opp->timers[i].tibc = 0x80000000;
374 /* Initialise doorbells */
376 opp->dar = 0x00000000;
377 for (i = 0; i < MAX_DBL; i++) {
378 opp->doorbells[i].dmr = 0x00000000;
381 /* Initialise mailboxes */
383 for (i = 0; i < MAX_MBX; i++) { /* ? */
384 opp->mailboxes[i].mbr = 0x00000000;
387 /* Go out of RESET state */
388 opp->glbc = 0x00000000;
391 static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
397 retval = opp->src[n_IRQ].ipvp;
400 retval = opp->src[n_IRQ].ide;
407 static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
408 uint32_t reg, uint32_t val)
414 /* NOTE: not fully accurate for special IRQs, but simple and
416 /* ACTIVITY bit is read-only */
417 opp->src[n_IRQ].ipvp =
418 (opp->src[n_IRQ].ipvp & 0x40000000) |
420 openpic_update_irq(opp, n_IRQ);
421 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
422 n_IRQ, val, opp->src[n_IRQ].ipvp);
425 tmp = val & 0xC0000000;
426 tmp |= val & ((1 << MAX_CPU) - 1);
427 opp->src[n_IRQ].ide = tmp;
428 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
433 #if 0 // Code provision for Intel model
435 static uint32_t read_doorbell_register (openpic_t *opp,
436 int n_dbl, uint32_t offset)
441 case DBL_IPVP_OFFSET:
442 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
445 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
448 retval = opp->doorbells[n_dbl].dmr;
455 static void write_doorbell_register (penpic_t *opp, int n_dbl,
456 uint32_t offset, uint32_t value)
459 case DBL_IVPR_OFFSET:
460 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
463 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
466 opp->doorbells[n_dbl].dmr = value;
473 static uint32_t read_mailbox_register (openpic_t *opp,
474 int n_mbx, uint32_t offset)
480 retval = opp->mailboxes[n_mbx].mbr;
482 case MBX_IVPR_OFFSET:
483 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
486 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
493 static void write_mailbox_register (openpic_t *opp, int n_mbx,
494 uint32_t address, uint32_t value)
498 opp->mailboxes[n_mbx].mbr = value;
500 case MBX_IVPR_OFFSET:
501 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
504 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
509 #endif /* 0 : Code provision for Intel model */
511 static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val)
513 openpic_t *opp = opaque;
515 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
518 #if defined OPENPIC_SWAP
523 case 0x00: /* FREP */
525 case 0x20: /* GLBC */
526 if (val & 0x80000000)
528 opp->glbc = val & ~0x80000000;
530 case 0x80: /* VENI */
532 case 0x90: /* PINT */
533 /* XXX: Should be able to reset any CPU */
535 DPRINTF("Reset CPU IRQ\n");
536 // cpu_interrupt(first_cpu, CPU_INTERRUPT_RESET);
540 case 0xA0: /* IPI_IPVP */
546 idx = (addr - 0xA0) >> 4;
547 write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP, val);
551 case 0xE0: /* SPVE */
552 opp->spve = val & 0x000000FF;
554 case 0xF0: /* TIFR */
562 static uint32_t openpic_gbl_read (void *opaque, uint32_t addr)
564 openpic_t *opp = opaque;
567 DPRINTF("%s: addr %08x\n", __func__, addr);
573 case 0x00: /* FREP */
576 case 0x20: /* GLBC */
579 case 0x80: /* VENI */
582 case 0x90: /* PINT */
586 case 0xA0: /* IPI_IPVP */
592 idx = (addr - 0xA0) >> 4;
593 retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP);
597 case 0xE0: /* SPVE */
600 case 0xF0: /* TIFR */
606 DPRINTF("%s: => %08x\n", __func__, retval);
607 #if defined OPENPIC_SWAP
608 retval = bswap32(retval);
614 static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
616 openpic_t *opp = opaque;
619 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
622 #if defined OPENPIC_SWAP
627 idx = (addr & 0xFFF0) >> 6;
630 case 0x00: /* TICC */
632 case 0x10: /* TIBC */
633 if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
634 (val & 0x80000000) == 0 &&
635 (opp->timers[idx].tibc & 0x80000000) != 0)
636 opp->timers[idx].ticc &= ~0x80000000;
637 opp->timers[idx].tibc = val;
639 case 0x20: /* TIVP */
640 write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP, val);
642 case 0x30: /* TIDE */
643 write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE, val);
648 static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
650 openpic_t *opp = opaque;
654 DPRINTF("%s: addr %08x\n", __func__, addr);
660 idx = (addr & 0xFFF0) >> 6;
663 case 0x00: /* TICC */
664 retval = opp->timers[idx].ticc;
666 case 0x10: /* TIBC */
667 retval = opp->timers[idx].tibc;
669 case 0x20: /* TIPV */
670 retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP);
672 case 0x30: /* TIDE */
673 retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE);
676 DPRINTF("%s: => %08x\n", __func__, retval);
677 #if defined OPENPIC_SWAP
678 retval = bswap32(retval);
684 static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
686 openpic_t *opp = opaque;
689 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
692 #if defined OPENPIC_SWAP
695 addr = addr & 0xFFF0;
698 /* EXDE / IFEDE / IEEDE */
699 write_IRQreg(opp, idx, IRQ_IDE, val);
701 /* EXVP / IFEVP / IEEVP */
702 write_IRQreg(opp, idx, IRQ_IPVP, val);
706 static uint32_t openpic_src_read (void *opaque, uint32_t addr)
708 openpic_t *opp = opaque;
712 DPRINTF("%s: addr %08x\n", __func__, addr);
716 addr = addr & 0xFFF0;
719 /* EXDE / IFEDE / IEEDE */
720 retval = read_IRQreg(opp, idx, IRQ_IDE);
722 /* EXVP / IFEVP / IEEVP */
723 retval = read_IRQreg(opp, idx, IRQ_IPVP);
725 DPRINTF("%s: => %08x\n", __func__, retval);
726 #if defined OPENPIC_SWAP
727 retval = tswap32(retval);
733 static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val)
735 openpic_t *opp = opaque;
740 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
743 #if defined OPENPIC_SWAP
748 dst = &opp->dst[idx];
752 case 0x40: /* PIPD */
756 idx = (addr - 0x40) >> 4;
757 write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val);
758 openpic_set_irq(opp, IRQ_IPI0 + idx, 1);
759 openpic_set_irq(opp, IRQ_IPI0 + idx, 0);
762 case 0x80: /* PCTP */
763 dst->pctp = val & 0x0000000F;
765 case 0x90: /* WHOAMI */
766 /* Read-only register */
768 case 0xA0: /* PIAC */
769 /* Read-only register */
771 case 0xB0: /* PEOI */
773 n_IRQ = IRQ_get_next(opp, &dst->servicing);
774 IRQ_resetbit(&dst->servicing, n_IRQ);
775 dst->servicing.next = -1;
776 src = &opp->src[n_IRQ];
777 /* Set up next servicing IRQ */
778 IRQ_get_next(opp, &dst->servicing);
779 /* Check queued interrupts. */
780 n_IRQ = IRQ_get_next(opp, &dst->raised);
782 src = &opp->src[n_IRQ];
783 if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
784 DPRINTF("Raise CPU IRQ\n");
785 /* XXX: choose cpu */
786 cpu_interrupt(first_cpu, CPU_INTERRUPT_HARD);
795 static uint32_t openpic_cpu_read (void *opaque, uint32_t addr)
797 openpic_t *opp = opaque;
803 DPRINTF("%s: addr %08x\n", __func__, addr);
809 dst = &opp->dst[idx];
812 case 0x80: /* PCTP */
815 case 0x90: /* WHOAMI */
818 case 0xA0: /* PIAC */
819 n_IRQ = IRQ_get_next(opp, &dst->raised);
820 DPRINTF("PIAC: irq=%d\n", n_IRQ);
822 /* No more interrupt pending */
825 src = &opp->src[n_IRQ];
826 if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
827 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
828 /* - Spurious level-sensitive IRQ
829 * - Priorities has been changed
830 * and the pending IRQ isn't allowed anymore
832 reset_bit(&src->ipvp, IPVP_ACTIVITY);
833 retval = IPVP_VECTOR(opp->spve);
835 /* IRQ enter servicing state */
836 IRQ_setbit(&dst->servicing, n_IRQ);
837 retval = IPVP_VECTOR(src->ipvp);
839 IRQ_resetbit(&dst->raised, n_IRQ);
840 dst->raised.next = -1;
841 if (!test_bit(&src->ipvp, IPVP_SENSE)) {
842 /* edge-sensitive IRQ */
843 reset_bit(&src->ipvp, IPVP_ACTIVITY);
848 case 0xB0: /* PEOI */
854 idx = (addr - 0x40) >> 4;
855 retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE);
861 DPRINTF("%s: => %08x\n", __func__, retval);
862 #if defined OPENPIC_SWAP
863 retval= bswap32(retval);
869 static void openpic_buggy_write (void *opaque,
870 target_phys_addr_t addr, uint32_t val)
872 printf("Invalid OPENPIC write access !\n");
875 static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr)
877 printf("Invalid OPENPIC read access !\n");
882 static void openpic_writel (void *opaque,
883 target_phys_addr_t addr, uint32_t val)
885 openpic_t *opp = opaque;
888 DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val);
890 /* Global registers */
891 openpic_gbl_write(opp, addr, val);
892 } else if (addr < 0x10000) {
893 /* Timers registers */
894 openpic_timer_write(opp, addr, val);
895 } else if (addr < 0x20000) {
896 /* Source registers */
897 openpic_src_write(opp, addr, val);
900 openpic_cpu_write(opp, addr, val);
904 static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr)
906 openpic_t *opp = opaque;
910 DPRINTF("%s: offset %08x\n", __func__, (int)addr);
912 /* Global registers */
913 retval = openpic_gbl_read(opp, addr);
914 } else if (addr < 0x10000) {
915 /* Timers registers */
916 retval = openpic_timer_read(opp, addr);
917 } else if (addr < 0x20000) {
918 /* Source registers */
919 retval = openpic_src_read(opp, addr);
922 retval = openpic_cpu_read(opp, addr);
928 static CPUWriteMemoryFunc *openpic_write[] = {
929 &openpic_buggy_write,
930 &openpic_buggy_write,
934 static CPUReadMemoryFunc *openpic_read[] = {
940 static void openpic_map(PCIDevice *pci_dev, int region_num,
941 uint32_t addr, uint32_t size, int type)
945 DPRINTF("Map OpenPIC\n");
946 opp = (openpic_t *)pci_dev;
947 /* Global registers */
948 DPRINTF("Register OPENPIC gbl %08x => %08x\n",
949 addr + 0x1000, addr + 0x1000 + 0x100);
950 /* Timer registers */
951 DPRINTF("Register OPENPIC timer %08x => %08x\n",
952 addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR);
953 /* Interrupt source registers */
954 DPRINTF("Register OPENPIC src %08x => %08x\n",
955 addr + 0x10000, addr + 0x10000 + 0x20 * (EXT_IRQ + 2));
956 /* Per CPU registers */
957 DPRINTF("Register OPENPIC dst %08x => %08x\n",
958 addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
959 cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
960 #if 0 // Don't implement ISU for now
961 opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
963 cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
968 openpic_t *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus)
974 /* XXX: for now, only one CPU is supported */
978 opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
982 pci_conf = opp->pci_dev.config;
983 pci_conf[0x00] = 0x14; // IBM MPIC2
984 pci_conf[0x01] = 0x10;
985 pci_conf[0x02] = 0xFF;
986 pci_conf[0x03] = 0xFF;
987 pci_conf[0x0a] = 0x80; // PIC
988 pci_conf[0x0b] = 0x08;
989 pci_conf[0x0e] = 0x00; // header_type
990 pci_conf[0x3d] = 0x00; // no interrupt pin
992 /* Register I/O spaces */
993 pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
994 PCI_ADDRESS_SPACE_MEM, &openpic_map);
996 opp = qemu_mallocz(sizeof(openpic_t));
999 opp->mem_index = cpu_register_io_memory(0, openpic_read,
1000 openpic_write, opp);
1002 // isu_base &= 0xFFFC0000;
1003 opp->nb_cpus = nb_cpus;
1005 for (i = 0; i < EXT_IRQ; i++) {
1006 opp->src[i].type = IRQ_EXTERNAL;
1008 for (; i < IRQ_TIM0; i++) {
1009 opp->src[i].type = IRQ_SPECIAL;
1016 for (; i < m; i++) {
1017 opp->src[i].type = IRQ_TIMER;
1019 for (; i < MAX_IRQ; i++) {
1020 opp->src[i].type = IRQ_INTERNAL;
1024 *pmem_index = opp->mem_index;