vcs.maemo.org Git - qemu/blob - hw/omap3_usb.c

   1 /*
   2  * TI OMAP3 High-Speed USB Host and OTG Controller emulation.
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20 #include "qemu-common.h"
  21 #include "qemu-timer.h"
  22 #include "usb.h"
  23 #include "omap.h"
  24 #include "irq.h"
  25 #include "devices.h"
  26 #include "hw.h"
  27
  28 #define OMAP3_HSUSB_OTG
  29 //#define OMAP3_HSUSB_HOST
  30
  31 /* #define OMAP3_HSUSB_DEBUG */
  32
  33 #ifdef OMAP3_HSUSB_DEBUG
  34 #define TRACE(fmt,...) fprintf(stderr, "%s: " fmt "\n", __FUNCTION__, ##__VA_ARGS__)
  35 #else
  36 #define TRACE(...)
  37 #endif
  38
  39 #ifdef OMAP3_HSUSB_OTG
  40 /* usb-musb.c */
  41 extern CPUReadMemoryFunc *musb_read[];
  42 extern CPUWriteMemoryFunc *musb_write[];
  43
  44 struct omap3_hsusb_otg_s {
  45     qemu_irq mc_irq;
  46     qemu_irq dma_irq;
  47     struct musb_s *musb;
  48
  49     uint8_t rev;
  50     uint16_t sysconfig;
  51     uint8_t interfsel;
  52     uint8_t simenable;
  53     uint8_t forcestdby;
  54 };
  55
  56 static void omap3_hsusb_otg_save_state(QEMUFile *f, void *opaque)
  57 {
  58     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
  59
  60     qemu_put_be16(f, s->sysconfig);
  61     qemu_put_byte(f, s->interfsel);
  62     qemu_put_byte(f, s->simenable);
  63     qemu_put_byte(f, s->forcestdby);
  64 }
  65
  66 static int omap3_hsusb_otg_load_state(QEMUFile *f, void *opaque,
  67                                       int version_id)
  68 {
  69     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
  70
  71     if (version_id)
  72         return -EINVAL;
  73
  74     s->sysconfig = qemu_get_be16(f);
  75     s->interfsel = qemu_get_byte(f);
  76     s->simenable = qemu_get_byte(f);
  77     s->forcestdby = qemu_get_byte(f);
  78
  79     return 0;
  80 }
  81
  82 static void omap3_hsusb_otg_reset(struct omap3_hsusb_otg_s *s)
  83 {
  84     s->rev = 0x33;
  85     s->sysconfig = 0;
  86     s->interfsel = 0x1;
  87     s->simenable = 0;
  88     s->forcestdby = 1;
  89 }
  90
  91 static uint32_t omap3_hsusb_otg_readb(void *opaque, target_phys_addr_t addr)
  92 {
  93     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
  94     if (addr < 0x200)
  95         return musb_read[0](s->musb, addr);
  96     if (addr < 0x400)
  97         return musb_read[0](s->musb, 0x20 + ((addr >> 3 ) & 0x3c));
  98     OMAP_BAD_REG(addr);
  99     return 0;
 100 }
 101
 102 static uint32_t omap3_hsusb_otg_readh(void *opaque, target_phys_addr_t addr)
 103 {
 104     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
 105     if (addr < 0x200)
 106         return musb_read[1](s->musb, addr);
 107     if (addr < 0x400)
 108         return musb_read[1](s->musb, 0x20 + ((addr >> 3 ) & 0x3c));
 109     OMAP_BAD_REG(addr);
 110     return 0;
 111 }
 112
 113 static uint32_t omap3_hsusb_otg_read(void *opaque, target_phys_addr_t addr)
 114 {
 115     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
 116
 117     if (addr < 0x200)
 118         return musb_read[2](s->musb, addr);
 119     if (addr < 0x400)
 120         return musb_read[2](s->musb, 0x20 + ((addr >> 3 ) & 0x3c));
 121
 122     switch (addr) {
 123         case 0x400: /* OTG_REVISION */
 124             TRACE("OTG_REVISION: 0x%08x", s->rev);
 125             return s->rev;
 126         case 0x404: /* OTG_SYSCONFIG */
 127             TRACE("OTG_SYSCONFIG: 0x%08x", s->sysconfig);
 128             return s->sysconfig;
 129         case 0x408: /* OTG_SYSSTATUS */
 130             TRACE("OTG_SYSSTATUS: 0x00000001");
 131             return 1; /* reset finished */
 132         case 0x40c: /* OTG_INTERFSEL */
 133             TRACE("OTG_INTERFSEL: 0x%08x", s->interfsel);
 134             return s->interfsel;
 135         case 0x410: /* OTG_SIMENABLE */
 136             TRACE("OTG_SIMENABLE: 0x%08x", s->simenable);
 137             return s->simenable;
 138         case 0x414: /* OTG_FORCESTDBY */
 139             TRACE("OTG_FORCESTDBY: 0x%08x", s->forcestdby);
 140             return s->forcestdby;
 141         default:
 142             break;
 143     }
 144     OMAP_BAD_REG(addr);
 145     return 0;
 146 }
 147
 148 static void omap3_hsusb_otg_writeb(void *opaque, target_phys_addr_t addr,
 149                                    uint32_t value)
 150 {
 151     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
 152
 153     if (addr < 0x200)
 154         musb_write[0](s->musb, addr, value);
 155     else if (addr < 0x400)
 156         musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 157     else
 158         OMAP_BAD_REG(addr);
 159 }
 160
 161 static void omap3_hsusb_otg_writeh(void *opaque, target_phys_addr_t addr,
 162                                    uint32_t value)
 163 {
 164     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
 165
 166     if (addr < 0x200)
 167         musb_write[1](s->musb, addr, value);
 168     else if (addr < 0x400)
 169         musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 170     else
 171         OMAP_BAD_REG(addr);
 172 }
 173
 174 static void omap3_hsusb_otg_write(void *opaque, target_phys_addr_t addr,
 175                                   uint32_t value)
 176 {
 177     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
 178
 179     if (addr < 0x200)
 180         musb_write[2](s->musb, addr, value);
 181     else if (addr < 0x400)
 182         musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value);
 183     else switch (addr) {
 184         case 0x400: /* OTG_REVISION */
 185         case 0x408: /* OTG_SYSSTATUS */
 186             OMAP_RO_REGV(addr, value);
 187             break;
 188         case 0x404: /* OTG_SYSCONFIG */
 189             TRACE("OTG_SYSCONFIG = 0x%08x", value);
 190             if (value & 2) /* SOFTRESET */
 191                 omap3_hsusb_otg_reset(s);
 192             s->sysconfig = value & 0x301f;
 193             break;
 194         case 0x40c: /* OTG_INTERFSEL */
 195             TRACE("OTG_INTERFSEL = 0x%08x", value);
 196             s->interfsel = value & 0x3;
 197             break;
 198         case 0x410: /* OTG_SIMENABLE */
 199             TRACE("OTG_SIMENABLE = 0x%08x", value);
 200             cpu_abort(cpu_single_env,
 201                       "%s: USB simulation mode not supported\n",
 202                       __FUNCTION__);
 203             break;
 204         case 0x414: /* OTG_FORCESTDBY */
 205             TRACE("OTG_FORCESTDBY = 0x%08x", value);
 206             s->forcestdby = value & 1;
 207             break;
 208         default:
 209             OMAP_BAD_REGV(addr, value);
 210             break;
 211     }
 212 }
 213
 214 static CPUReadMemoryFunc *omap3_hsusb_otg_readfn[] = {
 215     omap3_hsusb_otg_readb,
 216     omap3_hsusb_otg_readh,
 217     omap3_hsusb_otg_read,
 218 };
 219
 220 static CPUWriteMemoryFunc *omap3_hsusb_otg_writefn[] = {
 221     omap3_hsusb_otg_writeb,
 222     omap3_hsusb_otg_writeh,
 223     omap3_hsusb_otg_write,
 224 };
 225
 226 static void omap3_hsusb_musb_core_intr(void *opaque, int source, int level)
 227 {
 228     struct omap3_hsusb_otg_s *s = (struct omap3_hsusb_otg_s *)opaque;
 229     uint32_t value = musb_core_intr_get(s->musb);
 230     TRACE("intr 0x%08x, 0x%08x, 0x%08x", source, level, value);
 231     switch (source) {
 232     case musb_set_vbus:
 233        TRACE("ignoring VBUS");
 234        break;
 235     case musb_set_session:
 236        TRACE("ignoring SESSION");
 237        break;
 238     case musb_irq_tx:
 239     case musb_irq_rx:
 240        TRACE("rxtx");
 241        break;
 242        /* Fall through */
 243     default:
 244        TRACE("other");
 245     }
 246     qemu_set_irq(s->mc_irq, level);
 247 }
 248
 249 static void omap3_hsusb_otg_init(struct omap_target_agent_s *otg_ta,
 250                                  qemu_irq mc_irq,
 251                                  qemu_irq dma_irq,
 252                                  struct omap3_hsusb_otg_s *s)
 253 {
 254     s->mc_irq = mc_irq;
 255     s->dma_irq = dma_irq;
 256
 257     omap_l4_attach(otg_ta, 0, l4_register_io_memory(0,
 258                                                     omap3_hsusb_otg_readfn,
 259                                                     omap3_hsusb_otg_writefn,
 260                                                     s));
 261
 262     s->musb = musb_init(qemu_allocate_irqs(omap3_hsusb_musb_core_intr, s,
 263                                            __musb_irq_max));
 264     omap3_hsusb_otg_reset(s);
 265
 266     register_savevm("omap3_hsusb_otg", -1, 0,
 267                     omap3_hsusb_otg_save_state,
 268                     omap3_hsusb_otg_load_state,
 269                     s);
 270 }
 271 #endif
 272
 273 #ifdef OMAP3_HSUSB_HOST
 274 struct omap3_hsusb_host_s {
 275     qemu_irq ehci_irq;
 276     qemu_irq tll_irq;
 277
 278     uint32_t uhh_sysconfig;
 279     uint32_t uhh_hostconfig;
 280     uint32_t uhh_debug_csr;
 281 };
 282
 283 static void omap3_hsusb_host_save_state(QEMUFile *f, void *opaque)
 284 {
 285     struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
 286
 287     qemu_put_be32(f, s->uhh_sysconfig);
 288     qemu_put_be32(f, s->uhh_hostconfig);
 289     qemu_put_be32(f, s->uhh_debug_csr);
 290 }
 291
 292 static int omap3_hsusb_host_load_state(QEMUFile *f, void *opaque,
 293                                        int version_id)
 294 {
 295     struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
 296
 297     if (version_id)
 298         return -EINVAL;
 299
 300     s->uhh_sysconfig = qemu_get_be32(f);
 301     s->uhh_hostconfig = qemu_get_be32(f);
 302     s->uhh_debug_csr = qemu_get_be32(f);
 303
 304     return 0;
 305 }
 306
 307 static void omap3_hsusb_host_reset(struct omap3_hsusb_host_s *s)
 308 {
 309     s->uhh_sysconfig = 1;
 310     s->uhh_hostconfig = 0x700;
 311     s->uhh_debug_csr = 0x20;
 312     /* TODO: perform OHCI & EHCI reset */
 313 }
 314
 315 static uint32_t omap3_hsusb_host_read(void *opaque, target_phys_addr_t addr)
 316 {
 317     struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
 318
 319     switch (addr) {
 320         case 0x00: /* UHH_REVISION */
 321             return 0x10;
 322         case 0x10: /* UHH_SYSCONFIG */
 323             return s->uhh_sysconfig;
 324         case 0x14: /* UHH_SYSSTATUS */
 325             return 0x7; /* EHCI_RESETDONE | OHCI_RESETDONE | RESETDONE */
 326         case 0x40: /* UHH_HOSTCONFIG */
 327             return s->uhh_hostconfig;
 328         case 0x44: /* UHH_DEBUG_CSR */
 329             return s->uhh_debug_csr;
 330         default:
 331             break;
 332     }
 333     OMAP_BAD_REG(addr);
 334     return 0;
 335 }
 336
 337 static void omap3_hsusb_host_write(void *opaque, target_phys_addr_t addr,
 338                                    uint32_t value)
 339 {
 340     struct omap3_hsusb_host_s *s = (struct omap3_hsusb_host_s *)opaque;
 341
 342     switch (addr) {
 343         case 0x00: /* UHH_REVISION */
 344         case 0x14: /* UHH_SYSSTATUS */
 345             OMAP_RO_REGV(addr, value);
 346             break;
 347         case 0x10: /* UHH_SYSCONFIG */
 348             s->uhh_sysconfig = value & 0x311d;
 349             if (value & 2) { /* SOFTRESET */
 350                 omap3_hsusb_host_reset(s);
 351             }
 352             break;
 353         case 0x40: /* UHH_HOSTCONFIG */
 354             s->uhh_hostconfig = value & 0x1f3d;
 355             break;
 356         case 0x44: /* UHH_DEBUG_CSR */
 357             s->uhh_debug_csr = value & 0xf00ff;
 358             break;
 359         default:
 360             OMAP_BAD_REGV(addr, value);
 361             break;
 362     }
 363 }
 364
 365 static CPUReadMemoryFunc *omap3_hsusb_host_readfn[] = {
 366     omap_badwidth_read32,
 367     omap_badwidth_read32,
 368     omap3_hsusb_host_read,
 369 };
 370
 371 static CPUWriteMemoryFunc *omap3_hsusb_host_writefn[] = {
 372     omap_badwidth_write32,
 373     omap_badwidth_write32,
 374     omap3_hsusb_host_write,
 375 };
 376
 377 static uint32_t omap3_hsusb_ehci_read(void *opaque, target_phys_addr_t addr)
 378 {
 379     TRACE(OMAP_FMT_plx, addr);
 380     return 0;
 381 }
 382
 383 static void omap3_hsusb_ehci_write(void *opaque, target_phys_addr_t addr,
 384                                    uint32_t value)
 385 {
 386     TRACE(OMAP_FMT_plx " = 0x%08x", addr, value);
 387 }
 388
 389 static CPUReadMemoryFunc *omap3_hsusb_ehci_readfn[] = {
 390     omap_badwidth_read32,
 391     omap_badwidth_read32,
 392     omap3_hsusb_ehci_read,
 393 };
 394
 395 static CPUWriteMemoryFunc *omap3_hsusb_ehci_writefn[] = {
 396     omap_badwidth_write32,
 397     omap_badwidth_write32,
 398     omap3_hsusb_ehci_write,
 399 };
 400
 401 static uint32_t omap3_hsusb_tll_read(void *opaque, target_phys_addr_t addr)
 402 {
 403     TRACE(OMAP_FMT_plx, addr);
 404     return 0;
 405 }
 406
 407 static void omap3_hsusb_tll_write(void *opaque, target_phys_addr_t addr,
 408                                   uint32_t value)
 409 {
 410     TRACE(OMAP_FMT_plx " = 0x%08x", addr, value);
 411 }
 412
 413 static CPUReadMemoryFunc *omap3_hsusb_tll_readfn[] = {
 414     omap_badwidth_read32,
 415     omap_badwidth_read32,
 416     omap3_hsusb_tll_read,
 417 };
 418
 419 static CPUWriteMemoryFunc *omap3_hsusb_tll_writefn[] = {
 420     omap_badwidth_write32,
 421     omap_badwidth_write32,
 422     omap3_hsusb_tll_write,
 423 };
 424
 425 static void omap3_hsusb_host_init(struct omap_target_agent_s *host_ta,
 426                                   struct omap_target_agent_s *tll_ta,
 427                                   qemu_irq ohci_irq,
 428                                   qemu_irq ehci_irq,
 429                                   qemu_irq tll_irq,
 430                                   struct omap3_hsusb_host_s *s)
 431 {
 432     s->ehci_irq = ehci_irq;
 433     s->tll_irq  = tll_irq;
 434
 435     omap_l4_attach(tll_ta, 0, l4_register_io_memory(0,
 436                                                     omap3_hsusb_tll_readfn,
 437                                                     omap3_hsusb_tll_writefn,
 438                                                     s));
 439     omap_l4_attach(host_ta, 0, l4_register_io_memory(0,
 440                                                      omap3_hsusb_host_readfn,
 441                                                      omap3_hsusb_host_writefn,
 442                                                      s));
 443     omap_l4_attach(host_ta, 1, usb_ohci_init_omap(omap_l4_base(host_ta, 1),
 444                                                   omap_l4_size(host_ta, 1),
 445                                                   3, ohci_irq));
 446     omap_l4_attach(host_ta, 2, l4_register_io_memory(0,
 447                                                      omap3_hsusb_ehci_readfn,
 448                                                      omap3_hsusb_ehci_writefn,
 449                                                      s));
 450
 451     omap3_hsusb_host_reset(s);
 452
 453     register_savevm("omap3_hsusb_host", -1, 0,
 454                     omap3_hsusb_host_save_state,
 455                     omap3_hsusb_host_load_state, s);
 456 }
 457 #endif
 458
 459 struct omap3_hsusb_s {
 460 #ifdef OMAP3_HSUSB_OTG
 461     struct omap3_hsusb_otg_s otg;
 462 #endif
 463 #ifdef OMAP3_HSUSB_HOST
 464     struct omap3_hsusb_host_s host;
 465 #endif
 466 };
 467
 468 struct omap3_hsusb_s *omap3_hsusb_init(struct omap_target_agent_s *otg_ta,
 469                                        struct omap_target_agent_s *host_ta,
 470                                        struct omap_target_agent_s *tll_ta,
 471                                        qemu_irq mc_irq,
 472                                        qemu_irq dma_irq,
 473                                        qemu_irq ohci_irq,
 474                                        qemu_irq ehci_irq,
 475                                        qemu_irq tll_irq)
 476 {
 477     struct omap3_hsusb_s *s = qemu_mallocz(sizeof(struct omap3_hsusb_s));
 478 #ifdef OMAP3_HSUSB_HOST
 479     omap3_hsusb_host_init(host_ta, tll_ta,
 480                           ohci_irq, ehci_irq, tll_irq,
 481                           &s->host);
 482 #endif
 483 #ifdef OMAP3_HSUSB_OTG
 484     omap3_hsusb_otg_init(otg_ta, mc_irq, dma_irq, &s->otg);
 485 #endif
 486     return s;
 487 }
 488