2 * Texas Instruments OMAP processors.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 # define hw_omap_h "omap.h"
23 # define OMAP_EMIFS_BASE 0x00000000
24 # define OMAP2_Q0_BASE 0x00000000
25 # define OMAP_CS0_BASE 0x00000000
26 # define OMAP_CS1_BASE 0x04000000
27 # define OMAP_CS2_BASE 0x08000000
28 # define OMAP_CS3_BASE 0x0c000000
29 # define OMAP_EMIFF_BASE 0x10000000
30 # define OMAP_IMIF_BASE 0x20000000
31 # define OMAP_LOCALBUS_BASE 0x30000000
32 # define OMAP2_Q1_BASE 0x40000000
33 # define OMAP2_L4_BASE 0x48000000
34 # define OMAP2_SRAM_BASE 0x40200000
35 # define OMAP2_L3_BASE 0x68000000
36 # define OMAP2_Q2_BASE 0x80000000
37 # define OMAP2_Q3_BASE 0xc0000000
38 # define OMAP3_Q1_BASE 0x40000000
39 # define OMAP3_L4_BASE 0x48000000
40 # define OMAP3_SRAM_BASE 0x40200000
41 # define OMAP3_L3_BASE 0x68000000
42 # define OMAP3_Q2_BASE 0x80000000
43 # define OMAP3_Q3_BASE 0xc0000000
44 # define OMAP_MPUI_BASE 0xe1000000
46 # define OMAP730_SRAM_SIZE 0x00032000
47 # define OMAP15XX_SRAM_SIZE 0x00030000
48 # define OMAP16XX_SRAM_SIZE 0x00004000
49 # define OMAP1611_SRAM_SIZE 0x0003e800
50 # define OMAP242X_SRAM_SIZE 0x000a0000
51 # define OMAP243X_SRAM_SIZE 0x00010000
52 # define OMAP3530_SRAM_SIZE 0x00010000
53 # define OMAP_CS0_SIZE 0x04000000
54 # define OMAP_CS1_SIZE 0x04000000
55 # define OMAP_CS2_SIZE 0x04000000
56 # define OMAP_CS3_SIZE 0x04000000
59 struct omap_mpu_state_s;
60 typedef struct clk *omap_clk;
61 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
62 void omap_clk_init(struct omap_mpu_state_s *mpu);
63 void omap_clk_adduser(struct clk *clk, qemu_irq user);
64 void omap_clk_get(omap_clk clk);
65 void omap_clk_put(omap_clk clk);
66 void omap_clk_onoff(omap_clk clk, int on);
67 void omap_clk_canidle(omap_clk clk, int can);
68 void omap_clk_setrate(omap_clk clk, int divide, int multiply);
69 int64_t omap_clk_getrate(omap_clk clk);
70 void omap_clk_reparent(omap_clk clk, omap_clk parent);
75 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
77 struct omap_target_agent_s;
78 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
79 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
81 # define l4_register_io_memory cpu_register_io_memory
83 struct omap_intr_handler_s;
84 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
85 unsigned long size, unsigned char nbanks, qemu_irq **pins,
86 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
87 struct omap_intr_handler_s *omap2_inth_init(struct omap_mpu_state_s *mpu,
88 target_phys_addr_t base,
89 int size, int nbanks, qemu_irq **pins,
90 qemu_irq parent_irq, qemu_irq parent_fiq,
91 omap_clk fclk, omap_clk iclk);
92 void omap_inth_reset(struct omap_intr_handler_s *s);
95 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
96 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
97 struct omap_mpu_state_s *mpu);
100 struct omap3_prm_s *omap3_prm_init(struct omap_target_agent_s *ta,
101 qemu_irq mpu_int, qemu_irq iva_int,
102 struct omap_mpu_state_s *mpu);
105 struct omap3_cm_s *omap3_cm_init(struct omap_target_agent_s *ta,
106 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
107 struct omap_mpu_state_s *mpu);
109 struct omap_sysctl_s;
110 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
111 omap_clk iclk, struct omap_mpu_state_s *mpu);
114 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
115 void omap_sdrc_write_mcfg(struct omap_sdrc_s *s, uint32_t value, uint32_t cs);
118 struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
119 target_phys_addr_t base, qemu_irq irq);
120 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
121 void (*base_upd)(void *opaque, target_phys_addr_t new),
122 void (*unmap)(void *opaque), void *opaque,
123 CPUReadMemoryFunc **nand_readfn,
124 CPUWriteMemoryFunc **nand_writefn);
127 * Common IRQ numbers for level 1 interrupt handler
128 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
130 # define OMAP_INT_CAMERA 1
131 # define OMAP_INT_FIQ 3
132 # define OMAP_INT_RTDX 6
133 # define OMAP_INT_DSP_MMU_ABORT 7
134 # define OMAP_INT_HOST 8
135 # define OMAP_INT_ABORT 9
136 # define OMAP_INT_BRIDGE_PRIV 13
137 # define OMAP_INT_GPIO_BANK1 14
138 # define OMAP_INT_UART3 15
139 # define OMAP_INT_TIMER3 16
140 # define OMAP_INT_DMA_CH0_6 19
141 # define OMAP_INT_DMA_CH1_7 20
142 # define OMAP_INT_DMA_CH2_8 21
143 # define OMAP_INT_DMA_CH3 22
144 # define OMAP_INT_DMA_CH4 23
145 # define OMAP_INT_DMA_CH5 24
146 # define OMAP_INT_DMA_LCD 25
147 # define OMAP_INT_TIMER1 26
148 # define OMAP_INT_WD_TIMER 27
149 # define OMAP_INT_BRIDGE_PUB 28
150 # define OMAP_INT_TIMER2 30
151 # define OMAP_INT_LCD_CTRL 31
154 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
156 # define OMAP_INT_15XX_IH2_IRQ 0
157 # define OMAP_INT_15XX_LB_MMU 17
158 # define OMAP_INT_15XX_LOCAL_BUS 29
161 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
163 # define OMAP_INT_1510_SPI_TX 4
164 # define OMAP_INT_1510_SPI_RX 5
165 # define OMAP_INT_1510_DSP_MAILBOX1 10
166 # define OMAP_INT_1510_DSP_MAILBOX2 11
169 * OMAP-310 specific IRQ numbers for level 1 interrupt handler
171 # define OMAP_INT_310_McBSP2_TX 4
172 # define OMAP_INT_310_McBSP2_RX 5
173 # define OMAP_INT_310_HSB_MAILBOX1 12
174 # define OMAP_INT_310_HSAB_MMU 18
177 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
179 # define OMAP_INT_1610_IH2_IRQ 0
180 # define OMAP_INT_1610_IH2_FIQ 2
181 # define OMAP_INT_1610_McBSP2_TX 4
182 # define OMAP_INT_1610_McBSP2_RX 5
183 # define OMAP_INT_1610_DSP_MAILBOX1 10
184 # define OMAP_INT_1610_DSP_MAILBOX2 11
185 # define OMAP_INT_1610_LCD_LINE 12
186 # define OMAP_INT_1610_GPTIMER1 17
187 # define OMAP_INT_1610_GPTIMER2 18
188 # define OMAP_INT_1610_SSR_FIFO_0 29
191 * OMAP-730 specific IRQ numbers for level 1 interrupt handler
193 # define OMAP_INT_730_IH2_FIQ 0
194 # define OMAP_INT_730_IH2_IRQ 1
195 # define OMAP_INT_730_USB_NON_ISO 2
196 # define OMAP_INT_730_USB_ISO 3
197 # define OMAP_INT_730_ICR 4
198 # define OMAP_INT_730_EAC 5
199 # define OMAP_INT_730_GPIO_BANK1 6
200 # define OMAP_INT_730_GPIO_BANK2 7
201 # define OMAP_INT_730_GPIO_BANK3 8
202 # define OMAP_INT_730_McBSP2TX 10
203 # define OMAP_INT_730_McBSP2RX 11
204 # define OMAP_INT_730_McBSP2RX_OVF 12
205 # define OMAP_INT_730_LCD_LINE 14
206 # define OMAP_INT_730_GSM_PROTECT 15
207 # define OMAP_INT_730_TIMER3 16
208 # define OMAP_INT_730_GPIO_BANK5 17
209 # define OMAP_INT_730_GPIO_BANK6 18
210 # define OMAP_INT_730_SPGIO_WR 29
213 * Common IRQ numbers for level 2 interrupt handler
215 # define OMAP_INT_KEYBOARD 1
216 # define OMAP_INT_uWireTX 2
217 # define OMAP_INT_uWireRX 3
218 # define OMAP_INT_I2C 4
219 # define OMAP_INT_MPUIO 5
220 # define OMAP_INT_USB_HHC_1 6
221 # define OMAP_INT_McBSP3TX 10
222 # define OMAP_INT_McBSP3RX 11
223 # define OMAP_INT_McBSP1TX 12
224 # define OMAP_INT_McBSP1RX 13
225 # define OMAP_INT_UART1 14
226 # define OMAP_INT_UART2 15
227 # define OMAP_INT_USB_W2FC 20
228 # define OMAP_INT_1WIRE 21
229 # define OMAP_INT_OS_TIMER 22
230 # define OMAP_INT_OQN 23
231 # define OMAP_INT_GAUGE_32K 24
232 # define OMAP_INT_RTC_TIMER 25
233 # define OMAP_INT_RTC_ALARM 26
234 # define OMAP_INT_DSP_MMU 28
237 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
239 # define OMAP_INT_1510_BT_MCSI1TX 16
240 # define OMAP_INT_1510_BT_MCSI1RX 17
241 # define OMAP_INT_1510_SoSSI_MATCH 19
242 # define OMAP_INT_1510_MEM_STICK 27
243 # define OMAP_INT_1510_COM_SPI_RO 31
246 * OMAP-310 specific IRQ numbers for level 2 interrupt handler
248 # define OMAP_INT_310_FAC 0
249 # define OMAP_INT_310_USB_HHC_2 7
250 # define OMAP_INT_310_MCSI1_FE 16
251 # define OMAP_INT_310_MCSI2_FE 17
252 # define OMAP_INT_310_USB_W2FC_ISO 29
253 # define OMAP_INT_310_USB_W2FC_NON_ISO 30
254 # define OMAP_INT_310_McBSP2RX_OF 31
257 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
259 # define OMAP_INT_1610_FAC 0
260 # define OMAP_INT_1610_USB_HHC_2 7
261 # define OMAP_INT_1610_USB_OTG 8
262 # define OMAP_INT_1610_SoSSI 9
263 # define OMAP_INT_1610_BT_MCSI1TX 16
264 # define OMAP_INT_1610_BT_MCSI1RX 17
265 # define OMAP_INT_1610_SoSSI_MATCH 19
266 # define OMAP_INT_1610_MEM_STICK 27
267 # define OMAP_INT_1610_McBSP2RX_OF 31
268 # define OMAP_INT_1610_STI 32
269 # define OMAP_INT_1610_STI_WAKEUP 33
270 # define OMAP_INT_1610_GPTIMER3 34
271 # define OMAP_INT_1610_GPTIMER4 35
272 # define OMAP_INT_1610_GPTIMER5 36
273 # define OMAP_INT_1610_GPTIMER6 37
274 # define OMAP_INT_1610_GPTIMER7 38
275 # define OMAP_INT_1610_GPTIMER8 39
276 # define OMAP_INT_1610_GPIO_BANK2 40
277 # define OMAP_INT_1610_GPIO_BANK3 41
278 # define OMAP_INT_1610_MMC2 42
279 # define OMAP_INT_1610_CF 43
280 # define OMAP_INT_1610_WAKE_UP_REQ 46
281 # define OMAP_INT_1610_GPIO_BANK4 48
282 # define OMAP_INT_1610_SPI 49
283 # define OMAP_INT_1610_DMA_CH6 53
284 # define OMAP_INT_1610_DMA_CH7 54
285 # define OMAP_INT_1610_DMA_CH8 55
286 # define OMAP_INT_1610_DMA_CH9 56
287 # define OMAP_INT_1610_DMA_CH10 57
288 # define OMAP_INT_1610_DMA_CH11 58
289 # define OMAP_INT_1610_DMA_CH12 59
290 # define OMAP_INT_1610_DMA_CH13 60
291 # define OMAP_INT_1610_DMA_CH14 61
292 # define OMAP_INT_1610_DMA_CH15 62
293 # define OMAP_INT_1610_NAND 63
296 * OMAP-730 specific IRQ numbers for level 2 interrupt handler
298 # define OMAP_INT_730_HW_ERRORS 0
299 # define OMAP_INT_730_NFIQ_PWR_FAIL 1
300 # define OMAP_INT_730_CFCD 2
301 # define OMAP_INT_730_CFIREQ 3
302 # define OMAP_INT_730_I2C 4
303 # define OMAP_INT_730_PCC 5
304 # define OMAP_INT_730_MPU_EXT_NIRQ 6
305 # define OMAP_INT_730_SPI_100K_1 7
306 # define OMAP_INT_730_SYREN_SPI 8
307 # define OMAP_INT_730_VLYNQ 9
308 # define OMAP_INT_730_GPIO_BANK4 10
309 # define OMAP_INT_730_McBSP1TX 11
310 # define OMAP_INT_730_McBSP1RX 12
311 # define OMAP_INT_730_McBSP1RX_OF 13
312 # define OMAP_INT_730_UART_MODEM_IRDA_2 14
313 # define OMAP_INT_730_UART_MODEM_1 15
314 # define OMAP_INT_730_MCSI 16
315 # define OMAP_INT_730_uWireTX 17
316 # define OMAP_INT_730_uWireRX 18
317 # define OMAP_INT_730_SMC_CD 19
318 # define OMAP_INT_730_SMC_IREQ 20
319 # define OMAP_INT_730_HDQ_1WIRE 21
320 # define OMAP_INT_730_TIMER32K 22
321 # define OMAP_INT_730_MMC_SDIO 23
322 # define OMAP_INT_730_UPLD 24
323 # define OMAP_INT_730_USB_HHC_1 27
324 # define OMAP_INT_730_USB_HHC_2 28
325 # define OMAP_INT_730_USB_GENI 29
326 # define OMAP_INT_730_USB_OTG 30
327 # define OMAP_INT_730_CAMERA_IF 31
328 # define OMAP_INT_730_RNG 32
329 # define OMAP_INT_730_DUAL_MODE_TIMER 33
330 # define OMAP_INT_730_DBB_RF_EN 34
331 # define OMAP_INT_730_MPUIO_KEYPAD 35
332 # define OMAP_INT_730_SHA1_MD5 36
333 # define OMAP_INT_730_SPI_100K_2 37
334 # define OMAP_INT_730_RNG_IDLE 38
335 # define OMAP_INT_730_MPUIO 39
336 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
337 # define OMAP_INT_730_LLPC_OE_FALLING 41
338 # define OMAP_INT_730_LLPC_OE_RISING 42
339 # define OMAP_INT_730_LLPC_VSYNC 43
340 # define OMAP_INT_730_WAKE_UP_REQ 46
341 # define OMAP_INT_730_DMA_CH6 53
342 # define OMAP_INT_730_DMA_CH7 54
343 # define OMAP_INT_730_DMA_CH8 55
344 # define OMAP_INT_730_DMA_CH9 56
345 # define OMAP_INT_730_DMA_CH10 57
346 # define OMAP_INT_730_DMA_CH11 58
347 # define OMAP_INT_730_DMA_CH12 59
348 # define OMAP_INT_730_DMA_CH13 60
349 # define OMAP_INT_730_DMA_CH14 61
350 # define OMAP_INT_730_DMA_CH15 62
351 # define OMAP_INT_730_NAND 63
354 * OMAP-24xx common IRQ numbers
356 # define OMAP_INT_24XX_STI 4
357 # define OMAP_INT_24XX_SYS_NIRQ 7
358 # define OMAP_INT_24XX_L3_IRQ 10
359 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
360 # define OMAP_INT_24XX_SDMA_IRQ0 12
361 # define OMAP_INT_24XX_SDMA_IRQ1 13
362 # define OMAP_INT_24XX_SDMA_IRQ2 14
363 # define OMAP_INT_24XX_SDMA_IRQ3 15
364 # define OMAP_INT_243X_MCBSP2_IRQ 16
365 # define OMAP_INT_243X_MCBSP3_IRQ 17
366 # define OMAP_INT_243X_MCBSP4_IRQ 18
367 # define OMAP_INT_243X_MCBSP5_IRQ 19
368 # define OMAP_INT_24XX_GPMC_IRQ 20
369 # define OMAP_INT_24XX_GUFFAW_IRQ 21
370 # define OMAP_INT_24XX_IVA_IRQ 22
371 # define OMAP_INT_24XX_EAC_IRQ 23
372 # define OMAP_INT_24XX_CAM_IRQ 24
373 # define OMAP_INT_24XX_DSS_IRQ 25
374 # define OMAP_INT_24XX_MAIL_U0_MPU 26
375 # define OMAP_INT_24XX_DSP_UMA 27
376 # define OMAP_INT_24XX_DSP_MMU 28
377 # define OMAP_INT_24XX_GPIO_BANK1 29
378 # define OMAP_INT_24XX_GPIO_BANK2 30
379 # define OMAP_INT_24XX_GPIO_BANK3 31
380 # define OMAP_INT_24XX_GPIO_BANK4 32
381 # define OMAP_INT_243X_GPIO_BANK5 33
382 # define OMAP_INT_24XX_MAIL_U3_MPU 34
383 # define OMAP_INT_24XX_WDT3 35
384 # define OMAP_INT_24XX_WDT4 36
385 # define OMAP_INT_24XX_GPTIMER1 37
386 # define OMAP_INT_24XX_GPTIMER2 38
387 # define OMAP_INT_24XX_GPTIMER3 39
388 # define OMAP_INT_24XX_GPTIMER4 40
389 # define OMAP_INT_24XX_GPTIMER5 41
390 # define OMAP_INT_24XX_GPTIMER6 42
391 # define OMAP_INT_24XX_GPTIMER7 43
392 # define OMAP_INT_24XX_GPTIMER8 44
393 # define OMAP_INT_24XX_GPTIMER9 45
394 # define OMAP_INT_24XX_GPTIMER10 46
395 # define OMAP_INT_24XX_GPTIMER11 47
396 # define OMAP_INT_24XX_GPTIMER12 48
397 # define OMAP_INT_24XX_PKA_IRQ 50
398 # define OMAP_INT_24XX_SHA1MD5_IRQ 51
399 # define OMAP_INT_24XX_RNG_IRQ 52
400 # define OMAP_INT_24XX_MG_IRQ 53
401 # define OMAP_INT_24XX_I2C1_IRQ 56
402 # define OMAP_INT_24XX_I2C2_IRQ 57
403 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
404 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
405 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
406 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
407 # define OMAP_INT_243X_MCBSP1_IRQ 64
408 # define OMAP_INT_24XX_MCSPI1_IRQ 65
409 # define OMAP_INT_24XX_MCSPI2_IRQ 66
410 # define OMAP_INT_24XX_SSI1_IRQ0 67
411 # define OMAP_INT_24XX_SSI1_IRQ1 68
412 # define OMAP_INT_24XX_SSI2_IRQ0 69
413 # define OMAP_INT_24XX_SSI2_IRQ1 70
414 # define OMAP_INT_24XX_SSI_GDD_IRQ 71
415 # define OMAP_INT_24XX_UART1_IRQ 72
416 # define OMAP_INT_24XX_UART2_IRQ 73
417 # define OMAP_INT_24XX_UART3_IRQ 74
418 # define OMAP_INT_24XX_USB_IRQ_GEN 75
419 # define OMAP_INT_24XX_USB_IRQ_NISO 76
420 # define OMAP_INT_24XX_USB_IRQ_ISO 77
421 # define OMAP_INT_24XX_USB_IRQ_HGEN 78
422 # define OMAP_INT_24XX_USB_IRQ_HSOF 79
423 # define OMAP_INT_24XX_USB_IRQ_OTG 80
424 # define OMAP_INT_24XX_VLYNQ_IRQ 81
425 # define OMAP_INT_24XX_MMC_IRQ 83
426 # define OMAP_INT_24XX_MS_IRQ 84
427 # define OMAP_INT_24XX_FAC_IRQ 85
428 # define OMAP_INT_24XX_MCSPI3_IRQ 91
429 # define OMAP_INT_243X_HS_USB_MC 92
430 # define OMAP_INT_243X_HS_USB_DMA 93
431 # define OMAP_INT_243X_CARKIT 94
432 # define OMAP_INT_34XX_GPTIMER12 95
435 * OMAP-35XX common IRQ numbers
437 # define OMAP_INT_35XX_SYS_NIRQ 7
438 # define OMAP_INT_35XX_PRCM_MPU_IRQ 11
439 # define OMAP_INT_35XX_SDMA_IRQ0 12
440 # define OMAP_INT_35XX_SDMA_IRQ1 13
441 # define OMAP_INT_35XX_SDMA_IRQ2 14
442 # define OMAP_INT_35XX_SDMA_IRQ3 15
443 # define OMAP_INT_35XX_MCBSP1_IRQ 16
444 # define OMAP_INT_35XX_MCBSP2_IRQ 17
445 # define OMAP_INT_35XX_GPMC_IRQ 20
446 # define OMAP_INT_35XX_MCBSP3_IRQ 22
447 # define OMAP_INT_35XX_MCBSP4_IRQ 23
448 # define OMAP_INT_35XX_CAM_IRQ 24
449 # define OMAP_INT_35XX_DSS_IRQ 25
450 # define OMAP_INT_35XX_MAIL_U0_MPU 26
451 # define OMAP_INT_35XX_MCBSP5_IRQ 27
452 # define OMAP_INT_35XX_DSP_MMU 28
453 # define OMAP_INT_35XX_GPIO_BANK1 29
454 # define OMAP_INT_35XX_GPIO_BANK2 30
455 # define OMAP_INT_35XX_GPIO_BANK3 31
456 # define OMAP_INT_35XX_GPIO_BANK4 32
457 # define OMAP_INT_35XX_GPIO_BANK5 33
458 # define OMAP_INT_35XX_GPIO_BANK6 34
459 # define OMAP_INT_35XX_WDT3 36
460 # define OMAP_INT_35XX_GPTIMER1 37
461 # define OMAP_INT_35XX_GPTIMER2 38
462 # define OMAP_INT_35XX_GPTIMER3 39
463 # define OMAP_INT_35XX_GPTIMER4 40
464 # define OMAP_INT_35XX_GPTIMER5 41
465 # define OMAP_INT_35XX_GPTIMER6 42
466 # define OMAP_INT_35XX_GPTIMER7 43
467 # define OMAP_INT_35XX_GPTIMER8 44
468 # define OMAP_INT_35XX_GPTIMER9 45
469 # define OMAP_INT_35XX_GPTIMER10 46
470 # define OMAP_INT_35XX_GPTIMER11 47
471 # define OMAP_INT_35XX_MG_IRQ 53
472 # define OMAP_INT_35XX_MCBSP4_IRQ_TX 54
473 # define OMAP_INT_35XX_MCBSP4_IRQ_RX 55
474 # define OMAP_INT_35XX_I2C1_IRQ 56
475 # define OMAP_INT_35XX_I2C2_IRQ 57
476 # define OMAP_INT_35XX_MCBSP1_IRQ_TX 59
477 # define OMAP_INT_35XX_MCBSP1_IRQ_RX 60
478 # define OMAP_INT_35XX_I2C3_IRQ 61
479 # define OMAP_INT_35XX_MCBSP2_IRQ_TX 62
480 # define OMAP_INT_35XX_MCBSP2_IRQ_RX 63
481 # define OMAP_INT_35XX_MCSPI1_IRQ 65
482 # define OMAP_INT_35XX_MCSPI2_IRQ 66
483 # define OMAP_INT_35XX_UART1_IRQ 72
484 # define OMAP_INT_35XX_UART2_IRQ 73
485 # define OMAP_INT_35XX_UART3_IRQ 74
486 # define OMAP_INT_35XX_MCBSP5_IRQ_TX 81
487 # define OMAP_INT_35XX_MCBSP5_IRQ_RX 82
488 # define OMAP_INT_35XX_MMC1_IRQ 83
489 # define OMAP_INT_35XX_MS_IRQ 84
490 # define OMAP_INT_35XX_MMC2_IRQ 86
491 # define OMAP_INT_35XX_MCBSP3_IRQ_TX 89
492 # define OMAP_INT_35XX_MCBSP3_IRQ_RX 90
493 # define OMAP_INT_35XX_MCSPI3_IRQ 91
494 # define OMAP_INT_35XX_HS_USB_MC 92
495 # define OMAP_INT_35XX_HS_USB_DMA 93
496 # define OMAP_INT_35XX_MMC3_IRQ 94
497 # define OMAP_INT_35XX_GPTIMER12 95
500 enum omap_dma_model {
508 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
509 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
510 enum omap_dma_model model);
511 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
512 struct omap_mpu_state_s *mpu, int fifo,
513 int chans, omap_clk iclk, omap_clk fclk);
514 void omap_dma_reset(struct soc_dma_s *s);
521 /* Only used in OMAP DMA 3.x gigacells */
525 imif, /* omap16xx: ocp_t1 */
527 local, /* omap16xx: ocp_t2 */
529 __omap_dma_port_last,
537 } omap_dma_addressing_t;
539 /* Only used in OMAP DMA 3.x gigacells */
540 struct omap_dma_lcd_channel_s {
541 enum omap_dma_port src;
542 target_phys_addr_t src_f1_top;
543 target_phys_addr_t src_f1_bottom;
544 target_phys_addr_t src_f2_top;
545 target_phys_addr_t src_f2_bottom;
547 /* Used in OMAP DMA 3.2 gigacell */
548 unsigned char brust_f1;
549 unsigned char pack_f1;
550 unsigned char data_type_f1;
551 unsigned char brust_f2;
552 unsigned char pack_f2;
553 unsigned char data_type_f2;
554 unsigned char end_prog;
555 unsigned char repeat;
556 unsigned char auto_init;
557 unsigned char priority;
559 unsigned char running;
561 unsigned char omap_3_1_compatible_disable;
563 unsigned char lch_type;
564 int16_t element_index_f1;
565 int16_t element_index_f2;
566 int32_t frame_index_f1;
567 int32_t frame_index_f2;
568 uint16_t elements_f1;
570 uint16_t elements_f2;
572 omap_dma_addressing_t mode_f1;
573 omap_dma_addressing_t mode_f2;
575 /* Destination port is fixed. */
581 ram_addr_t phys_framebuffer[2];
583 struct omap_mpu_state_s *mpu;
584 } *omap_dma_get_lcdch(struct soc_dma_s *s);
587 * DMA request numbers for OMAP1
588 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
590 # define OMAP_DMA_NO_DEVICE 0
591 # define OMAP_DMA_MCSI1_TX 1
592 # define OMAP_DMA_MCSI1_RX 2
593 # define OMAP_DMA_I2C_RX 3
594 # define OMAP_DMA_I2C_TX 4
595 # define OMAP_DMA_EXT_NDMA_REQ0 5
596 # define OMAP_DMA_EXT_NDMA_REQ1 6
597 # define OMAP_DMA_UWIRE_TX 7
598 # define OMAP_DMA_MCBSP1_TX 8
599 # define OMAP_DMA_MCBSP1_RX 9
600 # define OMAP_DMA_MCBSP3_TX 10
601 # define OMAP_DMA_MCBSP3_RX 11
602 # define OMAP_DMA_UART1_TX 12
603 # define OMAP_DMA_UART1_RX 13
604 # define OMAP_DMA_UART2_TX 14
605 # define OMAP_DMA_UART2_RX 15
606 # define OMAP_DMA_MCBSP2_TX 16
607 # define OMAP_DMA_MCBSP2_RX 17
608 # define OMAP_DMA_UART3_TX 18
609 # define OMAP_DMA_UART3_RX 19
610 # define OMAP_DMA_CAMERA_IF_RX 20
611 # define OMAP_DMA_MMC_TX 21
612 # define OMAP_DMA_MMC_RX 22
613 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
614 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
615 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
616 # define OMAP_DMA_USB_W2FC_RX0 26
617 # define OMAP_DMA_USB_W2FC_RX1 27
618 # define OMAP_DMA_USB_W2FC_RX2 28
619 # define OMAP_DMA_USB_W2FC_TX0 29
620 # define OMAP_DMA_USB_W2FC_TX1 30
621 # define OMAP_DMA_USB_W2FC_TX2 31
623 /* These are only for 1610 */
624 # define OMAP_DMA_CRYPTO_DES_IN 32
625 # define OMAP_DMA_SPI_TX 33
626 # define OMAP_DMA_SPI_RX 34
627 # define OMAP_DMA_CRYPTO_HASH 35
628 # define OMAP_DMA_CCP_ATTN 36
629 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
630 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
631 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
632 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
633 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
634 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
635 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
636 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
637 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
638 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
639 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
640 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
641 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
642 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
643 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
644 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
645 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
646 # define OMAP_DMA_MMC2_TX 54
647 # define OMAP_DMA_MMC2_RX 55
648 # define OMAP_DMA_CRYPTO_DES_OUT 56
651 * DMA request numbers for the OMAP2
653 # define OMAP24XX_DMA_NO_DEVICE 0
654 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
655 # define OMAP24XX_DMA_EXT_DMAREQ0 2
656 # define OMAP24XX_DMA_EXT_DMAREQ1 3
657 # define OMAP24XX_DMA_GPMC 4
658 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
659 # define OMAP24XX_DMA_DSS 6
660 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
661 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
662 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
663 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
664 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
665 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
666 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
667 # define OMAP24XX_DMA_EXT_DMAREQ2 14
668 # define OMAP24XX_DMA_EXT_DMAREQ3 15
669 # define OMAP24XX_DMA_EXT_DMAREQ4 16
670 # define OMAP24XX_DMA_EAC_AC_RD 17
671 # define OMAP24XX_DMA_EAC_AC_WR 18
672 # define OMAP24XX_DMA_EAC_MD_UL_RD 19
673 # define OMAP24XX_DMA_EAC_MD_UL_WR 20
674 # define OMAP24XX_DMA_EAC_MD_DL_RD 21
675 # define OMAP24XX_DMA_EAC_MD_DL_WR 22
676 # define OMAP24XX_DMA_EAC_BT_UL_RD 23
677 # define OMAP24XX_DMA_EAC_BT_UL_WR 24
678 # define OMAP24XX_DMA_EAC_BT_DL_RD 25
679 # define OMAP24XX_DMA_EAC_BT_DL_WR 26
680 # define OMAP24XX_DMA_I2C1_TX 27
681 # define OMAP24XX_DMA_I2C1_RX 28
682 # define OMAP24XX_DMA_I2C2_TX 29
683 # define OMAP24XX_DMA_I2C2_RX 30
684 # define OMAP24XX_DMA_MCBSP1_TX 31
685 # define OMAP24XX_DMA_MCBSP1_RX 32
686 # define OMAP24XX_DMA_MCBSP2_TX 33
687 # define OMAP24XX_DMA_MCBSP2_RX 34
688 # define OMAP24XX_DMA_SPI1_TX0 35
689 # define OMAP24XX_DMA_SPI1_RX0 36
690 # define OMAP24XX_DMA_SPI1_TX1 37
691 # define OMAP24XX_DMA_SPI1_RX1 38
692 # define OMAP24XX_DMA_SPI1_TX2 39
693 # define OMAP24XX_DMA_SPI1_RX2 40
694 # define OMAP24XX_DMA_SPI1_TX3 41
695 # define OMAP24XX_DMA_SPI1_RX3 42
696 # define OMAP24XX_DMA_SPI2_TX0 43
697 # define OMAP24XX_DMA_SPI2_RX0 44
698 # define OMAP24XX_DMA_SPI2_TX1 45
699 # define OMAP24XX_DMA_SPI2_RX1 46
701 # define OMAP24XX_DMA_UART1_TX 49
702 # define OMAP24XX_DMA_UART1_RX 50
703 # define OMAP24XX_DMA_UART2_TX 51
704 # define OMAP24XX_DMA_UART2_RX 52
705 # define OMAP24XX_DMA_UART3_TX 53
706 # define OMAP24XX_DMA_UART3_RX 54
707 # define OMAP24XX_DMA_USB_W2FC_TX0 55
708 # define OMAP24XX_DMA_USB_W2FC_RX0 56
709 # define OMAP24XX_DMA_USB_W2FC_TX1 57
710 # define OMAP24XX_DMA_USB_W2FC_RX1 58
711 # define OMAP24XX_DMA_USB_W2FC_TX2 59
712 # define OMAP24XX_DMA_USB_W2FC_RX2 60
713 # define OMAP24XX_DMA_MMC1_TX 61
714 # define OMAP24XX_DMA_MMC1_RX 62
715 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
716 # define OMAP24XX_DMA_EXT_DMAREQ5 64
719 * DMA request numbers for the OMAP3
720 * Note that the numbers have to match the values that are
721 * written to CCRi SYNCHRO_CONTROL bits, i.e. actual line
722 * number plus one! Zero is a reserved value (defined as
723 * NO_DEVICE here). Other missing values are reserved.
725 #define OMAP35XX_DMA_NO_DEVICE 0
727 #define OMAP35XX_DMA_EXT_DMAREQ0 2
728 #define OMAP35XX_DMA_EXT_DMAREQ1 3
729 #define OMAP35XX_DMA_GPMC 4
731 #define OMAP35XX_DMA_DSS_LINETRIGGER 6
732 #define OMAP35XX_DMA_EXT_DMAREQ2 7
734 #define OMAP35XX_DMA_SPI3_TX0 15
735 #define OMAP35XX_DMA_SPI3_RX0 16
736 #define OMAP35XX_DMA_MCBSP3_TX 17
737 #define OMAP35XX_DMA_MCBSP3_RX 18
738 #define OMAP35XX_DMA_MCBSP4_TX 19
739 #define OMAP35XX_DMA_MCBSP4_RX 20
740 #define OMAP35XX_DMA_MCBSP5_TX 21
741 #define OMAP35XX_DMA_MCBSP5_RX 22
742 #define OMAP35XX_DMA_SPI3_TX1 23
743 #define OMAP35XX_DMA_SPI3_RX1 24
744 #define OMAP35XX_DMA_I2C3_TX 25
745 #define OMAP35XX_DMA_I2C3_RX 26
746 #define OMAP35XX_DMA_I2C1_TX 27
747 #define OMAP35XX_DMA_I2C1_RX 28
748 #define OMAP35XX_DMA_I2C2_TX 29
749 #define OMAP35XX_DMA_I2C2_RX 30
750 #define OMAP35XX_DMA_MCBSP1_TX 31
751 #define OMAP35XX_DMA_MCBSP1_RX 32
752 #define OMAP35XX_DMA_MCBSP2_TX 33
753 #define OMAP35XX_DMA_MCBSP2_RX 34
754 #define OMAP35XX_DMA_SPI1_TX0 35
755 #define OMAP35XX_DMA_SPI1_RX0 36
756 #define OMAP35XX_DMA_SPI1_TX1 37
757 #define OMAP35XX_DMA_SPI1_RX1 38
758 #define OMAP35XX_DMA_SPI1_TX2 39
759 #define OMAP35XX_DMA_SPI1_RX2 40
760 #define OMAP35XX_DMA_SPI1_TX3 41
761 #define OMAP35XX_DMA_SPI1_RX4 42
762 #define OMAP35XX_DMA_SPI2_TX0 43
763 #define OMAP35XX_DMA_SPI2_RX0 44
764 #define OMAP35XX_DMA_SPI2_TX1 45
765 #define OMAP35XX_DMA_SPI2_RX1 46
766 #define OMAP35XX_DMA_MMC2_TX 47
767 #define OMAP35XX_DMA_MMC2_RX 48
768 #define OMAP35XX_DMA_UART1_TX 49
769 #define OMAP35XX_DMA_UART1_RX 50
770 #define OMAP35XX_DMA_UART2_TX 51
771 #define OMAP35XX_DMA_UART2_RX 52
772 #define OMAP35XX_DMA_UART3_TX 53
773 #define OMAP35XX_DMA_UART3_RX 54
775 #define OMAP35XX_DMA_MMC1_TX 61
776 #define OMAP35XX_DMA_MMC1_RX 62
777 #define OMAP35XX_DMA_MS 63
778 #define OMAP35XX_DMA_EXT_DMAREQ3 64
780 #define OMAP35XX_DMA_SPI4_TX0 70
781 #define OMAP35XX_DMA_SPI4_RX0 71
782 #define OMAP35XX_DMA_DSS0 72
783 #define OMAP35XX_DMA_DSS1 73
784 #define OMAP35XX_DMA_DSS2 74
785 #define OMAP35XX_DMA_DSS3 75
787 #define OMAP35XX_DMA_MMC3_TX 77
788 #define OMAP35XX_DMA_MMC3_RX 78
792 struct omap_mpu_timer_s;
793 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
794 qemu_irq irq, omap_clk clk);
796 struct omap_gp_timer_s;
797 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
798 qemu_irq irq, omap_clk fclk, omap_clk iclk);
799 void omap_gp_timer_change_clk(struct omap_gp_timer_s *timer);
801 struct omap_watchdog_timer_s;
802 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
803 qemu_irq irq, omap_clk clk);
805 struct omap_32khz_timer_s;
806 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
807 qemu_irq irq, omap_clk clk);
809 void omap_synctimer_init(struct omap_target_agent_s *ta,
810 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
812 struct omap_tipb_bridge_s;
813 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
814 qemu_irq abort_irq, omap_clk clk);
817 struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
818 qemu_irq irq, omap_clk fclk, omap_clk iclk,
819 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
820 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
821 qemu_irq irq, omap_clk fclk, omap_clk iclk,
822 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
823 void omap_uart_reset(struct omap_uart_s *s);
824 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
827 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
828 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
830 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
831 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
832 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
835 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
836 qemu_irq irq, omap_clk clk);
837 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
838 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
841 struct omap_gpif_s *omap2_gpio_init(struct omap_mpu_state_s *mpu,
842 struct omap_target_agent_s *ta,
843 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
844 struct omap_gpif_s *omap3_gpif_init(void);
845 void omap3_gpio_init(struct omap_mpu_state_s *mpu,
846 struct omap_gpif_s *s, struct omap_target_agent_s *ta,
847 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int module_index);
848 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
849 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
851 struct uwire_slave_s {
852 uint16_t (*receive)(void *opaque);
853 void (*send)(void *opaque, uint16_t data);
857 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
858 qemu_irq *irq, qemu_irq dma, omap_clk clk);
859 void omap_uwire_attach(struct omap_uwire_s *s,
860 struct uwire_slave_s *slave, int chipselect);
863 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
864 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
865 void omap_mcspi_attach(struct omap_mcspi_s *s,
866 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
870 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
871 qemu_irq *irq, omap_clk clk);
876 /* The CPU can call this if it is generating the clock signal on the
877 * i2s port. The CODEC can ignore it if it is set up as a clock
878 * master and generates its own clock. */
879 void (*set_rate)(void *opaque, int in, int out);
881 void (*tx_swallow)(void *opaque);
898 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
899 qemu_irq *irq, qemu_irq *dma, omap_clk clk);
900 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
903 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
905 void omap_tap_init(struct omap_target_agent_s *ta,
906 struct omap_mpu_state_s *mpu);
909 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
910 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
913 struct omap_lcd_panel_s;
914 void omap_lcdc_reset(struct omap_lcd_panel_s *s);
915 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
916 struct omap_dma_lcd_channel_s *dma,
917 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
922 void (*write)(void *opaque, int dc, uint16_t value);
923 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
924 uint16_t (*read)(void *opaque, int dc);
926 typedef void (*omap3_lcd_panel_fn_t)(uint8_t *, const uint8_t *, unsigned int);
927 struct omap3_lcd_panel_s {
928 struct omap_dss_s *dss;
930 omap3_lcd_panel_fn_t *line_fn_tab[2];
931 omap3_lcd_panel_fn_t line_fn;
935 void omap_dss_reset(struct omap_dss_s *s);
936 struct omap_dss_s *omap_dss_init(struct omap_mpu_state_s *mpu,
937 struct omap_target_agent_s *ta,
938 qemu_irq irq, qemu_irq drq,
939 omap_clk fck1, omap_clk fck2, omap_clk ck54m,
940 omap_clk ick1, omap_clk ick2);
941 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
942 void omap3_lcd_panel_attach(struct omap_dss_s *s, int cs, struct omap3_lcd_panel_s *lcd_panel);
943 void *omap3_lcd_panel_init(void);
947 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
948 BlockDriverState *bd,
949 qemu_irq irq, qemu_irq dma[], omap_clk clk);
950 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
951 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
952 omap_clk fclk, omap_clk iclk);
953 void omap_mmc_reset(struct omap_mmc_s *s);
954 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
955 void omap_mmc_enable(struct omap_mmc_s *s, int enable);
959 struct omap3_mmc_s *omap3_mmc_init(struct omap_target_agent_s *ta,
960 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
961 omap_clk fclk, omap_clk iclk);
965 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
966 qemu_irq irq, qemu_irq *dma, omap_clk clk);
967 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
968 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
969 struct omap_i2c_s *omap3_i2c_init(struct omap_target_agent_s *ta,
970 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk,
972 void omap_i2c_reset(struct omap_i2c_s *s);
973 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
976 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
977 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
978 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
979 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
980 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
981 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
982 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
983 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
984 # define cpu_is_omap3530(cpu) (cpu->mpu_model == omap3530)
986 # define cpu_is_omap15xx(cpu) \
987 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
988 # define cpu_is_omap16xx(cpu) \
989 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
990 # define cpu_is_omap24xx(cpu) \
991 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
993 # define cpu_class_omap1(cpu) \
994 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
995 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
996 # define cpu_class_omap3(cpu) \
997 (cpu_is_omap3430(cpu) || cpu_is_omap3530(cpu))
999 struct omap_mpu_state_s {
1000 enum omap_mpu_model {
1021 struct omap_dma_port_if_s {
1022 uint32_t (*read[3])(struct omap_mpu_state_s *s,
1023 target_phys_addr_t offset);
1024 void (*write[3])(struct omap_mpu_state_s *s,
1025 target_phys_addr_t offset, uint32_t value);
1026 int (*addr_valid)(struct omap_mpu_state_s *s,
1027 target_phys_addr_t addr);
1028 } port[__omap_dma_port_last];
1030 unsigned long sdram_size;
1031 unsigned long sram_size;
1033 /* MPUI-TIPB peripherals */
1034 struct omap_uart_s *uart[3];
1036 struct omap_gpio_s *gpio;
1038 struct omap_mcbsp_s *mcbsp1;
1039 struct omap_mcbsp_s *mcbsp3;
1041 /* MPU public TIPB peripherals */
1042 struct omap_32khz_timer_s *os_timer;
1044 struct omap_mmc_s *mmc;
1046 struct omap_mpuio_s *mpuio;
1048 struct omap_uwire_s *microwire;
1064 struct omap_i2c_s *i2c[3];
1066 struct omap_rtc_s *rtc;
1068 struct omap_mcbsp_s *mcbsp2;
1070 struct omap_lpg_s *led[2];
1072 /* MPU private TIPB peripherals */
1073 struct omap_intr_handler_s *ih[2];
1075 struct soc_dma_s *dma;
1077 struct omap_mpu_timer_s *timer[3];
1078 struct omap_watchdog_timer_s *wdt;
1080 struct omap_lcd_panel_s *lcd;
1082 uint32_t ulpd_pm_regs[21];
1083 int64_t ulpd_gauge_start;
1085 uint32_t func_mux_ctrl[14];
1086 uint32_t comp_mode_ctrl[1];
1087 uint32_t pull_dwn_ctrl[4];
1088 uint32_t gate_inh_ctrl[1];
1089 uint32_t voltage_ctrl[1];
1090 uint32_t test_dbg_ctrl[1];
1091 uint32_t mod_conf_ctrl[1];
1096 struct omap_tipb_bridge_s *private_tipb;
1097 struct omap_tipb_bridge_s *public_tipb;
1099 uint32_t tcmi_regs[17];
1109 int clocking_scheme;
1111 uint16_t arm_idlect1;
1112 uint16_t arm_idlect2;
1113 uint16_t arm_ewupct;
1114 uint16_t arm_rstct1;
1115 uint16_t arm_rstct2;
1116 uint16_t arm_ckout1;
1118 uint16_t dsp_idlect1;
1119 uint16_t dsp_idlect2;
1120 uint16_t dsp_rstct2;
1123 /* OMAP2-only peripherals */
1124 struct omap_l4_s *l4;
1126 struct omap_gp_timer_s *gptimer[12];
1128 struct omap_synctimer_s {
1131 uint32_t sysconfig; /*OMAP3*/
1134 struct omap_prcm_s *prcm;
1135 struct omap_sdrc_s *sdrc;
1136 struct omap_gpmc_s *gpmc;
1137 struct omap_sysctl_s *sysc;
1139 struct omap_gpif_s *gpif;
1141 struct omap_mcspi_s *mcspi[2];
1143 struct omap_dss_s *dss;
1145 struct omap_eac_s *eac;
1148 struct omap3_prm_s *omap3_prm;
1149 struct omap3_cm_s *omap3_cm;
1150 struct omap3_wdt_s *omap3_mpu_wdt;
1151 struct omap_l3_s *omap3_l3;
1152 struct omap3_scm_s *omap3_scm;
1153 struct omap3_sms_s *omap3_sms;
1154 struct omap3_mmc_s *omap3_mmc[3];
1157 struct omap_target_agent_s {
1158 struct omap_l4_s *bus;
1160 struct omap_l4_region_s *start;
1161 target_phys_addr_t base;
1164 uint32_t control_h; /* OMAP3 */
1169 target_phys_addr_t base;
1171 struct omap_target_agent_s ta[0];
1174 struct omap_l4_region_s {
1175 target_phys_addr_t offset;
1180 struct omap_l4_agent_info_s {
1188 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
1192 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
1196 struct omap_mpu_state_s *omap3530_mpu_init(unsigned long sdram_size,
1198 void omap3_set_mem_type(struct omap_mpu_state_s *s, int bootfrom);
1199 void omap3_set_device_type(struct omap_mpu_state_s *s, int device_type);
1200 int omap3_mmc_boot(struct omap_mpu_state_s *s);
1202 # if TARGET_PHYS_ADDR_BITS == 32
1203 # define OMAP_FMT_plx "0x%08x"
1204 # elif TARGET_PHYS_ADDR_BITS == 64
1205 # define OMAP_FMT_plx "0x%08" PRIx64
1207 # error TARGET_PHYS_ADDR_BITS undefined
1210 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
1211 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
1213 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
1214 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
1216 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
1217 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
1220 void omap_mpu_wakeup(void *opaque, int irq, int req);
1222 # define OMAP_BAD_REG(paddr) \
1223 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
1224 __FUNCTION__, paddr)
1225 # define OMAP_BAD_REGV(paddr, value) \
1226 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx " (value " OMAP_FMT_plx ")\n", \
1227 __FUNCTION__, paddr, value)
1228 # define OMAP_RO_REG(paddr) \
1229 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1230 __FUNCTION__, paddr)
1231 # define OMAP_RO_REGV(paddr, value) \
1232 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx " (value " OMAP_FMT_plx ")\n", \
1233 __FUNCTION__, paddr, value)
1235 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
1236 (Board-specifc tags are not here) */
1237 #define OMAP_TAG_CLOCK 0x4f01
1238 #define OMAP_TAG_MMC 0x4f02
1239 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1240 #define OMAP_TAG_USB 0x4f04
1241 #define OMAP_TAG_LCD 0x4f05
1242 #define OMAP_TAG_GPIO_SWITCH 0x4f06
1243 #define OMAP_TAG_UART 0x4f07
1244 #define OMAP_TAG_FBMEM 0x4f08
1245 #define OMAP_TAG_STI_CONSOLE 0x4f09
1246 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1247 #define OMAP_TAG_PARTITION 0x4f0b
1248 #define OMAP_TAG_TEA5761 0x4f10
1249 #define OMAP_TAG_TMP105 0x4f11
1250 #define OMAP_TAG_BOOT_REASON 0x4f80
1251 #define OMAP_TAG_FLASH_PART_STR 0x4f81
1252 #define OMAP_TAG_VERSION_STR 0x4f82
1255 OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1256 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1257 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1260 #define OMAP_GPIOSW_INVERTED 0x0001
1261 #define OMAP_GPIOSW_OUTPUT 0x0002
1263 # define TCMI_VERBOSE 1
1264 //# define MEM_VERBOSE 1
1266 # ifdef TCMI_VERBOSE
1267 # define OMAP_8B_REG(paddr) \
1268 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1269 __FUNCTION__, paddr)
1270 # define OMAP_16B_REG(paddr) \
1271 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1272 __FUNCTION__, paddr)
1273 # define OMAP_32B_REG(paddr) \
1274 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1275 __FUNCTION__, paddr)
1277 # define OMAP_8B_REG(paddr)
1278 # define OMAP_16B_REG(paddr)
1279 # define OMAP_32B_REG(paddr)
1282 # define OMAP_MPUI_REG_MASK 0x000007ff
1286 CPUReadMemoryFunc **mem_read;
1287 CPUWriteMemoryFunc **mem_write;
1292 static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1294 struct io_fn *s = opaque;
1298 ret = s->mem_read[0](s->opaque, addr);
1301 fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1304 static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1306 struct io_fn *s = opaque;
1310 ret = s->mem_read[1](s->opaque, addr);
1313 fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1316 static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1318 struct io_fn *s = opaque;
1322 ret = s->mem_read[2](s->opaque, addr);
1325 fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1328 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1330 struct io_fn *s = opaque;
1333 fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1335 s->mem_write[0](s->opaque, addr, value);
1338 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1340 struct io_fn *s = opaque;
1343 fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1345 s->mem_write[1](s->opaque, addr, value);
1348 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1350 struct io_fn *s = opaque;
1353 fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1355 s->mem_write[2](s->opaque, addr, value);
1359 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
1360 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
1362 inline static int debug_register_io_memory(int io_index,
1363 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
1366 struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1368 s->mem_read = mem_read;
1369 s->mem_write = mem_write;
1372 return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
1374 # define cpu_register_io_memory debug_register_io_memory
1377 /* Define when we want to reduce the number of IO regions registered. */
1378 /*# define L4_MUX_HACK*/
1381 # undef l4_register_io_memory
1382 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
1383 CPUWriteMemoryFunc **mem_write, void *opaque);
1386 #endif /* hw_omap_h */