2 * QEMU NE2000 emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* debug NE2000 card */
27 //#define DEBUG_NE2000
29 #define MAX_ETH_FRAME_SIZE 1514
31 #define E8390_CMD 0x00 /* The command register (for all pages) */
32 /* Page 0 register offsets. */
33 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
34 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
35 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
36 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
37 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
38 #define EN0_TSR 0x04 /* Transmit status reg RD */
39 #define EN0_TPSR 0x04 /* Transmit starting page WR */
40 #define EN0_NCR 0x05 /* Number of collision reg RD */
41 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
42 #define EN0_FIFO 0x06 /* FIFO RD */
43 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
44 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
45 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
46 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
47 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
48 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
49 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
50 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
51 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
52 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
53 #define EN0_RSR 0x0c /* rx status reg RD */
54 #define EN0_RXCR 0x0c /* RX configuration reg WR */
55 #define EN0_TXCR 0x0d /* TX configuration reg WR */
56 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
57 #define EN0_DCFG 0x0e /* Data configuration reg WR */
58 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
59 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
60 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
63 #define EN1_CURPAG 0x17
66 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
67 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
69 #define EN3_CONFIG0 0x33
70 #define EN3_CONFIG1 0x34
71 #define EN3_CONFIG2 0x35
72 #define EN3_CONFIG3 0x36
74 /* Register accessed at EN_CMD, the 8390 base addr. */
75 #define E8390_STOP 0x01 /* Stop and reset the chip */
76 #define E8390_START 0x02 /* Start the chip, clear reset */
77 #define E8390_TRANS 0x04 /* Transmit a frame */
78 #define E8390_RREAD 0x08 /* Remote read */
79 #define E8390_RWRITE 0x10 /* Remote write */
80 #define E8390_NODMA 0x20 /* Remote DMA */
81 #define E8390_PAGE0 0x00 /* Select page chip registers */
82 #define E8390_PAGE1 0x40 /* using the two high-order bits */
83 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
85 /* Bits in EN0_ISR - Interrupt status register */
86 #define ENISR_RX 0x01 /* Receiver, no error */
87 #define ENISR_TX 0x02 /* Transmitter, no error */
88 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
89 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
90 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
91 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
92 #define ENISR_RDC 0x40 /* remote dma complete */
93 #define ENISR_RESET 0x80 /* Reset completed */
94 #define ENISR_ALL 0x3f /* Interrupts we will enable */
96 /* Bits in received packet status byte and EN0_RSR*/
97 #define ENRSR_RXOK 0x01 /* Received a good packet */
98 #define ENRSR_CRC 0x02 /* CRC error */
99 #define ENRSR_FAE 0x04 /* frame alignment error */
100 #define ENRSR_FO 0x08 /* FIFO overrun */
101 #define ENRSR_MPA 0x10 /* missed pkt */
102 #define ENRSR_PHY 0x20 /* physical/multicast address */
103 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
104 #define ENRSR_DEF 0x80 /* deferring */
106 /* Transmitted packet status, EN0_TSR. */
107 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
108 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
109 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
110 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
111 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
112 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
113 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
114 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
116 #define NE2000_PMEM_SIZE (32*1024)
117 #define NE2000_PMEM_START (16*1024)
118 #define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
119 #define NE2000_MEM_SIZE NE2000_PMEM_END
121 typedef struct NE2000State {
136 uint8_t phys[6]; /* mac address */
138 uint8_t mult[8]; /* multicast mask array */
143 uint8_t mem[NE2000_MEM_SIZE];
146 static void ne2000_reset(NE2000State *s)
150 s->isr = ENISR_RESET;
151 memcpy(s->mem, s->macaddr, 6);
155 /* duplicate prom data */
156 for(i = 15;i >= 0; i--) {
157 s->mem[2 * i] = s->mem[i];
158 s->mem[2 * i + 1] = s->mem[i];
162 static void ne2000_update_irq(NE2000State *s)
165 isr = (s->isr & s->imr) & 0x7f;
166 #if defined(DEBUG_NE2000)
167 printf("NE2000: Set IRQ line %d to %d (%02x %02x)\n",
168 s->irq, isr ? 1 : 0, s->isr, s->imr);
172 pci_set_irq(s->pci_dev, 0, (isr != 0));
175 pic_set_irq(s->irq, (isr != 0));
179 #define POLYNOMIAL 0x04c11db6
183 static int compute_mcast_idx(const uint8_t *ep)
190 for (i = 0; i < 6; i++) {
192 for (j = 0; j < 8; j++) {
193 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
197 crc = ((crc ^ POLYNOMIAL) | carry);
203 /* return the max buffer size if the NE2000 can receive more data */
204 static int ne2000_can_receive(void *opaque)
206 NE2000State *s = opaque;
207 int avail, index, boundary;
209 if (s->cmd & E8390_STOP)
211 index = s->curpag << 8;
212 boundary = s->boundary << 8;
213 if (index < boundary)
214 avail = boundary - index;
216 avail = (s->stop - s->start) - (index - boundary);
217 if (avail < (MAX_ETH_FRAME_SIZE + 4))
219 return MAX_ETH_FRAME_SIZE;
222 #define MIN_BUF_SIZE 60
224 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
226 NE2000State *s = opaque;
228 int total_len, next, avail, len, index, mcast_idx;
230 static const uint8_t broadcast_macaddr[6] =
231 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
233 #if defined(DEBUG_NE2000)
234 printf("NE2000: received len=%d\n", size);
237 if (!ne2000_can_receive(s))
240 /* XXX: check this */
241 if (s->rxcr & 0x10) {
242 /* promiscuous: receive all */
244 if (!memcmp(buf, broadcast_macaddr, 6)) {
245 /* broadcast address */
246 if (!(s->rxcr & 0x04))
248 } else if (buf[0] & 0x01) {
250 if (!(s->rxcr & 0x08))
252 mcast_idx = compute_mcast_idx(buf);
253 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
255 } else if (s->mem[0] == buf[0] &&
256 s->mem[2] == buf[1] &&
257 s->mem[4] == buf[2] &&
258 s->mem[6] == buf[3] &&
259 s->mem[8] == buf[4] &&
260 s->mem[10] == buf[5]) {
268 /* if too small buffer, then expand it */
269 if (size < MIN_BUF_SIZE) {
270 memcpy(buf1, buf, size);
271 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
276 index = s->curpag << 8;
277 /* 4 bytes for header */
278 total_len = size + 4;
279 /* address for next packet (4 bytes for CRC) */
280 next = index + ((total_len + 4 + 255) & ~0xff);
282 next -= (s->stop - s->start);
283 /* prepare packet header */
285 s->rsr = ENRSR_RXOK; /* receive status */
286 /* XXX: check this */
292 p[3] = total_len >> 8;
295 /* write packet data */
297 avail = s->stop - index;
301 memcpy(s->mem + index, buf, len);
304 if (index == s->stop)
308 s->curpag = next >> 8;
310 /* now we can signal we have receive something */
312 ne2000_update_irq(s);
315 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
317 NE2000State *s = opaque;
318 int offset, page, index;
322 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
324 if (addr == E8390_CMD) {
325 /* control register */
327 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
328 s->isr &= ~ENISR_RESET;
329 /* test specific case: zero length transfert */
330 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
333 ne2000_update_irq(s);
335 if (val & E8390_TRANS) {
336 index = (s->tpsr << 8);
337 /* XXX: next 2 lines are a hack to make netware 3.11 work */
338 if (index >= NE2000_PMEM_END)
339 index -= NE2000_PMEM_SIZE;
340 /* fail safe: check range on the transmitted length */
341 if (index + s->tcnt <= NE2000_PMEM_END) {
342 qemu_send_packet(s->vc, s->mem + index, s->tcnt);
344 /* signal end of transfert */
347 s->cmd &= ~E8390_TRANS;
348 ne2000_update_irq(s);
353 offset = addr | (page << 4);
366 ne2000_update_irq(s);
372 s->tcnt = (s->tcnt & 0xff00) | val;
375 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
378 s->rsar = (s->rsar & 0xff00) | val;
381 s->rsar = (s->rsar & 0x00ff) | (val << 8);
384 s->rcnt = (s->rcnt & 0xff00) | val;
387 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
396 s->isr &= ~(val & 0x7f);
397 ne2000_update_irq(s);
399 case EN1_PHYS ... EN1_PHYS + 5:
400 s->phys[offset - EN1_PHYS] = val;
405 case EN1_MULT ... EN1_MULT + 7:
406 s->mult[offset - EN1_MULT] = val;
412 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
414 NE2000State *s = opaque;
415 int offset, page, ret;
418 if (addr == E8390_CMD) {
422 offset = addr | (page << 4);
434 ret = s->rsar & 0x00ff;
439 case EN1_PHYS ... EN1_PHYS + 5:
440 ret = s->phys[offset - EN1_PHYS];
445 case EN1_MULT ... EN1_MULT + 7:
446 ret = s->mult[offset - EN1_MULT];
464 ret = 0; /* 10baseT media */
467 ret = 0x40; /* 10baseT active */
470 ret = 0x40; /* Full duplex */
478 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
483 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
487 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
492 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
495 addr &= ~1; /* XXX: check exact behaviour if not even */
497 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
498 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
502 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
505 addr &= ~1; /* XXX: check exact behaviour if not even */
507 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
508 cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
512 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
515 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
522 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
524 addr &= ~1; /* XXX: check exact behaviour if not even */
526 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
527 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
533 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
535 addr &= ~1; /* XXX: check exact behaviour if not even */
537 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
538 return le32_to_cpupu((uint32_t *)(s->mem + addr));
544 static inline void ne2000_dma_update(NE2000State *s, int len)
548 /* XXX: check what to do if rsar > stop */
549 if (s->rsar == s->stop)
552 if (s->rcnt <= len) {
554 /* signal end of transfert */
556 ne2000_update_irq(s);
562 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
564 NE2000State *s = opaque;
567 printf("NE2000: asic write val=0x%04x\n", val);
571 if (s->dcfg & 0x01) {
573 ne2000_mem_writew(s, s->rsar, val);
574 ne2000_dma_update(s, 2);
577 ne2000_mem_writeb(s, s->rsar, val);
578 ne2000_dma_update(s, 1);
582 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
584 NE2000State *s = opaque;
587 if (s->dcfg & 0x01) {
589 ret = ne2000_mem_readw(s, s->rsar);
590 ne2000_dma_update(s, 2);
593 ret = ne2000_mem_readb(s, s->rsar);
594 ne2000_dma_update(s, 1);
597 printf("NE2000: asic read val=0x%04x\n", ret);
602 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
604 NE2000State *s = opaque;
607 printf("NE2000: asic writel val=0x%04x\n", val);
612 ne2000_mem_writel(s, s->rsar, val);
613 ne2000_dma_update(s, 4);
616 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
618 NE2000State *s = opaque;
622 ret = ne2000_mem_readl(s, s->rsar);
623 ne2000_dma_update(s, 4);
625 printf("NE2000: asic readl val=0x%04x\n", ret);
630 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
632 /* nothing to do (end of reset pulse) */
635 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
637 NE2000State *s = opaque;
642 static void ne2000_save(QEMUFile* f,void* opaque)
644 NE2000State* s=(NE2000State*)opaque;
646 qemu_put_8s(f, &s->rxcr);
648 qemu_put_8s(f, &s->cmd);
649 qemu_put_be32s(f, &s->start);
650 qemu_put_be32s(f, &s->stop);
651 qemu_put_8s(f, &s->boundary);
652 qemu_put_8s(f, &s->tsr);
653 qemu_put_8s(f, &s->tpsr);
654 qemu_put_be16s(f, &s->tcnt);
655 qemu_put_be16s(f, &s->rcnt);
656 qemu_put_be32s(f, &s->rsar);
657 qemu_put_8s(f, &s->rsr);
658 qemu_put_8s(f, &s->isr);
659 qemu_put_8s(f, &s->dcfg);
660 qemu_put_8s(f, &s->imr);
661 qemu_put_buffer(f, s->phys, 6);
662 qemu_put_8s(f, &s->curpag);
663 qemu_put_buffer(f, s->mult, 8);
664 qemu_put_be32s(f, &s->irq);
665 qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE);
668 static int ne2000_load(QEMUFile* f,void* opaque,int version_id)
670 NE2000State* s=(NE2000State*)opaque;
672 if (version_id == 2) {
673 qemu_get_8s(f, &s->rxcr);
674 } else if (version_id == 1) {
680 qemu_get_8s(f, &s->cmd);
681 qemu_get_be32s(f, &s->start);
682 qemu_get_be32s(f, &s->stop);
683 qemu_get_8s(f, &s->boundary);
684 qemu_get_8s(f, &s->tsr);
685 qemu_get_8s(f, &s->tpsr);
686 qemu_get_be16s(f, &s->tcnt);
687 qemu_get_be16s(f, &s->rcnt);
688 qemu_get_be32s(f, &s->rsar);
689 qemu_get_8s(f, &s->rsr);
690 qemu_get_8s(f, &s->isr);
691 qemu_get_8s(f, &s->dcfg);
692 qemu_get_8s(f, &s->imr);
693 qemu_get_buffer(f, s->phys, 6);
694 qemu_get_8s(f, &s->curpag);
695 qemu_get_buffer(f, s->mult, 8);
696 qemu_get_be32s(f, &s->irq);
697 qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE);
702 void isa_ne2000_init(int base, int irq, NICInfo *nd)
706 s = qemu_mallocz(sizeof(NE2000State));
710 register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
711 register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
713 register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
714 register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
715 register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
716 register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
718 register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
719 register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
721 memcpy(s->macaddr, nd->macaddr, 6);
725 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s);
727 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
728 "ne2000 macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
736 register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
739 /***********************************************************/
740 /* PCI NE2000 definitions */
742 typedef struct PCINE2000State {
747 static void ne2000_map(PCIDevice *pci_dev, int region_num,
748 uint32_t addr, uint32_t size, int type)
750 PCINE2000State *d = (PCINE2000State *)pci_dev;
751 NE2000State *s = &d->ne2000;
753 register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
754 register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
756 register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
757 register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
758 register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
759 register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
760 register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
761 register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
763 register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
764 register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
767 void pci_ne2000_init(PCIBus *bus, NICInfo *nd)
773 d = (PCINE2000State *)pci_register_device(bus,
774 "NE2000", sizeof(PCINE2000State),
777 pci_conf = d->dev.config;
778 pci_conf[0x00] = 0xec; // Realtek 8029
779 pci_conf[0x01] = 0x10;
780 pci_conf[0x02] = 0x29;
781 pci_conf[0x03] = 0x80;
782 pci_conf[0x0a] = 0x00; // ethernet network controller
783 pci_conf[0x0b] = 0x02;
784 pci_conf[0x0e] = 0x00; // header_type
785 pci_conf[0x3d] = 1; // interrupt pin 0
787 pci_register_io_region(&d->dev, 0, 0x100,
788 PCI_ADDRESS_SPACE_IO, ne2000_map);
790 s->irq = 16; // PCI interrupt
791 s->pci_dev = (PCIDevice *)d;
792 memcpy(s->macaddr, nd->macaddr, 6);
794 s->vc = qemu_new_vlan_client(nd->vlan, ne2000_receive, s);
796 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
797 "ne2000 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
805 /* XXX: instance number ? */
806 register_savevm("ne2000", 0, 2, ne2000_save, ne2000_load, s);
807 register_savevm("ne2000_pci", 0, 1, generic_pci_save, generic_pci_load,