2 * ARM MPCore internal peripheral emulation.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
12 #define MPCORE_PRIV_BASE 0x10100000
14 /* ??? The MPCore TRM says the on-chip controller has 224 external IRQ lines
15 (+ 32 internal). However my test chip only exposes/reports 32.
16 More importantly Linux falls over if more than 32 are present! */
20 gic_get_current_cpu(void)
22 return cpu_single_env->cpu_index;
27 /* MPCore private memory region. */
37 struct mpcore_priv_state *mpcore;
38 int id; /* Encodes both timer/watchdog and CPU. */
41 typedef struct mpcore_priv_state {
44 mpcore_timer_state timer[8];
49 static inline void mpcore_timer_update_irq(mpcore_timer_state *s)
51 if (s->status & ~s->old_status) {
52 gic_set_pending_private(s->mpcore->gic, s->id >> 1, 29 + (s->id & 1));
54 s->old_status = s->status;
57 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
58 static inline uint32_t mpcore_timer_scale(mpcore_timer_state *s)
60 return (((s->control >> 8) & 0xff) + 1) * 10;
63 static void mpcore_timer_reload(mpcore_timer_state *s, int restart)
68 s->tick = qemu_get_clock(vm_clock);
69 s->tick += (int64_t)s->count * mpcore_timer_scale(s);
70 qemu_mod_timer(s->timer, s->tick);
73 static void mpcore_timer_tick(void *opaque)
75 mpcore_timer_state *s = (mpcore_timer_state *)opaque;
79 mpcore_timer_reload(s, 0);
83 mpcore_timer_update_irq(s);
86 static uint32_t mpcore_timer_read(mpcore_timer_state *s, int offset)
93 case 4: /* Counter. */
94 if (((s->control & 1) == 0) || (s->count == 0))
96 /* Slow and ugly, but hopefully won't happen too often. */
97 val = s->tick - qemu_get_clock(vm_clock);
98 val /= mpcore_timer_scale(s);
102 case 8: /* Control. */
104 case 12: /* Interrupt status. */
109 static void mpcore_timer_write(mpcore_timer_state *s, int offset,
117 case 4: /* Counter. */
118 if ((s->control & 1) && s->count) {
119 /* Cancel the previous timer. */
120 qemu_del_timer(s->timer);
123 if (s->control & 1) {
124 mpcore_timer_reload(s, 1);
127 case 8: /* Control. */
130 if (((old & 1) == 0) && (value & 1)) {
131 if (s->count == 0 && (s->control & 2))
133 mpcore_timer_reload(s, 1);
136 case 12: /* Interrupt status. */
138 mpcore_timer_update_irq(s);
143 static void mpcore_timer_init(mpcore_priv_state *mpcore,
144 mpcore_timer_state *s, int id)
148 s->timer = qemu_new_timer(vm_clock, mpcore_timer_tick, s);
152 /* Per-CPU private memory mapped IO. */
154 static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
156 mpcore_priv_state *s = (mpcore_priv_state *)opaque;
159 if (offset < 0x100) {
162 case 0x00: /* Control. */
163 return s->scu_control;
164 case 0x04: /* Configuration. */
166 case 0x08: /* CPU status. */
168 case 0x0c: /* Invalidate all. */
173 } else if (offset < 0x600) {
174 /* Interrupt controller. */
175 if (offset < 0x200) {
176 id = gic_get_current_cpu();
178 id = (offset - 0x200) >> 8;
180 return gic_cpu_read(s->gic, id, offset & 0xff);
181 } else if (offset < 0xb00) {
183 if (offset < 0x700) {
184 id = gic_get_current_cpu();
186 id = (offset - 0x700) >> 8;
191 return mpcore_timer_read(&s->timer[id], offset & 0xf);
194 cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
199 static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
202 mpcore_priv_state *s = (mpcore_priv_state *)opaque;
205 if (offset < 0x100) {
208 case 0: /* Control register. */
209 s->scu_control = value & 1;
211 case 0x0c: /* Invalidate all. */
212 /* This is a no-op as cache is not emulated. */
217 } else if (offset < 0x600) {
218 /* Interrupt controller. */
219 if (offset < 0x200) {
220 id = gic_get_current_cpu();
222 id = (offset - 0x200) >> 8;
224 gic_cpu_write(s->gic, id, offset & 0xff, value);
225 } else if (offset < 0xb00) {
227 if (offset < 0x700) {
228 id = gic_get_current_cpu();
230 id = (offset - 0x700) >> 8;
235 mpcore_timer_write(&s->timer[id], offset & 0xf, value);
240 cpu_abort(cpu_single_env, "mpcore_priv_read: Bad offset %x\n",
244 static CPUReadMemoryFunc *mpcore_priv_readfn[] = {
250 static CPUWriteMemoryFunc *mpcore_priv_writefn[] = {
257 static qemu_irq *mpcore_priv_init(uint32_t base, qemu_irq *pic_irq)
259 mpcore_priv_state *s;
263 s = (mpcore_priv_state *)qemu_mallocz(sizeof(mpcore_priv_state));
266 s->gic = gic_init(base, pic_irq);
269 iomemtype = cpu_register_io_memory(0, mpcore_priv_readfn,
270 mpcore_priv_writefn, s);
271 cpu_register_physical_memory(base, 0x00001000, iomemtype);
272 for (i = 0; i < 8; i++) {
273 mpcore_timer_init(s, &s->timer[i], i);
278 /* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
279 controllers. The output of these, plus some of the raw input lines
280 are fed into a single SMP-aware interrupt controller on the CPU. */
286 /* Map baseboard IRQs onto CPU IRQ lines. */
287 static const int mpcore_irq_map[32] = {
288 -1, -1, -1, -1, 1, 2, -1, -1,
289 -1, -1, 6, -1, 4, 5, -1, -1,
290 -1, 14, 15, 0, 7, 8, -1, -1,
291 -1, -1, -1, -1, 9, 3, -1, -1,
294 static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
296 mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
299 for (i = 0; i < 4; i++) {
300 qemu_set_irq(s->rvic[i][irq], level);
303 irq = mpcore_irq_map[irq];
305 qemu_set_irq(s->cpuic[irq], level);
310 qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq)
312 mpcore_rirq_state *s;
315 /* ??? IRQ routing is hardcoded to "normal" mode. */
316 s = qemu_mallocz(sizeof(mpcore_rirq_state));
317 s->cpuic = mpcore_priv_init(MPCORE_PRIV_BASE, cpu_irq);
318 for (n = 0; n < 4; n++) {
319 s->rvic[n] = realview_gic_init(0x10040000 + n * 0x10000,
322 return qemu_allocate_irqs(mpcore_rirq_set_irq, s, 64);