6 //#define DEBUG_MIPSNET_SEND
7 //#define DEBUG_MIPSNET_RECEIVE
8 //#define DEBUG_MIPSNET_DATA
9 //#define DEBUG_MIPSNET_IRQ
11 /* MIPSnet register offsets */
13 #define MIPSNET_DEV_ID 0x00
14 # define MIPSNET_DEV_ID_STRING "MIPSNET0"
15 #define MIPSNET_BUSY 0x08
16 #define MIPSNET_RX_DATA_COUNT 0x0c
17 #define MIPSNET_TX_DATA_COUNT 0x10
18 #define MIPSNET_INT_CTL 0x14
19 # define MIPSNET_INTCTL_TXDONE 0x00000001
20 # define MIPSNET_INTCTL_RXDONE 0x00000002
21 # define MIPSNET_INTCTL_TESTBIT 0x80000000
22 #define MIPSNET_INTERRUPT_INFO 0x18
23 #define MIPSNET_RX_DATA_BUFFER 0x1c
24 #define MIPSNET_TX_DATA_BUFFER 0x20
26 #define MAX_ETH_FRAME_SIZE 1514
28 typedef struct MIPSnetState {
35 uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
36 uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
42 static void mipsnet_reset(MIPSnetState *s)
50 memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
51 memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
54 static void mipsnet_update_irq(MIPSnetState *s)
56 int isr = !!s->intctl;
57 #ifdef DEBUG_MIPSNET_IRQ
58 printf("mipsnet: Set IRQ to %d (%02x)\n", isr, s->intctl);
60 qemu_set_irq(s->irq, isr);
63 static int mipsnet_buffer_full(MIPSnetState *s)
65 if (s->rx_count >= MAX_ETH_FRAME_SIZE)
70 static int mipsnet_can_receive(void *opaque)
72 MIPSnetState *s = opaque;
76 return !mipsnet_buffer_full(s);
79 static void mipsnet_receive(void *opaque, const uint8_t *buf, int size)
81 MIPSnetState *s = opaque;
83 #ifdef DEBUG_MIPSNET_RECEIVE
84 printf("mipsnet: receiving len=%d\n", size);
86 if (!mipsnet_can_receive(opaque))
91 /* Just accept everything. */
93 /* Write packet data. */
94 memcpy(s->rx_buffer, buf, size);
99 /* Now we can signal we have received something. */
100 s->intctl |= MIPSNET_INTCTL_RXDONE;
101 mipsnet_update_irq(s);
104 static uint32_t mipsnet_ioport_read(void *opaque, uint32_t addr)
106 MIPSnetState *s = opaque;
108 const char *devid = MIPSNET_DEV_ID_STRING;
113 ret = *((uint32_t *)&devid);
115 case MIPSNET_DEV_ID + 4:
116 ret = *((uint32_t *)(&devid + 4));
121 case MIPSNET_RX_DATA_COUNT:
124 case MIPSNET_TX_DATA_COUNT:
127 case MIPSNET_INT_CTL:
129 s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
131 case MIPSNET_INTERRUPT_INFO:
132 /* XXX: This seems to be a per-VPE interrupt number. */
135 case MIPSNET_RX_DATA_BUFFER:
138 ret = s->rx_buffer[s->rx_read++];
142 case MIPSNET_TX_DATA_BUFFER:
146 #ifdef DEBUG_MIPSNET_DATA
147 printf("mipsnet: read addr=0x%02x val=0x%02x\n", addr, ret);
152 static void mipsnet_ioport_write(void *opaque, uint32_t addr, uint32_t val)
154 MIPSnetState *s = opaque;
157 #ifdef DEBUG_MIPSNET_DATA
158 printf("mipsnet: write addr=0x%02x val=0x%02x\n", addr, val);
161 case MIPSNET_TX_DATA_COUNT:
162 s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
165 case MIPSNET_INT_CTL:
166 if (val & MIPSNET_INTCTL_TXDONE) {
167 s->intctl &= ~MIPSNET_INTCTL_TXDONE;
168 } else if (val & MIPSNET_INTCTL_RXDONE) {
169 s->intctl &= ~MIPSNET_INTCTL_RXDONE;
170 } else if (val & MIPSNET_INTCTL_TESTBIT) {
172 s->intctl |= MIPSNET_INTCTL_TESTBIT;
174 /* ACK testbit interrupt, flag was cleared on read. */
176 s->busy = !!s->intctl;
177 mipsnet_update_irq(s);
179 case MIPSNET_TX_DATA_BUFFER:
180 s->tx_buffer[s->tx_written++] = val;
181 if (s->tx_written == s->tx_count) {
183 #ifdef DEBUG_MIPSNET_SEND
184 printf("mipsnet: sending len=%d\n", s->tx_count);
186 qemu_send_packet(s->vc, s->tx_buffer, s->tx_count);
187 s->tx_count = s->tx_written = 0;
188 s->intctl |= MIPSNET_INTCTL_TXDONE;
190 mipsnet_update_irq(s);
193 /* Read-only registers */
196 case MIPSNET_RX_DATA_COUNT:
197 case MIPSNET_INTERRUPT_INFO:
198 case MIPSNET_RX_DATA_BUFFER:
204 static void mipsnet_save(QEMUFile *f, void *opaque)
206 MIPSnetState *s = opaque;
208 qemu_put_be32s(f, &s->busy);
209 qemu_put_be32s(f, &s->rx_count);
210 qemu_put_be32s(f, &s->rx_read);
211 qemu_put_be32s(f, &s->tx_count);
212 qemu_put_be32s(f, &s->tx_written);
213 qemu_put_be32s(f, &s->intctl);
214 qemu_put_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
215 qemu_put_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
218 static int mipsnet_load(QEMUFile *f, void *opaque, int version_id)
220 MIPSnetState *s = opaque;
225 qemu_get_be32s(f, &s->busy);
226 qemu_get_be32s(f, &s->rx_count);
227 qemu_get_be32s(f, &s->rx_read);
228 qemu_get_be32s(f, &s->tx_count);
229 qemu_get_be32s(f, &s->tx_written);
230 qemu_get_be32s(f, &s->intctl);
231 qemu_get_buffer(f, s->rx_buffer, MAX_ETH_FRAME_SIZE);
232 qemu_get_buffer(f, s->tx_buffer, MAX_ETH_FRAME_SIZE);
237 void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
241 s = qemu_mallocz(sizeof(MIPSnetState));
245 register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
246 register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
247 register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
248 register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
249 register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
250 register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
254 if (nd && nd->vlan) {
255 s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
256 mipsnet_can_receive, s);
261 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
262 "mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
271 register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);