2 * QEMU MC146818 RTC emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #define RTC_SECONDS_ALARM 1
31 #define RTC_MINUTES_ALARM 3
33 #define RTC_HOURS_ALARM 5
34 #define RTC_ALARM_DONT_CARE 0xC0
36 #define RTC_DAY_OF_WEEK 6
37 #define RTC_DAY_OF_MONTH 7
46 #define REG_A_UIP 0x80
48 #define REG_B_SET 0x80
49 #define REG_B_PIE 0x40
50 #define REG_B_AIE 0x20
51 #define REG_B_UIE 0x10
54 uint8_t cmos_data[128];
58 target_phys_addr_t base;
61 QEMUTimer *periodic_timer;
62 int64_t next_periodic_time;
64 int64_t next_second_time;
65 QEMUTimer *second_timer;
66 QEMUTimer *second_timer2;
69 static void rtc_set_time(RTCState *s);
70 static void rtc_copy_date(RTCState *s);
72 static void rtc_timer_update(RTCState *s, int64_t current_time)
74 int period_code, period;
75 int64_t cur_clock, next_irq_clock;
77 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
78 if (period_code != 0 &&
79 (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
82 /* period in 32 Khz cycles */
83 period = 1 << (period_code - 1);
84 /* compute 32 khz clock */
85 cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
86 next_irq_clock = (cur_clock & ~(period - 1)) + period;
87 s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
88 qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
90 qemu_del_timer(s->periodic_timer);
94 static void rtc_periodic_timer(void *opaque)
98 rtc_timer_update(s, s->next_periodic_time);
99 s->cmos_data[RTC_REG_C] |= 0xc0;
100 qemu_irq_raise(s->irq);
103 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
105 RTCState *s = opaque;
107 if ((addr & 1) == 0) {
108 s->cmos_index = data & 0x7f;
111 printf("cmos: write index=0x%02x val=0x%02x\n",
112 s->cmos_index, data);
114 switch(s->cmos_index) {
115 case RTC_SECONDS_ALARM:
116 case RTC_MINUTES_ALARM:
117 case RTC_HOURS_ALARM:
118 /* XXX: not supported */
119 s->cmos_data[s->cmos_index] = data;
124 case RTC_DAY_OF_WEEK:
125 case RTC_DAY_OF_MONTH:
128 s->cmos_data[s->cmos_index] = data;
129 /* if in set mode, do not update the time */
130 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
135 /* UIP bit is read only */
136 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
137 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
138 rtc_timer_update(s, qemu_get_clock(vm_clock));
141 if (data & REG_B_SET) {
142 /* set mode: reset UIP mode */
143 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
146 /* if disabling set mode, update the time */
147 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
151 s->cmos_data[RTC_REG_B] = data;
152 rtc_timer_update(s, qemu_get_clock(vm_clock));
156 /* cannot write to them */
159 s->cmos_data[s->cmos_index] = data;
165 static inline int to_bcd(RTCState *s, int a)
167 if (s->cmos_data[RTC_REG_B] & 0x04) {
170 return ((a / 10) << 4) | (a % 10);
174 static inline int from_bcd(RTCState *s, int a)
176 if (s->cmos_data[RTC_REG_B] & 0x04) {
179 return ((a >> 4) * 10) + (a & 0x0f);
183 static void rtc_set_time(RTCState *s)
185 struct tm *tm = &s->current_tm;
187 tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
188 tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
189 tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
190 if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
191 (s->cmos_data[RTC_HOURS] & 0x80)) {
194 tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
195 tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
196 tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
197 tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
200 static void rtc_copy_date(RTCState *s)
202 const struct tm *tm = &s->current_tm;
204 s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
205 s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
206 if (s->cmos_data[RTC_REG_B] & 0x02) {
208 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
211 s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
212 if (tm->tm_hour >= 12)
213 s->cmos_data[RTC_HOURS] |= 0x80;
215 s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
216 s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
217 s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
218 s->cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
221 /* month is between 0 and 11. */
222 static int get_days_in_month(int month, int year)
224 static const int days_tab[12] = {
225 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
228 if ((unsigned )month >= 12)
232 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
238 /* update 'tm' to the next second */
239 static void rtc_next_second(struct tm *tm)
244 if ((unsigned)tm->tm_sec >= 60) {
247 if ((unsigned)tm->tm_min >= 60) {
250 if ((unsigned)tm->tm_hour >= 24) {
254 if ((unsigned)tm->tm_wday >= 7)
256 days_in_month = get_days_in_month(tm->tm_mon,
259 if (tm->tm_mday < 1) {
261 } else if (tm->tm_mday > days_in_month) {
264 if (tm->tm_mon >= 12) {
275 static void rtc_update_second(void *opaque)
277 RTCState *s = opaque;
280 /* if the oscillator is not in normal operation, we do not update */
281 if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
282 s->next_second_time += ticks_per_sec;
283 qemu_mod_timer(s->second_timer, s->next_second_time);
285 rtc_next_second(&s->current_tm);
287 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
288 /* update in progress bit */
289 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
291 /* should be 244 us = 8 / 32768 seconds, but currently the
292 timers do not have the necessary resolution. */
293 delay = (ticks_per_sec * 1) / 100;
296 qemu_mod_timer(s->second_timer2,
297 s->next_second_time + delay);
301 static void rtc_update_second2(void *opaque)
303 RTCState *s = opaque;
305 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
310 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
311 if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
312 s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
313 ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
314 s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
315 ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
316 s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
318 s->cmos_data[RTC_REG_C] |= 0xa0;
319 qemu_irq_raise(s->irq);
323 /* update ended interrupt */
324 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
325 s->cmos_data[RTC_REG_C] |= 0x90;
326 qemu_irq_raise(s->irq);
329 /* clear update in progress bit */
330 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
332 s->next_second_time += ticks_per_sec;
333 qemu_mod_timer(s->second_timer, s->next_second_time);
336 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
338 RTCState *s = opaque;
340 if ((addr & 1) == 0) {
343 switch(s->cmos_index) {
347 case RTC_DAY_OF_WEEK:
348 case RTC_DAY_OF_MONTH:
351 ret = s->cmos_data[s->cmos_index];
354 ret = s->cmos_data[s->cmos_index];
357 ret = s->cmos_data[s->cmos_index];
358 qemu_irq_lower(s->irq);
359 s->cmos_data[RTC_REG_C] = 0x00;
362 ret = s->cmos_data[s->cmos_index];
366 printf("cmos: read index=0x%02x val=0x%02x\n",
373 void rtc_set_memory(RTCState *s, int addr, int val)
375 if (addr >= 0 && addr <= 127)
376 s->cmos_data[addr] = val;
379 void rtc_set_date(RTCState *s, const struct tm *tm)
385 /* PC cmos mappings */
386 #define REG_IBM_CENTURY_BYTE 0x32
387 #define REG_IBM_PS2_CENTURY_BYTE 0x37
389 void rtc_set_date_from_host(RTCState *s)
395 /* set the CMOS date */
396 if (rtc_start_date == -1) {
408 val = to_bcd(s, (tm->tm_year / 100) + 19);
409 rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
410 rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
413 static void rtc_save(QEMUFile *f, void *opaque)
415 RTCState *s = opaque;
417 qemu_put_buffer(f, s->cmos_data, 128);
418 qemu_put_8s(f, &s->cmos_index);
420 qemu_put_be32s(f, &s->current_tm.tm_sec);
421 qemu_put_be32s(f, &s->current_tm.tm_min);
422 qemu_put_be32s(f, &s->current_tm.tm_hour);
423 qemu_put_be32s(f, &s->current_tm.tm_wday);
424 qemu_put_be32s(f, &s->current_tm.tm_mday);
425 qemu_put_be32s(f, &s->current_tm.tm_mon);
426 qemu_put_be32s(f, &s->current_tm.tm_year);
428 qemu_put_timer(f, s->periodic_timer);
429 qemu_put_be64s(f, &s->next_periodic_time);
431 qemu_put_be64s(f, &s->next_second_time);
432 qemu_put_timer(f, s->second_timer);
433 qemu_put_timer(f, s->second_timer2);
436 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
438 RTCState *s = opaque;
443 qemu_get_buffer(f, s->cmos_data, 128);
444 qemu_get_8s(f, &s->cmos_index);
446 qemu_get_be32s(f, &s->current_tm.tm_sec);
447 qemu_get_be32s(f, &s->current_tm.tm_min);
448 qemu_get_be32s(f, &s->current_tm.tm_hour);
449 qemu_get_be32s(f, &s->current_tm.tm_wday);
450 qemu_get_be32s(f, &s->current_tm.tm_mday);
451 qemu_get_be32s(f, &s->current_tm.tm_mon);
452 qemu_get_be32s(f, &s->current_tm.tm_year);
454 qemu_get_timer(f, s->periodic_timer);
455 qemu_get_be64s(f, &s->next_periodic_time);
457 qemu_get_be64s(f, &s->next_second_time);
458 qemu_get_timer(f, s->second_timer);
459 qemu_get_timer(f, s->second_timer2);
463 RTCState *rtc_init(int base, qemu_irq irq)
467 s = qemu_mallocz(sizeof(RTCState));
472 s->cmos_data[RTC_REG_A] = 0x26;
473 s->cmos_data[RTC_REG_B] = 0x02;
474 s->cmos_data[RTC_REG_C] = 0x00;
475 s->cmos_data[RTC_REG_D] = 0x80;
477 rtc_set_date_from_host(s);
479 s->periodic_timer = qemu_new_timer(vm_clock,
480 rtc_periodic_timer, s);
481 s->second_timer = qemu_new_timer(vm_clock,
482 rtc_update_second, s);
483 s->second_timer2 = qemu_new_timer(vm_clock,
484 rtc_update_second2, s);
486 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
487 qemu_mod_timer(s->second_timer2, s->next_second_time);
489 register_ioport_write(base, 2, 1, cmos_ioport_write, s);
490 register_ioport_read(base, 2, 1, cmos_ioport_read, s);
492 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
496 /* Memory mapped interface */
497 uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
499 RTCState *s = opaque;
501 return cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
504 void cmos_mm_writeb (void *opaque,
505 target_phys_addr_t addr, uint32_t value)
507 RTCState *s = opaque;
509 cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
512 uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
514 RTCState *s = opaque;
517 val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
518 #ifdef TARGET_WORDS_BIGENDIAN
524 void cmos_mm_writew (void *opaque,
525 target_phys_addr_t addr, uint32_t value)
527 RTCState *s = opaque;
528 #ifdef TARGET_WORDS_BIGENDIAN
529 value = bswap16(value);
531 cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
534 uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
536 RTCState *s = opaque;
539 val = cmos_ioport_read(s, (addr - s->base) >> s->it_shift);
540 #ifdef TARGET_WORDS_BIGENDIAN
546 void cmos_mm_writel (void *opaque,
547 target_phys_addr_t addr, uint32_t value)
549 RTCState *s = opaque;
550 #ifdef TARGET_WORDS_BIGENDIAN
551 value = bswap32(value);
553 cmos_ioport_write(s, (addr - s->base) >> s->it_shift, value);
556 static CPUReadMemoryFunc *rtc_mm_read[] = {
562 static CPUWriteMemoryFunc *rtc_mm_write[] = {
568 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq)
573 s = qemu_mallocz(sizeof(RTCState));
578 s->cmos_data[RTC_REG_A] = 0x26;
579 s->cmos_data[RTC_REG_B] = 0x02;
580 s->cmos_data[RTC_REG_C] = 0x00;
581 s->cmos_data[RTC_REG_D] = 0x80;
584 rtc_set_date_from_host(s);
586 s->periodic_timer = qemu_new_timer(vm_clock,
587 rtc_periodic_timer, s);
588 s->second_timer = qemu_new_timer(vm_clock,
589 rtc_update_second, s);
590 s->second_timer2 = qemu_new_timer(vm_clock,
591 rtc_update_second2, s);
593 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
594 qemu_mod_timer(s->second_timer2, s->next_second_time);
596 io_memory = cpu_register_io_memory(0, rtc_mm_read, rtc_mm_write, s);
597 cpu_register_physical_memory(base, 2 << it_shift, io_memory);
599 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);