2 * QEMU MC146818 RTC emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #define RTC_SECONDS_ALARM 1
31 #define RTC_MINUTES_ALARM 3
33 #define RTC_HOURS_ALARM 5
34 #define RTC_ALARM_DONT_CARE 0xC0
36 #define RTC_DAY_OF_WEEK 6
37 #define RTC_DAY_OF_MONTH 7
46 #define REG_A_UIP 0x80
48 #define REG_B_SET 0x80
49 #define REG_B_PIE 0x40
50 #define REG_B_AIE 0x20
51 #define REG_B_UIE 0x10
54 uint8_t cmos_data[128];
56 int current_time; /* in seconds */
58 uint8_t buf_data[10]; /* buffered data */
60 QEMUTimer *periodic_timer;
61 int64_t next_periodic_time;
63 int64_t next_second_time;
64 QEMUTimer *second_timer;
65 QEMUTimer *second_timer2;
68 static void rtc_set_time(RTCState *s);
69 static void rtc_set_date_buf(RTCState *s, const struct tm *tm);
70 static void rtc_copy_date(RTCState *s);
72 static void rtc_timer_update(RTCState *s, int64_t current_time)
74 int period_code, period;
75 int64_t cur_clock, next_irq_clock;
77 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
78 if (period_code != 0 &&
79 (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
82 /* period in 32 Khz cycles */
83 period = 1 << (period_code - 1);
84 /* compute 32 khz clock */
85 cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
86 next_irq_clock = (cur_clock & ~(period - 1)) + period;
87 s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
88 qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
90 qemu_del_timer(s->periodic_timer);
94 static void rtc_periodic_timer(void *opaque)
98 rtc_timer_update(s, s->next_periodic_time);
99 s->cmos_data[RTC_REG_C] |= 0xc0;
100 pic_set_irq(s->irq, 1);
103 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
105 RTCState *s = opaque;
107 if ((addr & 1) == 0) {
108 s->cmos_index = data & 0x7f;
111 printf("cmos: write index=0x%02x val=0x%02x\n",
112 s->cmos_index, data);
114 switch(s->cmos_index) {
115 case RTC_SECONDS_ALARM:
116 case RTC_MINUTES_ALARM:
117 case RTC_HOURS_ALARM:
118 /* XXX: not supported */
119 s->cmos_data[s->cmos_index] = data;
124 case RTC_DAY_OF_WEEK:
125 case RTC_DAY_OF_MONTH:
128 s->cmos_data[s->cmos_index] = data;
129 /* if in set mode, do not update the time */
130 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
135 /* UIP bit is read only */
136 s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
137 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
138 rtc_timer_update(s, qemu_get_clock(vm_clock));
141 if (data & REG_B_SET) {
142 /* set mode: reset UIP mode */
143 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
146 /* if disabling set mode, update the time */
147 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
151 s->cmos_data[RTC_REG_B] = data;
152 rtc_timer_update(s, qemu_get_clock(vm_clock));
156 /* cannot write to them */
159 s->cmos_data[s->cmos_index] = data;
165 static inline int to_bcd(RTCState *s, int a)
167 if (s->cmos_data[RTC_REG_B] & 0x04) {
170 return ((a / 10) << 4) | (a % 10);
174 static inline int from_bcd(RTCState *s, int a)
176 if (s->cmos_data[RTC_REG_B] & 0x04) {
179 return ((a >> 4) * 10) + (a & 0x0f);
183 static void rtc_set_time(RTCState *s)
185 struct tm tm1, *tm = &tm1;
187 tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
188 tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
189 tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS]);
190 tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
191 tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
192 tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
193 tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
195 /* update internal state */
196 s->buf_data[RTC_SECONDS] = s->cmos_data[RTC_SECONDS];
197 s->buf_data[RTC_MINUTES] = s->cmos_data[RTC_MINUTES];
198 s->buf_data[RTC_HOURS] = s->cmos_data[RTC_HOURS];
199 s->buf_data[RTC_DAY_OF_WEEK] = s->cmos_data[RTC_DAY_OF_WEEK];
200 s->buf_data[RTC_DAY_OF_MONTH] = s->cmos_data[RTC_DAY_OF_MONTH];
201 s->buf_data[RTC_MONTH] = s->cmos_data[RTC_MONTH];
202 s->buf_data[RTC_YEAR] = s->cmos_data[RTC_YEAR];
203 s->current_time = mktime(tm);
206 static void rtc_update_second(void *opaque)
208 RTCState *s = opaque;
211 /* if the oscillator is not in normal operation, we do not update */
212 if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
213 s->next_second_time += ticks_per_sec;
214 qemu_mod_timer(s->second_timer, s->next_second_time);
218 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
219 /* update in progress bit */
220 s->cmos_data[RTC_REG_A] |= REG_A_UIP;
222 /* should be 244 us = 8 / 32768 seconds, but currently the
223 timers do not have the necessary resolution. */
224 delay = (ticks_per_sec * 1) / 100;
227 qemu_mod_timer(s->second_timer2,
228 s->next_second_time + delay);
232 static void rtc_update_second2(void *opaque)
234 RTCState *s = opaque;
237 ti = s->current_time;
238 rtc_set_date_buf(s, gmtime(&ti));
240 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
245 if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
246 if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
247 s->cmos_data[RTC_SECONDS_ALARM] == s->buf_data[RTC_SECONDS]) &&
248 ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
249 s->cmos_data[RTC_MINUTES_ALARM] == s->buf_data[RTC_MINUTES]) &&
250 ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
251 s->cmos_data[RTC_HOURS_ALARM] == s->buf_data[RTC_HOURS])) {
253 s->cmos_data[RTC_REG_C] |= 0xa0;
254 pic_set_irq(s->irq, 1);
258 /* update ended interrupt */
259 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
260 s->cmos_data[RTC_REG_C] |= 0x90;
261 pic_set_irq(s->irq, 1);
264 /* clear update in progress bit */
265 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
267 s->next_second_time += ticks_per_sec;
268 qemu_mod_timer(s->second_timer, s->next_second_time);
271 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
273 RTCState *s = opaque;
275 if ((addr & 1) == 0) {
278 switch(s->cmos_index) {
282 case RTC_DAY_OF_WEEK:
283 case RTC_DAY_OF_MONTH:
286 ret = s->cmos_data[s->cmos_index];
289 ret = s->cmos_data[s->cmos_index];
292 ret = s->cmos_data[s->cmos_index];
293 pic_set_irq(s->irq, 0);
294 s->cmos_data[RTC_REG_C] = 0x00;
297 ret = s->cmos_data[s->cmos_index];
301 printf("cmos: read index=0x%02x val=0x%02x\n",
308 static void rtc_set_date_buf(RTCState *s, const struct tm *tm)
310 s->buf_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
311 s->buf_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
312 if (s->cmos_data[RTC_REG_B] & 0x02) {
314 s->buf_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
317 s->buf_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
318 if (tm->tm_hour >= 12)
319 s->buf_data[RTC_HOURS] |= 0x80;
321 s->buf_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
322 s->buf_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
323 s->buf_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
324 s->buf_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
327 static void rtc_copy_date(RTCState *s)
329 s->cmos_data[RTC_SECONDS] = s->buf_data[RTC_SECONDS];
330 s->cmos_data[RTC_MINUTES] = s->buf_data[RTC_MINUTES];
331 s->cmos_data[RTC_HOURS] = s->buf_data[RTC_HOURS];
332 s->cmos_data[RTC_DAY_OF_WEEK] = s->buf_data[RTC_DAY_OF_WEEK];
333 s->cmos_data[RTC_DAY_OF_MONTH] = s->buf_data[RTC_DAY_OF_MONTH];
334 s->cmos_data[RTC_MONTH] = s->buf_data[RTC_MONTH];
335 s->cmos_data[RTC_YEAR] = s->buf_data[RTC_YEAR];
338 void rtc_set_memory(RTCState *s, int addr, int val)
340 if (addr >= 0 && addr <= 127)
341 s->cmos_data[addr] = val;
344 void rtc_set_date(RTCState *s, const struct tm *tm)
346 s->current_time = mktime((struct tm *)tm);
347 rtc_set_date_buf(s, tm);
351 static void rtc_save(QEMUFile *f, void *opaque)
353 RTCState *s = opaque;
355 qemu_put_buffer(f, s->cmos_data, 128);
356 qemu_put_8s(f, &s->cmos_index);
357 qemu_put_be32s(f, &s->current_time);
358 qemu_put_buffer(f, s->buf_data, 10);
360 qemu_put_timer(f, s->periodic_timer);
361 qemu_put_be64s(f, &s->next_periodic_time);
363 qemu_put_be64s(f, &s->next_second_time);
364 qemu_put_timer(f, s->second_timer);
365 qemu_put_timer(f, s->second_timer2);
368 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
370 RTCState *s = opaque;
375 qemu_get_buffer(f, s->cmos_data, 128);
376 qemu_get_8s(f, &s->cmos_index);
377 qemu_get_be32s(f, &s->current_time);
378 qemu_get_buffer(f, s->buf_data, 10);
380 qemu_get_timer(f, s->periodic_timer);
381 qemu_get_be64s(f, &s->next_periodic_time);
383 qemu_get_be64s(f, &s->next_second_time);
384 qemu_get_timer(f, s->second_timer);
385 qemu_get_timer(f, s->second_timer2);
389 RTCState *rtc_init(int base, int irq)
393 s = qemu_mallocz(sizeof(RTCState));
398 s->cmos_data[RTC_REG_A] = 0x26;
399 s->cmos_data[RTC_REG_B] = 0x02;
400 s->cmos_data[RTC_REG_C] = 0x00;
401 s->cmos_data[RTC_REG_D] = 0x80;
403 s->periodic_timer = qemu_new_timer(vm_clock,
404 rtc_periodic_timer, s);
405 s->second_timer = qemu_new_timer(vm_clock,
406 rtc_update_second, s);
407 s->second_timer2 = qemu_new_timer(vm_clock,
408 rtc_update_second2, s);
410 s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
411 qemu_mod_timer(s->second_timer2, s->next_second_time);
413 register_ioport_write(base, 2, 1, cmos_ioport_write, s);
414 register_ioport_read(base, 2, 1, cmos_ioport_read, s);
416 register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);