2 * PowerMac MacIO device emulation
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 typedef struct macio_state_t macio_state_t;
29 struct macio_state_t {
39 static void macio_map (PCIDevice *pci_dev, int region_num,
40 uint32_t addr, uint32_t size, int type)
42 macio_state_t *macio_state;
45 macio_state = (macio_state_t *)(pci_dev + 1);
46 if (macio_state->pic_mem_index >= 0) {
47 if (macio_state->is_oldworld) {
49 cpu_register_physical_memory(addr + 0x00000, 0x1000,
50 macio_state->pic_mem_index);
53 cpu_register_physical_memory(addr + 0x40000, 0x40000,
54 macio_state->pic_mem_index);
57 if (macio_state->dbdma_mem_index >= 0) {
58 cpu_register_physical_memory(addr + 0x08000, 0x1000,
59 macio_state->dbdma_mem_index);
61 if (macio_state->cuda_mem_index >= 0) {
62 cpu_register_physical_memory(addr + 0x16000, 0x2000,
63 macio_state->cuda_mem_index);
65 for (i = 0; i < macio_state->nb_ide; i++) {
66 if (macio_state->ide_mem_index[i] >= 0) {
67 cpu_register_physical_memory(addr + 0x1f000 + (i * 0x1000), 0x1000,
68 macio_state->ide_mem_index[i]);
71 if (macio_state->nvram != NULL)
72 macio_nvram_map(macio_state->nvram, addr + 0x60000);
75 void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
76 int dbdma_mem_index, int cuda_mem_index, void *nvram,
77 int nb_ide, int *ide_mem_index)
80 macio_state_t *macio_state;
83 d = pci_register_device(bus, "macio",
84 sizeof(PCIDevice) + sizeof(macio_state_t),
86 macio_state = (macio_state_t *)(d + 1);
87 macio_state->is_oldworld = is_oldworld;
88 macio_state->pic_mem_index = pic_mem_index;
89 macio_state->dbdma_mem_index = dbdma_mem_index;
90 macio_state->cuda_mem_index = cuda_mem_index;
91 macio_state->nvram = nvram;
94 macio_state->nb_ide = nb_ide;
95 for (i = 0; i < nb_ide; i++)
96 macio_state->ide_mem_index[i] = ide_mem_index[i];
98 macio_state->ide_mem_index[i] = -1;
99 /* Note: this code is strongly inspirated from the corresponding code
101 d->config[0x00] = 0x6b; // vendor_id
102 d->config[0x01] = 0x10;
103 d->config[0x02] = device_id;
104 d->config[0x03] = device_id >> 8;
106 d->config[0x0a] = 0x00; // class_sub = pci2pci
107 d->config[0x0b] = 0xff; // class_base = bridge
108 d->config[0x0e] = 0x00; // header_type
110 d->config[0x3d] = 0x01; // interrupt on pin 1
112 pci_register_io_region(d, 0, 0x80000,
113 PCI_ADDRESS_SPACE_MEM, macio_map);