2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu-timer.h"
32 #if defined(DEBUG_NVRAM)
33 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
35 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
39 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
40 * alarm and a watchdog timer and related control registers. In the
41 * PPC platform there is also a nvram lock function.
44 /* Model parameters */
45 int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
46 /* Hardware parameters */
49 target_phys_addr_t mem_base;
55 /* Alarm & watchdog */
57 struct QEMUTimer *alrm_timer;
58 struct QEMUTimer *wd_timer;
65 /* Fake timer functions */
66 /* Generic helpers for BCD */
67 static inline uint8_t toBCD (uint8_t value)
69 return (((value / 10) % 10) << 4) | (value % 10);
72 static inline uint8_t fromBCD (uint8_t BCD)
74 return ((BCD >> 4) * 10) + (BCD & 0x0F);
77 /* RTC management helpers */
78 static void get_time (m48t59_t *NVRAM, struct tm *tm)
82 t = time(NULL) + NVRAM->time_offset;
84 memcpy(tm,localtime(&t),sizeof(*tm));
89 localtime_r (&t, tm) ;
93 static void set_time (m48t59_t *NVRAM, struct tm *tm)
97 new_time = mktime(tm);
99 NVRAM->time_offset = new_time - now;
102 /* Alarm management */
103 static void alarm_cb (void *opaque)
105 struct tm tm, tm_now;
107 m48t59_t *NVRAM = opaque;
109 qemu_set_irq(NVRAM->IRQ, 1);
110 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
111 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
112 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
113 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
114 /* Repeat once a month */
115 get_time(NVRAM, &tm_now);
116 memcpy(&tm, &tm_now, sizeof(struct tm));
118 if (tm.tm_mon == 13) {
122 next_time = mktime(&tm);
123 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
124 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
125 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
126 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
127 /* Repeat once a day */
128 next_time = 24 * 60 * 60 + mktime(&tm_now);
129 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
130 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
131 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
132 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
133 /* Repeat once an hour */
134 next_time = 60 * 60 + mktime(&tm_now);
135 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
136 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
137 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
138 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
139 /* Repeat once a minute */
140 next_time = 60 + mktime(&tm_now);
142 /* Repeat once a second */
143 next_time = 1 + mktime(&tm_now);
145 qemu_mod_timer(NVRAM->alrm_timer, next_time * 1000);
146 qemu_set_irq(NVRAM->IRQ, 0);
150 static void get_alarm (m48t59_t *NVRAM, struct tm *tm)
153 memcpy(tm,localtime(&NVRAM->alarm),sizeof(*tm));
156 gmtime_r (&NVRAM->alarm, tm);
158 localtime_r (&NVRAM->alarm, tm);
162 static void set_alarm (m48t59_t *NVRAM, struct tm *tm)
164 NVRAM->alarm = mktime(tm);
165 if (NVRAM->alrm_timer != NULL) {
166 qemu_del_timer(NVRAM->alrm_timer);
167 if (NVRAM->alarm - time(NULL) > 0)
168 qemu_mod_timer(NVRAM->alrm_timer, NVRAM->alarm * 1000);
172 /* Watchdog management */
173 static void watchdog_cb (void *opaque)
175 m48t59_t *NVRAM = opaque;
177 NVRAM->buffer[0x1FF0] |= 0x80;
178 if (NVRAM->buffer[0x1FF7] & 0x80) {
179 NVRAM->buffer[0x1FF7] = 0x00;
180 NVRAM->buffer[0x1FFC] &= ~0x40;
181 /* May it be a hw CPU Reset instead ? */
182 qemu_system_reset_request();
184 qemu_set_irq(NVRAM->IRQ, 1);
185 qemu_set_irq(NVRAM->IRQ, 0);
189 static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
191 uint64_t interval; /* in 1/16 seconds */
193 NVRAM->buffer[0x1FF0] &= ~0x80;
194 if (NVRAM->wd_timer != NULL) {
195 qemu_del_timer(NVRAM->wd_timer);
197 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
198 qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
199 ((interval * 1000) >> 4));
204 /* Direct access to NVRAM */
205 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
207 m48t59_t *NVRAM = opaque;
211 if (addr > 0x1FF8 && addr < 0x2000)
212 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
214 /* check for NVRAM access */
215 if ((NVRAM->type == 2 && addr < 0x7f8) ||
216 (NVRAM->type == 8 && addr < 0x1ff8) ||
217 (NVRAM->type == 59 && addr < 0x1ff0))
223 /* flags register : read-only */
230 tmp = fromBCD(val & 0x7F);
231 if (tmp >= 0 && tmp <= 59) {
232 get_alarm(NVRAM, &tm);
234 NVRAM->buffer[0x1FF2] = val;
235 set_alarm(NVRAM, &tm);
240 tmp = fromBCD(val & 0x7F);
241 if (tmp >= 0 && tmp <= 59) {
242 get_alarm(NVRAM, &tm);
244 NVRAM->buffer[0x1FF3] = val;
245 set_alarm(NVRAM, &tm);
250 tmp = fromBCD(val & 0x3F);
251 if (tmp >= 0 && tmp <= 23) {
252 get_alarm(NVRAM, &tm);
254 NVRAM->buffer[0x1FF4] = val;
255 set_alarm(NVRAM, &tm);
260 tmp = fromBCD(val & 0x1F);
262 get_alarm(NVRAM, &tm);
264 NVRAM->buffer[0x1FF5] = val;
265 set_alarm(NVRAM, &tm);
270 NVRAM->buffer[0x1FF6] = val;
274 NVRAM->buffer[0x1FF7] = val;
275 set_up_watchdog(NVRAM, val);
280 NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
285 tmp = fromBCD(val & 0x7F);
286 if (tmp >= 0 && tmp <= 59) {
287 get_time(NVRAM, &tm);
289 set_time(NVRAM, &tm);
291 if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
293 NVRAM->stop_time = time(NULL);
295 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
296 NVRAM->stop_time = 0;
299 NVRAM->buffer[addr] = val & 0x80;
304 tmp = fromBCD(val & 0x7F);
305 if (tmp >= 0 && tmp <= 59) {
306 get_time(NVRAM, &tm);
308 set_time(NVRAM, &tm);
314 tmp = fromBCD(val & 0x3F);
315 if (tmp >= 0 && tmp <= 23) {
316 get_time(NVRAM, &tm);
318 set_time(NVRAM, &tm);
323 /* day of the week / century */
324 tmp = fromBCD(val & 0x07);
325 get_time(NVRAM, &tm);
327 set_time(NVRAM, &tm);
328 NVRAM->buffer[addr] = val & 0x40;
333 tmp = fromBCD(val & 0x1F);
335 get_time(NVRAM, &tm);
337 set_time(NVRAM, &tm);
343 tmp = fromBCD(val & 0x1F);
344 if (tmp >= 1 && tmp <= 12) {
345 get_time(NVRAM, &tm);
347 set_time(NVRAM, &tm);
354 if (tmp >= 0 && tmp <= 99) {
355 get_time(NVRAM, &tm);
356 if (NVRAM->type == 8)
357 tm.tm_year = fromBCD(val) + 68; // Base year is 1968
359 tm.tm_year = fromBCD(val);
360 set_time(NVRAM, &tm);
364 /* Check lock registers state */
365 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
367 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
370 if (addr < NVRAM->size) {
371 NVRAM->buffer[addr] = val & 0xFF;
377 uint32_t m48t59_read (void *opaque, uint32_t addr)
379 m48t59_t *NVRAM = opaque;
381 uint32_t retval = 0xFF;
383 /* check for NVRAM access */
384 if ((NVRAM->type == 2 && addr < 0x078f) ||
385 (NVRAM->type == 8 && addr < 0x1ff8) ||
386 (NVRAM->type == 59 && addr < 0x1ff0))
414 /* A read resets the watchdog */
415 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
424 get_time(NVRAM, &tm);
425 retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
430 get_time(NVRAM, &tm);
431 retval = toBCD(tm.tm_min);
436 get_time(NVRAM, &tm);
437 retval = toBCD(tm.tm_hour);
441 /* day of the week / century */
442 get_time(NVRAM, &tm);
443 retval = NVRAM->buffer[addr] | tm.tm_wday;
448 get_time(NVRAM, &tm);
449 retval = toBCD(tm.tm_mday);
454 get_time(NVRAM, &tm);
455 retval = toBCD(tm.tm_mon + 1);
460 get_time(NVRAM, &tm);
461 if (NVRAM->type == 8)
462 retval = toBCD(tm.tm_year - 68); // Base year is 1968
464 retval = toBCD(tm.tm_year);
467 /* Check lock registers state */
468 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
470 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
473 if (addr < NVRAM->size) {
474 retval = NVRAM->buffer[addr];
478 if (addr > 0x1FF9 && addr < 0x2000)
479 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
484 void m48t59_set_addr (void *opaque, uint32_t addr)
486 m48t59_t *NVRAM = opaque;
491 void m48t59_toggle_lock (void *opaque, int lock)
493 m48t59_t *NVRAM = opaque;
495 NVRAM->lock ^= 1 << lock;
498 /* IO access to NVRAM */
499 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
501 m48t59_t *NVRAM = opaque;
503 addr -= NVRAM->io_base;
504 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
507 NVRAM->addr &= ~0x00FF;
511 NVRAM->addr &= ~0xFF00;
512 NVRAM->addr |= val << 8;
515 m48t59_write(NVRAM, val, NVRAM->addr);
516 NVRAM->addr = 0x0000;
523 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
525 m48t59_t *NVRAM = opaque;
528 addr -= NVRAM->io_base;
531 retval = m48t59_read(NVRAM, NVRAM->addr);
537 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
542 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
544 m48t59_t *NVRAM = opaque;
546 addr -= NVRAM->mem_base;
547 m48t59_write(NVRAM, addr, value & 0xff);
550 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
552 m48t59_t *NVRAM = opaque;
554 addr -= NVRAM->mem_base;
555 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
556 m48t59_write(NVRAM, addr + 1, value & 0xff);
559 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
561 m48t59_t *NVRAM = opaque;
563 addr -= NVRAM->mem_base;
564 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
565 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
566 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
567 m48t59_write(NVRAM, addr + 3, value & 0xff);
570 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
572 m48t59_t *NVRAM = opaque;
575 addr -= NVRAM->mem_base;
576 retval = m48t59_read(NVRAM, addr);
580 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
582 m48t59_t *NVRAM = opaque;
585 addr -= NVRAM->mem_base;
586 retval = m48t59_read(NVRAM, addr) << 8;
587 retval |= m48t59_read(NVRAM, addr + 1);
591 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
593 m48t59_t *NVRAM = opaque;
596 addr -= NVRAM->mem_base;
597 retval = m48t59_read(NVRAM, addr) << 24;
598 retval |= m48t59_read(NVRAM, addr + 1) << 16;
599 retval |= m48t59_read(NVRAM, addr + 2) << 8;
600 retval |= m48t59_read(NVRAM, addr + 3);
604 static CPUWriteMemoryFunc *nvram_write[] = {
610 static CPUReadMemoryFunc *nvram_read[] = {
616 static void m48t59_save(QEMUFile *f, void *opaque)
618 m48t59_t *s = opaque;
620 qemu_put_8s(f, &s->lock);
621 qemu_put_be16s(f, &s->addr);
622 qemu_put_buffer(f, s->buffer, s->size);
625 static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
627 m48t59_t *s = opaque;
632 qemu_get_8s(f, &s->lock);
633 qemu_get_be16s(f, &s->addr);
634 qemu_get_buffer(f, s->buffer, s->size);
639 static void m48t59_reset(void *opaque)
641 m48t59_t *NVRAM = opaque;
643 if (NVRAM->alrm_timer != NULL)
644 qemu_del_timer(NVRAM->alrm_timer);
646 if (NVRAM->wd_timer != NULL)
647 qemu_del_timer(NVRAM->wd_timer);
650 /* Initialisation routine */
651 m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
652 uint32_t io_base, uint16_t size,
656 target_phys_addr_t save_base;
658 s = qemu_mallocz(sizeof(m48t59_t));
661 s->buffer = qemu_mallocz(size);
668 s->mem_base = mem_base;
669 s->io_base = io_base;
673 register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
674 register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
677 s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
678 cpu_register_physical_memory(mem_base, size, s->mem_index);
681 s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
682 s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
686 qemu_register_reset(m48t59_reset, s);
687 save_base = mem_base ? mem_base : io_base;
688 register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);