2 * QEMU M48T08 NVRAM emulation for Sparc platform
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(DEBUG_NVRAM)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
35 #define NVRAM_MAX_MEM 0x1ff0
36 #define NVRAM_MAXADDR 0x1fff
46 /* Fake timer functions */
47 /* Generic helpers for BCD */
48 static inline uint8_t toBCD (uint8_t value)
50 return (((value / 10) % 10) << 4) | (value % 10);
53 static inline uint8_t fromBCD (uint8_t BCD)
55 return ((BCD >> 4) * 10) + (BCD & 0x0F);
58 /* RTC management helpers */
59 static void get_time (m48t08_t *NVRAM, struct tm *tm)
63 t = time(NULL) + NVRAM->time_offset;
65 memcpy(tm,localtime(&t),sizeof(*tm));
67 localtime_r (&t, tm) ;
71 static void set_time (m48t08_t *NVRAM, struct tm *tm)
75 new_time = mktime(tm);
77 NVRAM->time_offset = new_time - now;
80 /* Direct access to NVRAM */
81 void m48t08_write (m48t08_t *NVRAM, uint32_t addr, uint8_t val)
86 addr &= NVRAM_MAXADDR;
90 NVRAM->buffer[0x1FF8] = (val & ~0xA0) | 0x90;
94 tmp = fromBCD(val & 0x7F);
95 if (tmp >= 0 && tmp <= 59) {
100 if ((val & 0x80) ^ (NVRAM->buffer[0x1FF9] & 0x80)) {
102 NVRAM->stop_time = time(NULL);
104 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
105 NVRAM->stop_time = 0;
108 NVRAM->buffer[0x1FF9] = val & 0x80;
112 tmp = fromBCD(val & 0x7F);
113 if (tmp >= 0 && tmp <= 59) {
114 get_time(NVRAM, &tm);
116 set_time(NVRAM, &tm);
121 tmp = fromBCD(val & 0x3F);
122 if (tmp >= 0 && tmp <= 23) {
123 get_time(NVRAM, &tm);
125 set_time(NVRAM, &tm);
129 /* day of the week / century */
130 tmp = fromBCD(val & 0x07);
131 get_time(NVRAM, &tm);
133 set_time(NVRAM, &tm);
134 NVRAM->buffer[0x1FFC] = val & 0x40;
138 tmp = fromBCD(val & 0x1F);
140 get_time(NVRAM, &tm);
142 set_time(NVRAM, &tm);
147 tmp = fromBCD(val & 0x1F);
148 if (tmp >= 1 && tmp <= 12) {
149 get_time(NVRAM, &tm);
151 set_time(NVRAM, &tm);
157 if (tmp >= 0 && tmp <= 99) {
158 get_time(NVRAM, &tm);
159 tm.tm_year = fromBCD(val);
160 set_time(NVRAM, &tm);
164 NVRAM->buffer[addr] = val & 0xFF;
169 uint8_t m48t08_read (m48t08_t *NVRAM, uint32_t addr)
172 uint8_t retval = 0xFF;
174 addr &= NVRAM_MAXADDR;
181 get_time(NVRAM, &tm);
182 retval = (NVRAM->buffer[0x1FF9] & 0x80) | toBCD(tm.tm_sec);
186 get_time(NVRAM, &tm);
187 retval = toBCD(tm.tm_min);
191 get_time(NVRAM, &tm);
192 retval = toBCD(tm.tm_hour);
195 /* day of the week / century */
196 get_time(NVRAM, &tm);
197 retval = NVRAM->buffer[0x1FFC] | tm.tm_wday;
201 get_time(NVRAM, &tm);
202 retval = toBCD(tm.tm_mday);
206 get_time(NVRAM, &tm);
207 retval = toBCD(tm.tm_mon + 1);
211 get_time(NVRAM, &tm);
212 retval = toBCD(tm.tm_year);
216 retval = NVRAM->buffer[addr];
222 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
224 m48t08_t *NVRAM = opaque;
226 m48t08_write(NVRAM, addr, value);
229 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
231 m48t08_t *NVRAM = opaque;
233 m48t08_write(NVRAM, addr, value);
234 m48t08_write(NVRAM, addr + 1, value >> 8);
237 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
239 m48t08_t *NVRAM = opaque;
241 m48t08_write(NVRAM, addr, value);
242 m48t08_write(NVRAM, addr + 1, value >> 8);
243 m48t08_write(NVRAM, addr + 2, value >> 16);
244 m48t08_write(NVRAM, addr + 3, value >> 24);
247 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
249 m48t08_t *NVRAM = opaque;
252 retval = m48t08_read(NVRAM, addr);
256 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
258 m48t08_t *NVRAM = opaque;
261 retval = m48t08_read(NVRAM, addr) << 8;
262 retval |= m48t08_read(NVRAM, addr + 1);
266 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
268 m48t08_t *NVRAM = opaque;
271 retval = m48t08_read(NVRAM, addr) << 24;
272 retval |= m48t08_read(NVRAM, addr + 1) << 16;
273 retval |= m48t08_read(NVRAM, addr + 2) << 8;
274 retval |= m48t08_read(NVRAM, addr + 3);
278 static CPUWriteMemoryFunc *nvram_write[] = {
284 static CPUReadMemoryFunc *nvram_read[] = {
290 static void nvram_save(QEMUFile *f, void *opaque)
292 m48t08_t *s = opaque;
294 qemu_put_be32s(f, (uint32_t *)&s->time_offset);
295 qemu_put_be32s(f, (uint32_t *)&s->stop_time);
296 qemu_put_buffer(f, s->buffer, 0x2000);
299 static int nvram_load(QEMUFile *f, void *opaque, int version_id)
301 m48t08_t *s = opaque;
306 qemu_get_be32s(f, (uint32_t *)&s->time_offset);
307 qemu_get_be32s(f, (uint32_t *)&s->stop_time);
308 qemu_get_buffer(f, s->buffer, 0x2000);
312 static void m48t08_reset(void *opaque)
314 m48t08_t *s = opaque;
321 /* Initialisation routine */
322 m48t08_t *m48t08_init(uint32_t mem_base, uint16_t size)
327 s = qemu_mallocz(sizeof(m48t08_t));
330 s->buffer = qemu_mallocz(size);
336 mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
337 cpu_register_physical_memory(mem_base, 0x2000, mem_index);
340 register_savevm("nvram", mem_base, 1, nvram_save, nvram_load, s);
341 qemu_register_reset(m48t08_reset, s);
348 unsigned char id_format; /* Format identifier (always 0x01) */
349 unsigned char id_machtype; /* Machine type */
350 unsigned char id_ethaddr[6]; /* Hardware ethernet address */
351 long id_date; /* Date of manufacture */
352 unsigned int id_sernum:24; /* Unique serial number */
353 unsigned char id_cksum; /* Checksum - xor of the data bytes */
354 unsigned char reserved[16];