2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the LGPL.
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
16 //#define DEBUG_LSI_REG
19 #define DPRINTF(fmt, args...) \
20 do { printf("lsi_scsi: " fmt , ##args); } while (0)
21 #define BADF(fmt, args...) \
22 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
24 #define DPRINTF(fmt, args...) do {} while(0)
25 #define BADF(fmt, args...) \
26 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
29 #define LSI_SCNTL0_TRG 0x01
30 #define LSI_SCNTL0_AAP 0x02
31 #define LSI_SCNTL0_EPC 0x08
32 #define LSI_SCNTL0_WATN 0x10
33 #define LSI_SCNTL0_START 0x20
35 #define LSI_SCNTL1_SST 0x01
36 #define LSI_SCNTL1_IARB 0x02
37 #define LSI_SCNTL1_AESP 0x04
38 #define LSI_SCNTL1_RST 0x08
39 #define LSI_SCNTL1_CON 0x10
40 #define LSI_SCNTL1_DHP 0x20
41 #define LSI_SCNTL1_ADB 0x40
42 #define LSI_SCNTL1_EXC 0x80
44 #define LSI_SCNTL2_WSR 0x01
45 #define LSI_SCNTL2_VUE0 0x02
46 #define LSI_SCNTL2_VUE1 0x04
47 #define LSI_SCNTL2_WSS 0x08
48 #define LSI_SCNTL2_SLPHBEN 0x10
49 #define LSI_SCNTL2_SLPMD 0x20
50 #define LSI_SCNTL2_CHM 0x40
51 #define LSI_SCNTL2_SDU 0x80
53 #define LSI_ISTAT0_DIP 0x01
54 #define LSI_ISTAT0_SIP 0x02
55 #define LSI_ISTAT0_INTF 0x04
56 #define LSI_ISTAT0_CON 0x08
57 #define LSI_ISTAT0_SEM 0x10
58 #define LSI_ISTAT0_SIGP 0x20
59 #define LSI_ISTAT0_SRST 0x40
60 #define LSI_ISTAT0_ABRT 0x80
62 #define LSI_ISTAT1_SI 0x01
63 #define LSI_ISTAT1_SRUN 0x02
64 #define LSI_ISTAT1_FLSH 0x04
66 #define LSI_SSTAT0_SDP0 0x01
67 #define LSI_SSTAT0_RST 0x02
68 #define LSI_SSTAT0_WOA 0x04
69 #define LSI_SSTAT0_LOA 0x08
70 #define LSI_SSTAT0_AIP 0x10
71 #define LSI_SSTAT0_OLF 0x20
72 #define LSI_SSTAT0_ORF 0x40
73 #define LSI_SSTAT0_ILF 0x80
75 #define LSI_SIST0_PAR 0x01
76 #define LSI_SIST0_RST 0x02
77 #define LSI_SIST0_UDC 0x04
78 #define LSI_SIST0_SGE 0x08
79 #define LSI_SIST0_RSL 0x10
80 #define LSI_SIST0_SEL 0x20
81 #define LSI_SIST0_CMP 0x40
82 #define LSI_SIST0_MA 0x80
84 #define LSI_SIST1_HTH 0x01
85 #define LSI_SIST1_GEN 0x02
86 #define LSI_SIST1_STO 0x04
87 #define LSI_SIST1_SBMC 0x10
89 #define LSI_SOCL_IO 0x01
90 #define LSI_SOCL_CD 0x02
91 #define LSI_SOCL_MSG 0x04
92 #define LSI_SOCL_ATN 0x08
93 #define LSI_SOCL_SEL 0x10
94 #define LSI_SOCL_BSY 0x20
95 #define LSI_SOCL_ACK 0x40
96 #define LSI_SOCL_REQ 0x80
98 #define LSI_DSTAT_IID 0x01
99 #define LSI_DSTAT_SIR 0x04
100 #define LSI_DSTAT_SSI 0x08
101 #define LSI_DSTAT_ABRT 0x10
102 #define LSI_DSTAT_BF 0x20
103 #define LSI_DSTAT_MDPE 0x40
104 #define LSI_DSTAT_DFE 0x80
106 #define LSI_DCNTL_COM 0x01
107 #define LSI_DCNTL_IRQD 0x02
108 #define LSI_DCNTL_STD 0x04
109 #define LSI_DCNTL_IRQM 0x08
110 #define LSI_DCNTL_SSM 0x10
111 #define LSI_DCNTL_PFEN 0x20
112 #define LSI_DCNTL_PFF 0x40
113 #define LSI_DCNTL_CLSE 0x80
115 #define LSI_DMODE_MAN 0x01
116 #define LSI_DMODE_BOF 0x02
117 #define LSI_DMODE_ERMP 0x04
118 #define LSI_DMODE_ERL 0x08
119 #define LSI_DMODE_DIOM 0x10
120 #define LSI_DMODE_SIOM 0x20
122 #define LSI_CTEST2_DACK 0x01
123 #define LSI_CTEST2_DREQ 0x02
124 #define LSI_CTEST2_TEOP 0x04
125 #define LSI_CTEST2_PCICIE 0x08
126 #define LSI_CTEST2_CM 0x10
127 #define LSI_CTEST2_CIO 0x20
128 #define LSI_CTEST2_SIGP 0x40
129 #define LSI_CTEST2_DDIR 0x80
131 #define LSI_CTEST5_BL2 0x04
132 #define LSI_CTEST5_DDIR 0x08
133 #define LSI_CTEST5_MASR 0x10
134 #define LSI_CTEST5_DFSN 0x20
135 #define LSI_CTEST5_BBCK 0x40
136 #define LSI_CTEST5_ADCK 0x80
138 #define LSI_CCNTL0_DILS 0x01
139 #define LSI_CCNTL0_DISFC 0x10
140 #define LSI_CCNTL0_ENNDJ 0x20
141 #define LSI_CCNTL0_PMJCTL 0x40
142 #define LSI_CCNTL0_ENPMJ 0x80
152 /* The HBA is ID 7, so for simplicitly limit to 7 devices. */
153 #define LSI_MAX_DEVS 7
155 /* Maximum length of MSG IN data. */
156 #define LSI_MAX_MSGIN_LEN 8
158 /* Flag set if this is a tagged command. */
159 #define LSI_TAG_VALID (1 << 16)
171 uint32_t script_ram_base;
173 int carry; /* ??? Should this be an a visible register somewhere? */
175 /* Action to take at the end of a MSG IN phase.
176 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
179 uint8_t msg[LSI_MAX_MSGIN_LEN];
180 /* 0 if SCRIPTS are running or stopped.
181 * 1 if a Wait Reselect instruction has been issued.
182 * 2 if processing DMA from lsi_execute_script.
183 * 3 if a DMA operation is in progress. */
185 SCSIDevice *scsi_dev[LSI_MAX_DEVS];
186 SCSIDevice *current_dev;
188 /* The tag is a combination of the device ID and the SCSI tag. */
189 uint32_t current_tag;
190 uint32_t current_dma_len;
254 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
256 /* Script ram is stored as 32-bit words in host byteorder. */
257 uint32_t script_ram[2048];
260 static void lsi_soft_reset(LSIState *s)
270 memset(s->scratch, 0, sizeof(s->scratch));
324 static uint8_t lsi_reg_readb(LSIState *s, int offset);
325 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
326 static void lsi_execute_script(LSIState *s);
328 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
332 /* Optimize reading from SCRIPTS RAM. */
333 if ((addr & 0xffffe000) == s->script_ram_base) {
334 return s->script_ram[(addr & 0x1fff) >> 2];
336 cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
337 return cpu_to_le32(buf);
340 static void lsi_stop_script(LSIState *s)
342 s->istat1 &= ~LSI_ISTAT1_SRUN;
345 static void lsi_update_irq(LSIState *s)
348 static int last_level;
350 /* It's unclear whether the DIP/SIP bits should be cleared when the
351 Interrupt Status Registers are cleared or when istat0 is read.
352 We currently do the formwer, which seems to work. */
355 if (s->dstat & s->dien)
357 s->istat0 |= LSI_ISTAT0_DIP;
359 s->istat0 &= ~LSI_ISTAT0_DIP;
362 if (s->sist0 || s->sist1) {
363 if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
365 s->istat0 |= LSI_ISTAT0_SIP;
367 s->istat0 &= ~LSI_ISTAT0_SIP;
369 if (s->istat0 & LSI_ISTAT0_INTF)
372 if (level != last_level) {
373 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
374 level, s->dstat, s->sist1, s->sist0);
377 pci_set_irq(&s->pci_dev, 0, level);
380 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
381 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
386 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
387 stat1, stat0, s->sist1, s->sist0);
390 /* Stop processor on fatal or unmasked interrupt. As a special hack
391 we don't stop processing when raising STO. Instead continue
392 execution and stop at the next insn that accesses the SCSI bus. */
393 mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
394 mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
395 mask1 &= ~LSI_SIST1_STO;
396 if (s->sist0 & mask0 || s->sist1 & mask1) {
402 /* Stop SCRIPTS execution and raise a DMA interrupt. */
403 static void lsi_script_dma_interrupt(LSIState *s, int stat)
405 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
411 static inline void lsi_set_phase(LSIState *s, int phase)
413 s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
416 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
418 /* Trigger a phase mismatch. */
419 if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
420 if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
425 DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
427 DPRINTF("Phase mismatch interrupt\n");
428 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
431 lsi_set_phase(s, new_phase);
435 /* Resume SCRIPTS execution after a DMA operation. */
436 static void lsi_resume_script(LSIState *s)
438 if (s->waiting != 2) {
440 lsi_execute_script(s);
446 /* Initiate a SCSI layer data transfer. */
447 static void lsi_do_dma(LSIState *s, int out)
452 if (!s->current_dma_len) {
453 /* Wait until data is available. */
454 DPRINTF("DMA no data available\n");
459 if (count > s->current_dma_len)
460 count = s->current_dma_len;
461 DPRINTF("DMA addr=0x%08x len=%d\n", s->dnad, count);
468 if (s->dma_buf == NULL) {
469 s->dma_buf = scsi_get_buf(s->current_dev, s->current_tag);
472 /* ??? Set SFBR to first data byte. */
474 cpu_physical_memory_read(addr, s->dma_buf, count);
476 cpu_physical_memory_write(addr, s->dma_buf, count);
478 s->current_dma_len -= count;
479 if (s->current_dma_len == 0) {
482 /* Write the data. */
483 scsi_write_data(s->current_dev, s->current_tag);
485 /* Request any remaining data. */
486 scsi_read_data(s->current_dev, s->current_tag);
490 lsi_resume_script(s);
495 /* Add a command to the queue. */
496 static void lsi_queue_command(LSIState *s)
500 DPRINTF("Queueing tag=0x%x\n", s->current_tag);
501 if (s->queue_len == s->active_commands) {
503 s->queue = realloc(s->queue, s->queue_len * sizeof(lsi_queue));
505 p = &s->queue[s->active_commands++];
506 p->tag = s->current_tag;
508 p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
511 /* Queue a byte for a MSG IN phase. */
512 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
514 if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
515 BADF("MSG IN data too long\n");
517 DPRINTF("MSG IN 0x%02x\n", data);
518 s->msg[s->msg_len++] = data;
522 /* Perform reselection to continue a command. */
523 static void lsi_reselect(LSIState *s, uint32_t tag)
530 for (n = 0; n < s->active_commands; n++) {
535 if (n == s->active_commands) {
536 BADF("Reselected non-existant command tag=0x%x\n", tag);
539 id = (tag >> 8) & 0xf;
541 DPRINTF("Reselected target %d\n", id);
542 s->current_dev = s->scsi_dev[id];
543 s->current_tag = tag;
544 s->scntl1 |= LSI_SCNTL1_CON;
545 lsi_set_phase(s, PHASE_MI);
546 s->msg_action = p->out ? 2 : 3;
547 s->current_dma_len = p->pending;
549 lsi_add_msg_byte(s, 0x80);
550 if (s->current_tag & LSI_TAG_VALID) {
551 lsi_add_msg_byte(s, 0x20);
552 lsi_add_msg_byte(s, tag & 0xff);
555 s->active_commands--;
556 if (n != s->active_commands) {
557 s->queue[n] = s->queue[s->active_commands];
561 /* Record that data is available for a queued command. Returns zero if
562 the device was reselected, nonzero if the IO is deferred. */
563 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
567 for (i = 0; i < s->active_commands; i++) {
571 BADF("Multiple IO pending for tag %d\n", tag);
574 if (s->waiting == 1) {
575 /* Reselect device. */
576 lsi_reselect(s, tag);
579 DPRINTF("Queueing IO tag=0x%x\n", tag);
585 BADF("IO with unknown tag %d\n", tag);
589 /* Callback to indicate that the SCSI layer has completed a transfer. */
590 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
593 LSIState *s = (LSIState *)opaque;
596 out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
597 if (reason == SCSI_REASON_DONE) {
598 DPRINTF("Command complete sense=%d\n", (int)arg);
600 if (s->waiting && s->dbc != 0) {
601 /* Raise phase mismatch for short transfers. */
602 lsi_bad_phase(s, out, PHASE_ST);
604 lsi_set_phase(s, PHASE_ST);
606 lsi_resume_script(s);
610 if (s->waiting == 1 || tag != s->current_tag) {
611 if (lsi_queue_tag(s, tag, arg))
614 DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
615 s->current_dma_len = arg;
618 if (s->waiting == 1 || s->dbc == 0) {
619 lsi_resume_script(s);
625 static void lsi_do_command(LSIState *s)
630 DPRINTF("Send command len=%d\n", s->dbc);
633 cpu_physical_memory_read(s->dnad, buf, s->dbc);
635 n = scsi_send_command(s->current_dev, s->current_tag, buf, s->current_lun);
637 lsi_set_phase(s, PHASE_DI);
638 scsi_read_data(s->current_dev, s->current_tag);
640 lsi_set_phase(s, PHASE_DO);
641 scsi_write_data(s->current_dev, s->current_tag);
643 if (n && s->current_dma_len == 0) {
644 /* Command did not complete immediately so disconnect. */
645 lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
646 lsi_add_msg_byte(s, 4); /* DISCONNECT */
647 lsi_set_phase(s, PHASE_MI);
649 lsi_queue_command(s);
653 static void lsi_do_status(LSIState *s)
656 DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
658 BADF("Bad Status move\n");
662 cpu_physical_memory_write(s->dnad, &sense, 1);
663 lsi_set_phase(s, PHASE_MI);
665 lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
668 static void lsi_disconnect(LSIState *s)
670 s->scntl1 &= ~LSI_SCNTL1_CON;
671 s->sstat1 &= ~PHASE_MASK;
674 static void lsi_do_msgin(LSIState *s)
677 DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
682 cpu_physical_memory_write(s->dnad, s->msg, len);
683 /* Linux drivers rely on the last byte being in the SIDL. */
684 s->sidl = s->msg[len - 1];
687 memmove(s->msg, s->msg + len, s->msg_len);
689 /* ??? Check if ATN (not yet implemented) is asserted and maybe
690 switch to PHASE_MO. */
691 switch (s->msg_action) {
693 lsi_set_phase(s, PHASE_CMD);
699 lsi_set_phase(s, PHASE_DO);
702 lsi_set_phase(s, PHASE_DI);
710 /* Read the next byte during a MSGOUT phase. */
711 static uint8_t lsi_get_msgbyte(LSIState *s)
714 cpu_physical_memory_read(s->dnad, &data, 1);
720 static void lsi_do_msgout(LSIState *s)
725 DPRINTF("MSG out len=%d\n", s->dbc);
727 msg = lsi_get_msgbyte(s);
732 DPRINTF("MSG: Disconnect\n");
736 DPRINTF("MSG: No Operation\n");
737 lsi_set_phase(s, PHASE_CMD);
740 len = lsi_get_msgbyte(s);
741 msg = lsi_get_msgbyte(s);
742 DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
745 DPRINTF("SDTR (ignored)\n");
749 DPRINTF("WDTR (ignored)\n");
756 case 0x20: /* SIMPLE queue */
757 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
758 DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
760 case 0x21: /* HEAD of queue */
761 BADF("HEAD queue not implemented\n");
762 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
764 case 0x22: /* ORDERED queue */
765 BADF("ORDERED queue not implemented\n");
766 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
769 if ((msg & 0x80) == 0) {
772 s->current_lun = msg & 7;
773 DPRINTF("Select LUN %d\n", s->current_lun);
774 lsi_set_phase(s, PHASE_CMD);
780 BADF("Unimplemented message 0x%02x\n", msg);
781 lsi_set_phase(s, PHASE_MI);
782 lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
786 /* Sign extend a 24-bit value. */
787 static inline int32_t sxt24(int32_t n)
789 return (n << 8) >> 8;
792 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
795 uint8_t buf[TARGET_PAGE_SIZE];
797 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
799 n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
800 cpu_physical_memory_read(src, buf, n);
801 cpu_physical_memory_write(dest, buf, n);
808 static void lsi_wait_reselect(LSIState *s)
811 DPRINTF("Wait Reselect\n");
812 if (s->current_dma_len)
813 BADF("Reselect with pending DMA\n");
814 for (i = 0; i < s->active_commands; i++) {
815 if (s->queue[i].pending) {
816 lsi_reselect(s, s->queue[i].tag);
820 if (s->current_dma_len == 0) {
825 static void lsi_execute_script(LSIState *s)
831 s->istat1 |= LSI_ISTAT1_SRUN;
833 insn = read_dword(s, s->dsp);
834 addr = read_dword(s, s->dsp + 4);
835 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
837 s->dcmd = insn >> 24;
839 switch (insn >> 30) {
840 case 0: /* Block move. */
841 if (s->sist1 & LSI_SIST1_STO) {
842 DPRINTF("Delayed select timeout\n");
846 s->dbc = insn & 0xffffff;
848 if (insn & (1 << 29)) {
849 /* Indirect addressing. */
850 addr = read_dword(s, addr);
851 } else if (insn & (1 << 28)) {
854 /* Table indirect addressing. */
855 offset = sxt24(addr);
856 cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
857 s->dbc = cpu_to_le32(buf[0]);
858 addr = cpu_to_le32(buf[1]);
860 if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
861 DPRINTF("Wrong phase got %d expected %d\n",
862 s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
863 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
867 switch (s->sstat1 & 0x7) {
893 BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
896 s->dfifo = s->dbc & 0xff;
897 s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
900 s->ua = addr + s->dbc;
905 case 1: /* IO or Read/Write instruction. */
906 opcode = (insn >> 27) & 7;
910 if (insn & (1 << 25)) {
911 id = read_dword(s, s->dsa + sxt24(insn));
915 id = (id >> 16) & 0xf;
916 if (insn & (1 << 26)) {
917 addr = s->dsp + sxt24(addr);
923 if (s->current_dma_len && (s->ssid & 0xf) == id) {
924 DPRINTF("Already reselected by target %d\n", id);
927 s->sstat0 |= LSI_SSTAT0_WOA;
928 s->scntl1 &= ~LSI_SCNTL1_IARB;
929 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
930 DPRINTF("Selected absent target %d\n", id);
931 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
935 DPRINTF("Selected target %d%s\n",
936 id, insn & (1 << 3) ? " ATN" : "");
937 /* ??? Linux drivers compain when this is set. Maybe
938 it only applies in low-level mode (unimplemented).
939 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
940 s->current_dev = s->scsi_dev[id];
941 s->current_tag = id << 8;
942 s->scntl1 |= LSI_SCNTL1_CON;
943 if (insn & (1 << 3)) {
944 s->socl |= LSI_SOCL_ATN;
946 lsi_set_phase(s, PHASE_MO);
948 case 1: /* Disconnect */
949 DPRINTF("Wait Disconect\n");
950 s->scntl1 &= ~LSI_SCNTL1_CON;
952 case 2: /* Wait Reselect */
953 lsi_wait_reselect(s);
956 DPRINTF("Set%s%s%s%s\n",
957 insn & (1 << 3) ? " ATN" : "",
958 insn & (1 << 6) ? " ACK" : "",
959 insn & (1 << 9) ? " TM" : "",
960 insn & (1 << 10) ? " CC" : "");
961 if (insn & (1 << 3)) {
962 s->socl |= LSI_SOCL_ATN;
963 lsi_set_phase(s, PHASE_MO);
965 if (insn & (1 << 9)) {
966 BADF("Target mode not implemented\n");
969 if (insn & (1 << 10))
973 DPRINTF("Clear%s%s%s%s\n",
974 insn & (1 << 3) ? " ATN" : "",
975 insn & (1 << 6) ? " ACK" : "",
976 insn & (1 << 9) ? " TM" : "",
977 insn & (1 << 10) ? " CC" : "");
978 if (insn & (1 << 3)) {
979 s->socl &= ~LSI_SOCL_ATN;
981 if (insn & (1 << 10))
992 static const char *opcode_names[3] =
993 {"Write", "Read", "Read-Modify-Write"};
994 static const char *operator_names[8] =
995 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
998 reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
999 data8 = (insn >> 8) & 0xff;
1000 opcode = (insn >> 27) & 7;
1001 operator = (insn >> 24) & 7;
1002 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1003 opcode_names[opcode - 5], reg,
1004 operator_names[operator], data8, s->sfbr,
1005 (insn & (1 << 23)) ? " SFBR" : "");
1008 case 5: /* From SFBR */
1012 case 6: /* To SFBR */
1014 op0 = lsi_reg_readb(s, reg);
1017 case 7: /* Read-modify-write */
1019 op0 = lsi_reg_readb(s, reg);
1020 if (insn & (1 << 23)) {
1032 case 1: /* Shift left */
1034 op0 = (op0 << 1) | s->carry;
1048 op0 = (op0 >> 1) | (s->carry << 7);
1052 s->carry = op0 < op1;
1055 op0 += op1 + s->carry;
1057 s->carry = op0 <= op1;
1059 s->carry = op0 < op1;
1064 case 5: /* From SFBR */
1065 case 7: /* Read-modify-write */
1066 lsi_reg_writeb(s, reg, op0);
1068 case 6: /* To SFBR */
1075 case 2: /* Transfer Control. */
1080 if ((insn & 0x002e0000) == 0) {
1084 if (s->sist1 & LSI_SIST1_STO) {
1085 DPRINTF("Delayed select timeout\n");
1089 cond = jmp = (insn & (1 << 19)) != 0;
1090 if (cond == jmp && (insn & (1 << 21))) {
1091 DPRINTF("Compare carry %d\n", s->carry == jmp);
1092 cond = s->carry != 0;
1094 if (cond == jmp && (insn & (1 << 17))) {
1095 DPRINTF("Compare phase %d %c= %d\n",
1096 (s->sstat1 & PHASE_MASK),
1098 ((insn >> 24) & 7));
1099 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1101 if (cond == jmp && (insn & (1 << 18))) {
1104 mask = (~insn >> 8) & 0xff;
1105 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1106 s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1107 cond = (s->sfbr & mask) == (insn & mask);
1110 if (insn & (1 << 23)) {
1111 /* Relative address. */
1112 addr = s->dsp + sxt24(addr);
1114 switch ((insn >> 27) & 7) {
1116 DPRINTF("Jump to 0x%08x\n", addr);
1120 DPRINTF("Call 0x%08x\n", addr);
1124 case 2: /* Return */
1125 DPRINTF("Return to 0x%08x\n", s->temp);
1128 case 3: /* Interrupt */
1129 DPRINTF("Interrupt 0x%08x\n", s->dsps);
1130 if ((insn & (1 << 20)) != 0) {
1131 s->istat0 |= LSI_ISTAT0_INTF;
1134 lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1138 DPRINTF("Illegal transfer control\n");
1139 lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1143 DPRINTF("Control condition failed\n");
1149 if ((insn & (1 << 29)) == 0) {
1152 /* ??? The docs imply the destination address is loaded into
1153 the TEMP register. However the Linux drivers rely on
1154 the value being presrved. */
1155 dest = read_dword(s, s->dsp);
1157 lsi_memcpy(s, dest, addr, insn & 0xffffff);
1164 if (insn & (1 << 28)) {
1165 addr = s->dsa + sxt24(addr);
1168 reg = (insn >> 16) & 0xff;
1169 if (insn & (1 << 24)) {
1170 cpu_physical_memory_read(addr, data, n);
1171 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1172 addr, *(int *)data);
1173 for (i = 0; i < n; i++) {
1174 lsi_reg_writeb(s, reg + i, data[i]);
1177 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1178 for (i = 0; i < n; i++) {
1179 data[i] = lsi_reg_readb(s, reg + i);
1181 cpu_physical_memory_write(addr, data, n);
1185 /* ??? Need to avoid infinite loops. */
1186 if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1187 if (s->dcntl & LSI_DCNTL_SSM) {
1188 lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1193 DPRINTF("SCRIPTS execution stopped\n");
1196 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1199 #define CASE_GET_REG32(name, addr) \
1200 case addr: return s->name & 0xff; \
1201 case addr + 1: return (s->name >> 8) & 0xff; \
1202 case addr + 2: return (s->name >> 16) & 0xff; \
1203 case addr + 3: return (s->name >> 24) & 0xff;
1205 #ifdef DEBUG_LSI_REG
1206 DPRINTF("Read reg %x\n", offset);
1209 case 0x00: /* SCNTL0 */
1211 case 0x01: /* SCNTL1 */
1213 case 0x02: /* SCNTL2 */
1215 case 0x03: /* SCNTL3 */
1217 case 0x04: /* SCID */
1219 case 0x05: /* SXFER */
1221 case 0x06: /* SDID */
1223 case 0x07: /* GPREG0 */
1225 case 0xa: /* SSID */
1227 case 0xb: /* SBCL */
1228 /* ??? This is not correct. However it's (hopefully) only
1229 used for diagnostics, so should be ok. */
1231 case 0xc: /* DSTAT */
1232 tmp = s->dstat | 0x80;
1233 if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1237 case 0x0d: /* SSTAT0 */
1239 case 0x0e: /* SSTAT1 */
1241 case 0x0f: /* SSTAT2 */
1242 return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1243 CASE_GET_REG32(dsa, 0x10)
1244 case 0x14: /* ISTAT0 */
1246 case 0x16: /* MBOX0 */
1248 case 0x17: /* MBOX1 */
1250 case 0x18: /* CTEST0 */
1252 case 0x19: /* CTEST1 */
1254 case 0x1a: /* CTEST2 */
1255 tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM;
1256 if (s->istat0 & LSI_ISTAT0_SIGP) {
1257 s->istat0 &= ~LSI_ISTAT0_SIGP;
1258 tmp |= LSI_CTEST2_SIGP;
1261 case 0x1b: /* CTEST3 */
1263 CASE_GET_REG32(temp, 0x1c)
1264 case 0x20: /* DFIFO */
1266 case 0x21: /* CTEST4 */
1268 case 0x22: /* CTEST5 */
1270 case 0x24: /* DBC[0:7] */
1271 return s->dbc & 0xff;
1272 case 0x25: /* DBC[8:15] */
1273 return (s->dbc >> 8) & 0xff;
1274 case 0x26: /* DBC[16->23] */
1275 return (s->dbc >> 16) & 0xff;
1276 case 0x27: /* DCMD */
1278 CASE_GET_REG32(dsp, 0x2c)
1279 CASE_GET_REG32(dsps, 0x30)
1280 CASE_GET_REG32(scratch[0], 0x34)
1281 case 0x38: /* DMODE */
1283 case 0x39: /* DIEN */
1285 case 0x3b: /* DCNTL */
1287 case 0x40: /* SIEN0 */
1289 case 0x41: /* SIEN1 */
1291 case 0x42: /* SIST0 */
1296 case 0x43: /* SIST1 */
1301 case 0x47: /* GPCNTL0 */
1303 case 0x48: /* STIME0 */
1305 case 0x4a: /* RESPID0 */
1307 case 0x4b: /* RESPID1 */
1309 case 0x4d: /* STEST1 */
1311 case 0x4e: /* STEST2 */
1313 case 0x4f: /* STEST3 */
1315 case 0x50: /* SIDL */
1316 /* This is needed by the linux drivers. We currently only update it
1317 during the MSG IN phase. */
1319 case 0x52: /* STEST4 */
1321 case 0x56: /* CCNTL0 */
1323 case 0x57: /* CCNTL1 */
1325 case 0x58: /* SBDL */
1326 /* Some drivers peek at the data bus during the MSG IN phase. */
1327 if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1330 case 0x59: /* SBDL high */
1332 CASE_GET_REG32(mmrs, 0xa0)
1333 CASE_GET_REG32(mmws, 0xa4)
1334 CASE_GET_REG32(sfs, 0xa8)
1335 CASE_GET_REG32(drs, 0xac)
1336 CASE_GET_REG32(sbms, 0xb0)
1337 CASE_GET_REG32(dmbs, 0xb4)
1338 CASE_GET_REG32(dnad64, 0xb8)
1339 CASE_GET_REG32(pmjad1, 0xc0)
1340 CASE_GET_REG32(pmjad2, 0xc4)
1341 CASE_GET_REG32(rbc, 0xc8)
1342 CASE_GET_REG32(ua, 0xcc)
1343 CASE_GET_REG32(ia, 0xd4)
1344 CASE_GET_REG32(sbc, 0xd8)
1345 CASE_GET_REG32(csbc, 0xdc)
1347 if (offset >= 0x5c && offset < 0xa0) {
1350 n = (offset - 0x58) >> 2;
1351 shift = (offset & 3) * 8;
1352 return (s->scratch[n] >> shift) & 0xff;
1354 BADF("readb 0x%x\n", offset);
1356 #undef CASE_GET_REG32
1359 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1361 #define CASE_SET_REG32(name, addr) \
1362 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1363 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1364 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1365 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1367 #ifdef DEBUG_LSI_REG
1368 DPRINTF("Write reg %x = %02x\n", offset, val);
1371 case 0x00: /* SCNTL0 */
1373 if (val & LSI_SCNTL0_START) {
1374 BADF("Start sequence not implemented\n");
1377 case 0x01: /* SCNTL1 */
1378 s->scntl1 = val & ~LSI_SCNTL1_SST;
1379 if (val & LSI_SCNTL1_IARB) {
1380 BADF("Immediate Arbritration not implemented\n");
1382 if (val & LSI_SCNTL1_RST) {
1383 s->sstat0 |= LSI_SSTAT0_RST;
1384 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1386 s->sstat0 &= ~LSI_SSTAT0_RST;
1389 case 0x02: /* SCNTL2 */
1390 val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1393 case 0x03: /* SCNTL3 */
1396 case 0x04: /* SCID */
1399 case 0x05: /* SXFER */
1402 case 0x06: /* SDID */
1403 if ((val & 0xf) != (s->ssid & 0xf))
1404 BADF("Destination ID does not match SSID\n");
1405 s->sdid = val & 0xf;
1407 case 0x07: /* GPREG0 */
1409 case 0x08: /* SFBR */
1410 /* The CPU is not allowed to write to this register. However the
1411 SCRIPTS register move instructions are. */
1414 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1415 /* Linux writes to these readonly registers on startup. */
1417 CASE_SET_REG32(dsa, 0x10)
1418 case 0x14: /* ISTAT0 */
1419 s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1420 if (val & LSI_ISTAT0_ABRT) {
1421 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1423 if (val & LSI_ISTAT0_INTF) {
1424 s->istat0 &= ~LSI_ISTAT0_INTF;
1427 if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1428 DPRINTF("Woken by SIGP\n");
1431 lsi_execute_script(s);
1433 if (val & LSI_ISTAT0_SRST) {
1436 case 0x16: /* MBOX0 */
1438 case 0x17: /* MBOX1 */
1440 case 0x1b: /* CTEST3 */
1441 s->ctest3 = val & 0x0f;
1443 CASE_SET_REG32(temp, 0x1c)
1444 case 0x21: /* CTEST4 */
1446 BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1450 case 0x22: /* CTEST5 */
1451 if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1452 BADF("CTEST5 DMA increment not implemented\n");
1456 case 0x2c: /* DSPS[0:7] */
1457 s->dsp &= 0xffffff00;
1460 case 0x2d: /* DSPS[8:15] */
1461 s->dsp &= 0xffff00ff;
1464 case 0x2e: /* DSPS[16:23] */
1465 s->dsp &= 0xff00ffff;
1466 s->dsp |= val << 16;
1468 case 0x2f: /* DSPS[14:31] */
1469 s->dsp &= 0x00ffffff;
1470 s->dsp |= val << 24;
1471 if ((s->dmode & LSI_DMODE_MAN) == 0
1472 && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1473 lsi_execute_script(s);
1475 CASE_SET_REG32(dsps, 0x30)
1476 CASE_SET_REG32(scratch[0], 0x34)
1477 case 0x38: /* DMODE */
1478 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1479 BADF("IO mappings not implemented\n");
1483 case 0x39: /* DIEN */
1487 case 0x3b: /* DCNTL */
1488 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1489 if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1490 lsi_execute_script(s);
1492 case 0x40: /* SIEN0 */
1496 case 0x41: /* SIEN1 */
1500 case 0x47: /* GPCNTL0 */
1502 case 0x48: /* STIME0 */
1505 case 0x49: /* STIME1 */
1507 DPRINTF("General purpose timer not implemented\n");
1508 /* ??? Raising the interrupt immediately seems to be sufficient
1509 to keep the FreeBSD driver happy. */
1510 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1513 case 0x4a: /* RESPID0 */
1516 case 0x4b: /* RESPID1 */
1519 case 0x4d: /* STEST1 */
1522 case 0x4e: /* STEST2 */
1524 BADF("Low level mode not implemented\n");
1528 case 0x4f: /* STEST3 */
1530 BADF("SCSI FIFO test mode not implemented\n");
1534 case 0x56: /* CCNTL0 */
1537 case 0x57: /* CCNTL1 */
1540 CASE_SET_REG32(mmrs, 0xa0)
1541 CASE_SET_REG32(mmws, 0xa4)
1542 CASE_SET_REG32(sfs, 0xa8)
1543 CASE_SET_REG32(drs, 0xac)
1544 CASE_SET_REG32(sbms, 0xb0)
1545 CASE_SET_REG32(dmbs, 0xb4)
1546 CASE_SET_REG32(dnad64, 0xb8)
1547 CASE_SET_REG32(pmjad1, 0xc0)
1548 CASE_SET_REG32(pmjad2, 0xc4)
1549 CASE_SET_REG32(rbc, 0xc8)
1550 CASE_SET_REG32(ua, 0xcc)
1551 CASE_SET_REG32(ia, 0xd4)
1552 CASE_SET_REG32(sbc, 0xd8)
1553 CASE_SET_REG32(csbc, 0xdc)
1555 if (offset >= 0x5c && offset < 0xa0) {
1558 n = (offset - 0x58) >> 2;
1559 shift = (offset & 3) * 8;
1560 s->scratch[n] &= ~(0xff << shift);
1561 s->scratch[n] |= (val & 0xff) << shift;
1563 BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1566 #undef CASE_SET_REG32
1569 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1571 LSIState *s = (LSIState *)opaque;
1573 lsi_reg_writeb(s, addr & 0xff, val);
1576 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1578 LSIState *s = (LSIState *)opaque;
1581 lsi_reg_writeb(s, addr, val & 0xff);
1582 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1585 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1587 LSIState *s = (LSIState *)opaque;
1590 lsi_reg_writeb(s, addr, val & 0xff);
1591 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1592 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1593 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1596 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1598 LSIState *s = (LSIState *)opaque;
1600 return lsi_reg_readb(s, addr & 0xff);
1603 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1605 LSIState *s = (LSIState *)opaque;
1609 val = lsi_reg_readb(s, addr);
1610 val |= lsi_reg_readb(s, addr + 1) << 8;
1614 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1616 LSIState *s = (LSIState *)opaque;
1619 val = lsi_reg_readb(s, addr);
1620 val |= lsi_reg_readb(s, addr + 1) << 8;
1621 val |= lsi_reg_readb(s, addr + 2) << 16;
1622 val |= lsi_reg_readb(s, addr + 3) << 24;
1626 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1632 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1638 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1640 LSIState *s = (LSIState *)opaque;
1645 newval = s->script_ram[addr >> 2];
1646 shift = (addr & 3) * 8;
1647 newval &= ~(0xff << shift);
1648 newval |= val << shift;
1649 s->script_ram[addr >> 2] = newval;
1652 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1654 LSIState *s = (LSIState *)opaque;
1658 newval = s->script_ram[addr >> 2];
1660 newval = (newval & 0xffff) | (val << 16);
1662 newval = (newval & 0xffff0000) | val;
1664 s->script_ram[addr >> 2] = newval;
1668 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1670 LSIState *s = (LSIState *)opaque;
1673 s->script_ram[addr >> 2] = val;
1676 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1678 LSIState *s = (LSIState *)opaque;
1682 val = s->script_ram[addr >> 2];
1683 val >>= (addr & 3) * 8;
1687 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1689 LSIState *s = (LSIState *)opaque;
1693 val = s->script_ram[addr >> 2];
1696 return le16_to_cpu(val);
1699 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1701 LSIState *s = (LSIState *)opaque;
1704 return le32_to_cpu(s->script_ram[addr >> 2]);
1707 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1713 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1719 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1721 LSIState *s = (LSIState *)opaque;
1722 return lsi_reg_readb(s, addr & 0xff);
1725 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1727 LSIState *s = (LSIState *)opaque;
1730 val = lsi_reg_readb(s, addr);
1731 val |= lsi_reg_readb(s, addr + 1) << 8;
1735 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1737 LSIState *s = (LSIState *)opaque;
1740 val = lsi_reg_readb(s, addr);
1741 val |= lsi_reg_readb(s, addr + 1) << 8;
1742 val |= lsi_reg_readb(s, addr + 2) << 16;
1743 val |= lsi_reg_readb(s, addr + 3) << 24;
1747 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1749 LSIState *s = (LSIState *)opaque;
1750 lsi_reg_writeb(s, addr & 0xff, val);
1753 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1755 LSIState *s = (LSIState *)opaque;
1757 lsi_reg_writeb(s, addr, val & 0xff);
1758 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1761 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1763 LSIState *s = (LSIState *)opaque;
1765 lsi_reg_writeb(s, addr, val & 0xff);
1766 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1767 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1768 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1771 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1772 uint32_t addr, uint32_t size, int type)
1774 LSIState *s = (LSIState *)pci_dev;
1776 DPRINTF("Mapping IO at %08x\n", addr);
1778 register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1779 register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1780 register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1781 register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1782 register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1783 register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1786 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1787 uint32_t addr, uint32_t size, int type)
1789 LSIState *s = (LSIState *)pci_dev;
1791 DPRINTF("Mapping ram at %08x\n", addr);
1792 s->script_ram_base = addr;
1793 cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1796 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1797 uint32_t addr, uint32_t size, int type)
1799 LSIState *s = (LSIState *)pci_dev;
1801 DPRINTF("Mapping registers at %08x\n", addr);
1802 cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1805 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1807 LSIState *s = (LSIState *)opaque;
1810 for (id = 0; id < LSI_MAX_DEVS; id++) {
1811 if (s->scsi_dev[id] == NULL)
1815 if (id >= LSI_MAX_DEVS) {
1816 BADF("Bad Device ID %d\n", id);
1819 if (s->scsi_dev[id]) {
1820 DPRINTF("Destroying device %d\n", id);
1821 scsi_disk_destroy(s->scsi_dev[id]);
1823 DPRINTF("Attaching block device %d\n", id);
1824 s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1827 void *lsi_scsi_init(PCIBus *bus, int devfn)
1831 s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1832 sizeof(*s), devfn, NULL, NULL);
1834 fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1838 s->pci_dev.config[0x00] = 0x00;
1839 s->pci_dev.config[0x01] = 0x10;
1840 s->pci_dev.config[0x02] = 0x12;
1841 s->pci_dev.config[0x03] = 0x00;
1842 s->pci_dev.config[0x0b] = 0x01;
1843 s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1845 s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1846 lsi_mmio_writefn, s);
1847 s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1848 lsi_ram_writefn, s);
1850 pci_register_io_region((struct PCIDevice *)s, 0, 256,
1851 PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1852 pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1853 PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1854 pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1855 PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1856 s->queue = qemu_malloc(sizeof(lsi_queue));
1858 s->active_commands = 0;