2 * QEMU SPARC iommu emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #define DPRINTF(fmt, args...) \
31 do { printf("IOMMU: " fmt , ##args); } while (0)
33 #define DPRINTF(fmt, args...)
36 #define IOMMU_NREGS (3*4096)
37 #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
38 #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
39 #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
40 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
41 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
42 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
43 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
44 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
45 #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
46 #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
47 #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
48 #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
50 /* The format of an iopte in the page tables */
51 #define IOPTE_PAGE 0x07ffff00 /* Physical page number (PA[30:12]) */
52 #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or Viking/MXCC) */
53 #define IOPTE_WRITE 0x00000004 /* Writeable */
54 #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
55 #define IOPTE_WAZ 0x00000001 /* Write as zeros */
58 #define PAGE_SIZE (1 << PAGE_SHIFT)
59 #define PAGE_MASK (PAGE_SIZE - 1)
61 typedef struct IOMMUState {
63 uint32_t regs[IOMMU_NREGS];
67 static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
69 IOMMUState *s = opaque;
72 saddr = (addr - s->addr) >> 2;
75 DPRINTF("read reg[%d] = %x\n", saddr, s->regs[saddr]);
76 return s->regs[saddr];
82 static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
84 IOMMUState *s = opaque;
87 saddr = (addr - s->addr) >> 2;
88 DPRINTF("write reg[%d] = %x\n", saddr, val);
91 switch (val & IOMMU_CTRL_RNGE) {
93 s->iostart = 0xff000000;
96 s->iostart = 0xfe000000;
99 s->iostart = 0xfc000000;
101 case IOMMU_RNGE_128MB:
102 s->iostart = 0xf8000000;
104 case IOMMU_RNGE_256MB:
105 s->iostart = 0xf0000000;
107 case IOMMU_RNGE_512MB:
108 s->iostart = 0xe0000000;
111 s->iostart = 0xc0000000;
115 s->iostart = 0x80000000;
118 DPRINTF("iostart = %x\n", s->iostart);
121 s->regs[saddr] = val;
126 static CPUReadMemoryFunc *iommu_mem_read[3] = {
132 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
138 uint32_t iommu_translate_local(void *opaque, uint32_t addr)
140 IOMMUState *s = opaque;
141 uint32_t iopte, pa, tmppte;
143 iopte = s->regs[1] << 4;
145 iopte += (addr >> (PAGE_SHIFT - 2)) & ~3;
146 cpu_physical_memory_read(iopte, (void *) &pa, 4);
149 pa = ((pa & IOPTE_PAGE) << 4) + (addr & PAGE_MASK);
150 DPRINTF("xlate dva %x => pa %x (iopte[%x] = %x)\n", addr, pa, iopte, tmppte);
154 static void iommu_save(QEMUFile *f, void *opaque)
156 IOMMUState *s = opaque;
159 qemu_put_be32s(f, &s->addr);
160 for (i = 0; i < IOMMU_NREGS; i++)
161 qemu_put_be32s(f, &s->regs[i]);
162 qemu_put_be32s(f, &s->iostart);
165 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
167 IOMMUState *s = opaque;
173 qemu_get_be32s(f, &s->addr);
174 for (i = 0; i < IOMMU_NREGS; i++)
175 qemu_put_be32s(f, &s->regs[i]);
176 qemu_get_be32s(f, &s->iostart);
181 static void iommu_reset(void *opaque)
183 IOMMUState *s = opaque;
185 memset(s->regs, 0, IOMMU_NREGS * 4);
189 void *iommu_init(uint32_t addr)
194 s = qemu_mallocz(sizeof(IOMMUState));
200 iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
201 cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
203 register_savevm("iommu", addr, 1, iommu_save, iommu_load, s);
204 qemu_register_reset(iommu_reset, s);