2 * QEMU 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
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29 //#define DEBUG_IRQ_LATENCY
30 //#define DEBUG_IRQ_COUNT
32 typedef struct PicState {
33 uint8_t last_irr; /* edge detection */
34 uint8_t irr; /* interrupt request register */
35 uint8_t imr; /* interrupt mask register */
36 uint8_t isr; /* interrupt service register */
37 uint8_t priority_add; /* highest irq priority */
39 uint8_t read_reg_select;
44 uint8_t rotate_on_auto_eoi;
45 uint8_t special_fully_nested_mode;
46 uint8_t init4; /* true if 4 byte init */
47 uint8_t elcr; /* PIIX edge/trigger selection*/
49 PicState2 *pics_state;
53 /* 0 is master pic, 1 is slave pic */
54 /* XXX: better separation between the two pics */
56 IRQRequestFunc *irq_request;
57 void *irq_request_opaque;
58 /* IOAPIC callback support */
59 SetIRQFunc *alt_irq_func;
63 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
64 static int irq_level[16];
66 #ifdef DEBUG_IRQ_COUNT
67 static uint64_t irq_count[16];
70 /* set irq level. If an edge is detected, then the IRR is set to 1 */
71 static inline void pic_set_irq1(PicState *s, int irq, int level)
87 if ((s->last_irr & mask) == 0)
96 /* return the highest priority found in mask (highest = smallest
97 number). Return 8 if no irq */
98 static inline int get_priority(PicState *s, int mask)
104 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
109 /* return the pic wanted interrupt. return -1 if none */
110 static int pic_get_irq(PicState *s)
112 int mask, cur_priority, priority;
114 mask = s->irr & ~s->imr;
115 priority = get_priority(s, mask);
118 /* compute current priority. If special fully nested mode on the
119 master, the IRQ coming from the slave is not taken into account
120 for the priority computation. */
122 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
124 cur_priority = get_priority(s, mask);
125 if (priority < cur_priority) {
126 /* higher priority found: an irq should be generated */
127 return (priority + s->priority_add) & 7;
133 /* raise irq to CPU if necessary. must be called every time the active
135 /* XXX: should not export it, but it is needed for an APIC kludge */
136 void pic_update_irq(PicState2 *s)
140 /* first look at slave pic */
141 irq2 = pic_get_irq(&s->pics[1]);
143 /* if irq request by slave pic, signal master PIC */
144 pic_set_irq1(&s->pics[0], 2, 1);
145 pic_set_irq1(&s->pics[0], 2, 0);
147 /* look at requested irq */
148 irq = pic_get_irq(&s->pics[0]);
150 #if defined(DEBUG_PIC)
153 for(i = 0; i < 2; i++) {
154 printf("pic%d: imr=%x irr=%x padd=%d\n",
155 i, s->pics[i].imr, s->pics[i].irr,
156 s->pics[i].priority_add);
160 printf("pic: cpu_interrupt\n");
162 s->irq_request(s->irq_request_opaque, 1);
165 /* all targets should do this rather than acking the IRQ in the cpu */
166 #if defined(TARGET_MIPS)
168 s->irq_request(s->irq_request_opaque, 0);
173 #ifdef DEBUG_IRQ_LATENCY
174 int64_t irq_time[16];
177 void pic_set_irq_new(void *opaque, int irq, int level)
179 PicState2 *s = opaque;
181 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
182 if (level != irq_level[irq]) {
183 #if defined(DEBUG_PIC)
184 printf("pic_set_irq: irq=%d level=%d\n", irq, level);
186 irq_level[irq] = level;
187 #ifdef DEBUG_IRQ_COUNT
193 #ifdef DEBUG_IRQ_LATENCY
195 irq_time[irq] = qemu_get_clock(vm_clock);
198 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
199 /* used for IOAPIC irqs */
201 s->alt_irq_func(s->alt_irq_opaque, irq, level);
205 /* obsolete function */
206 void pic_set_irq(int irq, int level)
208 pic_set_irq_new(isa_pic, irq, level);
211 /* acknowledge interrupt 'irq' */
212 static inline void pic_intack(PicState *s, int irq)
215 if (s->rotate_on_auto_eoi)
216 s->priority_add = (irq + 1) & 7;
218 s->isr |= (1 << irq);
220 /* We don't clear a level sensitive interrupt here */
221 if (!(s->elcr & (1 << irq)))
222 s->irr &= ~(1 << irq);
225 int pic_read_irq(PicState2 *s)
227 int irq, irq2, intno;
229 irq = pic_get_irq(&s->pics[0]);
231 pic_intack(&s->pics[0], irq);
233 irq2 = pic_get_irq(&s->pics[1]);
235 pic_intack(&s->pics[1], irq2);
237 /* spurious IRQ on slave controller */
240 intno = s->pics[1].irq_base + irq2;
243 intno = s->pics[0].irq_base + irq;
246 /* spurious IRQ on host controller */
248 intno = s->pics[0].irq_base + irq;
252 #ifdef DEBUG_IRQ_LATENCY
253 printf("IRQ%d latency=%0.3fus\n",
255 (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
257 #if defined(DEBUG_PIC)
258 printf("pic_interrupt: irq=%d\n", irq);
263 static void pic_reset(void *opaque)
265 PicState *s = opaque;
273 s->read_reg_select = 0;
278 s->rotate_on_auto_eoi = 0;
279 s->special_fully_nested_mode = 0;
281 /* Note: ELCR is not reset */
284 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
286 PicState *s = opaque;
287 int priority, cmd, irq;
290 printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
297 /* deassert a pending interrupt */
298 s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
302 hw_error("single mode not supported");
304 hw_error("level sensitive irq not supported");
305 } else if (val & 0x08) {
309 s->read_reg_select = val & 1;
311 s->special_mask = (val >> 5) & 1;
317 s->rotate_on_auto_eoi = cmd >> 2;
319 case 1: /* end of interrupt */
321 priority = get_priority(s, s->isr);
323 irq = (priority + s->priority_add) & 7;
324 s->isr &= ~(1 << irq);
326 s->priority_add = (irq + 1) & 7;
327 pic_update_irq(s->pics_state);
332 s->isr &= ~(1 << irq);
333 pic_update_irq(s->pics_state);
336 s->priority_add = (val + 1) & 7;
337 pic_update_irq(s->pics_state);
341 s->isr &= ~(1 << irq);
342 s->priority_add = (irq + 1) & 7;
343 pic_update_irq(s->pics_state);
351 switch(s->init_state) {
355 pic_update_irq(s->pics_state);
358 s->irq_base = val & 0xf8;
369 s->special_fully_nested_mode = (val >> 4) & 1;
370 s->auto_eoi = (val >> 1) & 1;
377 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
381 ret = pic_get_irq(s);
384 s->pics_state->pics[0].isr &= ~(1 << 2);
385 s->pics_state->pics[0].irr &= ~(1 << 2);
387 s->irr &= ~(1 << ret);
388 s->isr &= ~(1 << ret);
389 if (addr1 >> 7 || ret != 2)
390 pic_update_irq(s->pics_state);
393 pic_update_irq(s->pics_state);
399 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
401 PicState *s = opaque;
408 ret = pic_poll_read(s, addr1);
412 if (s->read_reg_select)
421 printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
426 /* memory mapped interrupt status */
427 /* XXX: may be the same than pic_read_irq() */
428 uint32_t pic_intack_read(PicState2 *s)
432 ret = pic_poll_read(&s->pics[0], 0x00);
434 ret = pic_poll_read(&s->pics[1], 0x80) + 8;
435 /* Prepare for ISR read */
436 s->pics[0].read_reg_select = 1;
441 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
443 PicState *s = opaque;
444 s->elcr = val & s->elcr_mask;
447 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
449 PicState *s = opaque;
453 static void pic_save(QEMUFile *f, void *opaque)
455 PicState *s = opaque;
457 qemu_put_8s(f, &s->last_irr);
458 qemu_put_8s(f, &s->irr);
459 qemu_put_8s(f, &s->imr);
460 qemu_put_8s(f, &s->isr);
461 qemu_put_8s(f, &s->priority_add);
462 qemu_put_8s(f, &s->irq_base);
463 qemu_put_8s(f, &s->read_reg_select);
464 qemu_put_8s(f, &s->poll);
465 qemu_put_8s(f, &s->special_mask);
466 qemu_put_8s(f, &s->init_state);
467 qemu_put_8s(f, &s->auto_eoi);
468 qemu_put_8s(f, &s->rotate_on_auto_eoi);
469 qemu_put_8s(f, &s->special_fully_nested_mode);
470 qemu_put_8s(f, &s->init4);
471 qemu_put_8s(f, &s->elcr);
474 static int pic_load(QEMUFile *f, void *opaque, int version_id)
476 PicState *s = opaque;
481 qemu_get_8s(f, &s->last_irr);
482 qemu_get_8s(f, &s->irr);
483 qemu_get_8s(f, &s->imr);
484 qemu_get_8s(f, &s->isr);
485 qemu_get_8s(f, &s->priority_add);
486 qemu_get_8s(f, &s->irq_base);
487 qemu_get_8s(f, &s->read_reg_select);
488 qemu_get_8s(f, &s->poll);
489 qemu_get_8s(f, &s->special_mask);
490 qemu_get_8s(f, &s->init_state);
491 qemu_get_8s(f, &s->auto_eoi);
492 qemu_get_8s(f, &s->rotate_on_auto_eoi);
493 qemu_get_8s(f, &s->special_fully_nested_mode);
494 qemu_get_8s(f, &s->init4);
495 qemu_get_8s(f, &s->elcr);
499 /* XXX: add generic master/slave system */
500 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
502 register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
503 register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
504 if (elcr_addr >= 0) {
505 register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
506 register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
508 register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
509 qemu_register_reset(pic_reset, s);
521 s = &isa_pic->pics[i];
522 term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
523 i, s->irr, s->imr, s->isr, s->priority_add,
524 s->irq_base, s->read_reg_select, s->elcr,
525 s->special_fully_nested_mode);
531 #ifndef DEBUG_IRQ_COUNT
532 term_printf("irq statistic code not compiled.\n");
537 term_printf("IRQ statistics:\n");
538 for (i = 0; i < 16; i++) {
539 count = irq_count[i];
541 term_printf("%2d: %" PRId64 "\n", i, count);
546 PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
549 s = qemu_mallocz(sizeof(PicState2));
552 pic_init1(0x20, 0x4d0, &s->pics[0]);
553 pic_init1(0xa0, 0x4d1, &s->pics[1]);
554 s->pics[0].elcr_mask = 0xf8;
555 s->pics[1].elcr_mask = 0xde;
556 s->irq_request = irq_request;
557 s->irq_request_opaque = irq_request_opaque;
558 s->pics[0].pics_state = s;
559 s->pics[1].pics_state = s;
563 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
564 void *alt_irq_opaque)
566 s->alt_irq_func = alt_irq_func;
567 s->alt_irq_opaque = alt_irq_opaque;