4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #define DPRINTF(fmt, args...) \
31 do { printf("ESP: " fmt , ##args); } while (0)
33 #define DPRINTF(fmt, args...)
37 #define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1)
38 #define ESP_MAXREG 0x3f
40 typedef struct ESPState {
41 BlockDriverState **bd;
42 uint8_t rregs[ESP_MAXREG];
43 uint8_t wregs[ESP_MAXREG];
45 uint32_t espdmaregs[ESPDMA_REGS];
48 uint8_t ti_buf[65536];
68 static void handle_satn(ESPState *s)
71 uint32_t dmaptr, dmalen;
76 dmaptr = iommu_translate(s->espdmaregs[1]);
77 dmalen = s->wregs[0] | (s->wregs[1] << 8);
78 DPRINTF("Select with ATN at %8.8x len %d\n", dmaptr, dmalen);
79 DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r');
80 cpu_physical_memory_read(dmaptr, buf, dmalen);
81 for (i = 0; i < dmalen; i++) {
82 DPRINTF("Command %2.2x\n", buf[i]);
86 target = s->wregs[4] & 7;
88 if (target > 4 || !s->bd[target]) { // No such drive
89 s->rregs[4] = STAT_IN;
90 s->rregs[5] = INTR_DC;
92 s->espdmaregs[0] |= 1;
93 pic_set_irq(s->irq, 1);
98 DPRINTF("Test Unit Ready (len %d)\n", buf[5]);
101 DPRINTF("Inquiry (len %d)\n", buf[5]);
102 memset(s->ti_buf, 0, 36);
103 if (bdrv_get_type_hint(s->bd[target]) == BDRV_TYPE_CDROM) {
105 memcpy(&s->ti_buf[16], "QEMU CDROM ", 16);
108 memcpy(&s->ti_buf[16], "QEMU HARDDISK ", 16);
110 memcpy(&s->ti_buf[8], "QEMU ", 8);
117 DPRINTF("Mode Sense(6) (page %d, len %d)\n", buf[3], buf[5]);
120 DPRINTF("Read Capacity (len %d)\n", buf[5]);
121 memset(s->ti_buf, 0, 8);
122 bdrv_get_geometry(s->bd[target], &nb_sectors);
123 s->ti_buf[0] = (nb_sectors >> 24) & 0xff;
124 s->ti_buf[1] = (nb_sectors >> 16) & 0xff;
125 s->ti_buf[2] = (nb_sectors >> 8) & 0xff;
126 s->ti_buf[3] = nb_sectors & 0xff;
138 offset = (buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6];
139 len = (buf[8] << 8) | buf[9];
140 DPRINTF("Read (10) (offset %lld len %lld)\n", offset, len);
141 bdrv_read(s->bd[target], offset, s->ti_buf, len);
143 s->ti_size = len * 512;
150 offset = (buf[3] << 24) | (buf[4] << 16) | (buf[5] << 8) | buf[6];
151 len = (buf[8] << 8) | buf[9];
152 DPRINTF("Write (10) (offset %lld len %lld)\n", offset, len);
153 bdrv_write(s->bd[target], offset, s->ti_buf, len);
155 s->ti_size = len * 512;
159 DPRINTF("Unknown command (%2.2x)\n", buf[1]);
162 s->rregs[4] = STAT_IN | STAT_TC | STAT_DI;
163 s->rregs[5] = INTR_BS | INTR_FC;
164 s->rregs[6] = SEQ_CD;
165 s->espdmaregs[0] |= 1;
166 pic_set_irq(s->irq, 1);
169 static void dma_write(ESPState *s, const uint8_t *buf, uint32_t len)
171 uint32_t dmaptr, dmalen;
173 dmaptr = iommu_translate(s->espdmaregs[1]);
174 dmalen = s->wregs[0] | (s->wregs[1] << 8);
175 DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r');
176 cpu_physical_memory_write(dmaptr, buf, len);
177 s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
178 s->rregs[5] = INTR_BS | INTR_FC;
179 s->rregs[6] = SEQ_CD;
180 s->espdmaregs[0] |= 1;
181 pic_set_irq(s->irq, 1);
184 static const uint8_t okbuf[] = {0, 0};
186 static void handle_ti(ESPState *s)
188 uint32_t dmaptr, dmalen;
191 dmaptr = iommu_translate(s->espdmaregs[1]);
192 dmalen = s->wregs[0] | (s->wregs[1] << 8);
193 DPRINTF("Transfer Information at %8.8x len %d\n", dmaptr, dmalen);
194 DPRINTF("DMA Direction: %c\n", s->espdmaregs[0] & 0x100? 'w': 'r');
195 for (i = 0; i < s->ti_size; i++) {
196 dmaptr = iommu_translate(s->espdmaregs[1] + i);
198 cpu_physical_memory_write(dmaptr, &s->ti_buf[i], 1);
200 cpu_physical_memory_read(dmaptr, &s->ti_buf[i], 1);
202 s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
203 s->rregs[5] = INTR_BS;
205 s->espdmaregs[0] |= 1;
206 pic_set_irq(s->irq, 1);
209 static void esp_reset(void *opaque)
211 ESPState *s = opaque;
212 memset(s->rregs, 0, ESP_MAXREG);
213 s->rregs[0x0e] = 0x4; // Indicate fas100a
214 memset(s->espdmaregs, 0, ESPDMA_REGS * 4);
217 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
219 ESPState *s = opaque;
222 saddr = (addr & ESP_MAXREG) >> 2;
227 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
228 return s->rregs[saddr];
231 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
233 ESPState *s = opaque;
236 saddr = (addr & ESP_MAXREG) >> 2;
237 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
243 DPRINTF("NOP (%2.2x)\n", val);
246 DPRINTF("Flush FIFO (%2.2x)\n", val);
248 s->rregs[5] = INTR_FC;
251 DPRINTF("Chip reset (%2.2x)\n", val);
255 DPRINTF("Bus reset (%2.2x)\n", val);
261 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
262 dma_write(s, okbuf, 2);
265 DPRINTF("Message Accepted (%2.2x)\n", val);
266 dma_write(s, okbuf, 2);
267 s->rregs[5] = INTR_DC;
271 DPRINTF("Set ATN (%2.2x)\n", val);
277 DPRINTF("Set ATN & stop (%2.2x)\n", val);
281 DPRINTF("Unhandled command (%2.2x)\n", val);
291 s->wregs[saddr] = val;
294 static CPUReadMemoryFunc *esp_mem_read[3] = {
300 static CPUWriteMemoryFunc *esp_mem_write[3] = {
306 static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr)
308 ESPState *s = opaque;
311 saddr = (addr & ESPDMA_MAXADDR) >> 2;
312 DPRINTF("read dmareg[%d]: 0x%2.2x\n", saddr, s->espdmaregs[saddr]);
313 return s->espdmaregs[saddr];
316 static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
318 ESPState *s = opaque;
321 saddr = (addr & ESPDMA_MAXADDR) >> 2;
322 DPRINTF("write dmareg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->espdmaregs[saddr], val);
326 pic_set_irq(s->irq, 0);
331 s->espdmaregs[saddr] = val;
334 static CPUReadMemoryFunc *espdma_mem_read[3] = {
340 static CPUWriteMemoryFunc *espdma_mem_write[3] = {
346 static void esp_save(QEMUFile *f, void *opaque)
348 ESPState *s = opaque;
351 qemu_put_buffer(f, s->rregs, ESP_MAXREG);
352 qemu_put_buffer(f, s->wregs, ESP_MAXREG);
353 qemu_put_be32s(f, &s->irq);
354 for (i = 0; i < ESPDMA_REGS; i++)
355 qemu_put_be32s(f, &s->espdmaregs[i]);
358 static int esp_load(QEMUFile *f, void *opaque, int version_id)
360 ESPState *s = opaque;
366 qemu_get_buffer(f, s->rregs, ESP_MAXREG);
367 qemu_get_buffer(f, s->wregs, ESP_MAXREG);
368 qemu_get_be32s(f, &s->irq);
369 for (i = 0; i < ESPDMA_REGS; i++)
370 qemu_get_be32s(f, &s->espdmaregs[i]);
375 void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr)
378 int esp_io_memory, espdma_io_memory;
380 s = qemu_mallocz(sizeof(ESPState));
387 esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
388 cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
390 espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
391 cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
395 register_savevm("esp", espaddr, 1, esp_save, esp_load, s);
396 qemu_register_reset(esp_reset, s);